Jason 558f49cd4a Add 8 Verilog testbenches with full coverage (144/144 pass) ...

Testbenches for: edge_detector (17), nco_400m (20), cic_decimator (14),
fir_lowpass (13), freq_matched_filter (14), ddc_400m full-chain (7),
chirp_controller (39), chirp_contract regression (20).

Includes CSV output data for waveform verification.
Add .gitignore to exclude VCD/VVP build artifacts.

2026-03-15 06:14:11 +02:00

..

tb

Add 8 Verilog testbenches with full coverage (144/144 pass)

2026-03-15 06:14:11 +02:00

ad9484_interface_400m.v

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2026-03-09 00:17:39 +00:00

cdc_modules.v

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2026-03-09 00:17:39 +00:00

chirp_lut_init.v

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2026-03-09 00:17:39 +00:00

chirp_memory_loader_param.v

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2026-03-09 00:17:39 +00:00

cic_decimator_4x_enhanced.v

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2026-03-09 00:17:39 +00:00

cntrt.xdc

Create cntrt.xdc

2026-03-10 02:42:15 +00:00

dac_interface_single.v

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2026-03-09 00:17:39 +00:00

ddc_400m.v

Fix 6 RTL bugs in FPGA signal processing chain

2026-03-15 06:14:04 +02:00

ddc_input_interface.v

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2026-03-09 00:17:39 +00:00

doppler_processor.v

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edge_detector.v

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2026-03-09 00:17:39 +00:00

fft_1024_forward.v

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fft_1024_inverse.v

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2026-03-09 00:17:39 +00:00

fir_lowpass.v

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2026-03-09 00:17:39 +00:00

frequency_matched_filter.v

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latency_buffer_2159.v

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2026-03-09 00:17:39 +00:00

level_shifter_interface.v

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2026-03-10 01:31:50 +00:00

long_chirp_seg0_i.mem

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2026-03-09 00:17:39 +00:00

long_chirp_seg0_q.mem

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2026-03-09 00:17:39 +00:00

long_chirp_seg1_i.mem

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2026-03-09 00:17:39 +00:00

long_chirp_seg1_q.mem

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long_chirp_seg2_i.mem

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long_chirp_seg2_q.mem

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2026-03-09 00:17:39 +00:00

lvds_to_cmos_400m.v

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2026-03-09 00:17:39 +00:00

matched_filter_multi_segment.v

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2026-03-09 00:17:39 +00:00

nco_400m_enhanced.v

Fix 6 RTL bugs in FPGA signal processing chain

2026-03-15 06:14:04 +02:00

plfm_chirp_controller.v

Fix 6 RTL bugs in FPGA signal processing chain

2026-03-15 06:14:04 +02:00

radar_receiver_final.v

Fix 6 RTL bugs in FPGA signal processing chain

2026-03-15 06:14:04 +02:00

radar_system_tb.v

Create radar_system_tb.v

2026-03-10 01:35:26 +00:00

radar_system_top.v

Fix 6 RTL bugs in FPGA signal processing chain

2026-03-15 06:14:04 +02:00

radar_transmitter.v

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2026-03-09 00:17:39 +00:00

short_chirp_i.mem

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2026-03-09 00:17:39 +00:00

short_chirp_q.mem

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2026-03-09 00:17:39 +00:00

usb_data_interface.v

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2026-03-10 01:23:26 +00:00

usb_packet_analyzer.v

Create usb_packet_analyzer.v

2026-03-10 01:36:04 +00:00