Jason 3d0ee50999 fix(fpga): reset chirp_counter at DONE; source CHIRP_MAX from radar_params ...

C-3: plfm_chirp_controller_enhanced never reset chirp_counter when the
frame completed. Counter sat at CHIRP_MAX after frame 1, so the
LONG_LISTEN -> GUARD transition guard (== CHIRP_MAX/2-1) never matched
correctly on subsequent frames and frame 2+ ran extra chirps until the
6-bit counter wrapped. Reset chirp_counter in the DONE state.

S-2: Replace hardcoded CHIRP_MAX = 32 with RP_CHIRPS_PER_FRAME from
radar_params.vh so the TX FSM tracks the single source of truth.

S-1: Correct misleading labels in tb_system_e2e G14.1-G14.3. Per
radar_params.vh the range_mode encoding is 2'b00 = 3 km, 2'b01 =
long-range, 2'b10/2'b11 = reserved. The TB strings previously called
2'b01 "short" and 2'b10 "long", which is inverted and inconsistent
with the RTL comments in radar_mode_controller.v.

Regression: 32/32 PASS.

2026-04-22 19:34:09 +05:45

..

constraints

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

formal

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scripts

Revert "fix(fpga): F-0.9 option A — BUFIO+BUFR for 50T ft_clkout (SRCC pin)"

2026-04-20 21:47:19 +05:45

tb

fix(fpga): reset chirp_counter at DONE; source CHIRP_MAX from radar_params

2026-04-22 19:34:09 +05:45

.gitignore

chore(fpga): untrack TB-generated CSV, ignore a.out

2026-04-22 13:36:03 +05:45

ad9484_interface_400m.v

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

adc_clk_mmcm_integration.md

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adc_clk_mmcm.v

fix: FPGA timing margins (WNS +0.002→+0.080ns) + 11 bug fixes from code review

2026-04-14 00:08:26 +05:45

cdc_modules.v

fix(pre-bringup): second-batch P1/P2/P3 audit findings

2026-04-20 14:28:22 +05:45

cfar_ca.v

feat(fpga): integrate 2048-pt FFT upgrade — non-conflicting RTL (wave 1/3)

2026-04-21 01:52:32 +05:45

chirp_memory_loader_param.v

feat(fpga): integrate 2048-pt FFT upgrade — non-conflicting RTL (wave 1/3)

2026-04-21 01:52:32 +05:45

cic_decimator_4x_enhanced.v

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

dac_interface_single.v

…

ddc_400m.v

fix(pre-bringup): second-batch P1/P2/P3 audit findings

2026-04-20 14:28:22 +05:45

ddc_input_interface.v

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doppler_processor.v

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

edge_detector.v

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fft_engine.v

feat(fpga): integrate 2048-pt FFT upgrade — non-conflicting RTL (wave 1/3)

2026-04-21 01:52:32 +05:45

fft_twiddle_16.mem

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fft_twiddle_1024.mem

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fft_twiddle_2048.mem

feat(fpga): integrate 2048-pt FFT upgrade — non-conflicting RTL (wave 1/3)

2026-04-21 01:52:32 +05:45

fir_lowpass.v

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fpga_self_test.v

fix: FPGA timing margins (WNS +0.002→+0.080ns) + 11 bug fixes from code review

2026-04-14 00:08:26 +05:45

frequency_matched_filter.v

…

latency_buffer.v

…

long_chirp_lut.mem

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long_chirp_seg0_i.mem

feat(fpga): integrate 2048-pt FFT upgrade — non-conflicting RTL (wave 1/3)

2026-04-21 01:52:32 +05:45

long_chirp_seg0_q.mem

feat(fpga): integrate 2048-pt FFT upgrade — non-conflicting RTL (wave 1/3)

2026-04-21 01:52:32 +05:45

long_chirp_seg1_i.mem

feat(fpga): integrate 2048-pt FFT upgrade — non-conflicting RTL (wave 1/3)

2026-04-21 01:52:32 +05:45

long_chirp_seg1_q.mem

feat(fpga): integrate 2048-pt FFT upgrade — non-conflicting RTL (wave 1/3)

2026-04-21 01:52:32 +05:45

matched_filter_multi_segment.v

feat(fpga): integrate 2048-pt FFT upgrade — non-conflicting RTL (wave 1/3)

2026-04-21 01:52:32 +05:45

matched_filter_processing_chain.v

feat(fpga): integrate 2048-pt FFT upgrade — non-conflicting RTL (wave 1/3)

2026-04-21 01:52:32 +05:45

mti_canceller.v

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

nco_400m_enhanced.v

fix(fpga): registered reset fan-out at 400 MHz; default USB to FT2232H

2026-04-18 20:34:52 +05:45

plfm_chirp_controller.v

fix(fpga): reset chirp_counter at DONE; source CHIRP_MAX from radar_params

2026-04-22 19:34:09 +05:45

radar_mode_controller.v

feat(fpga): integrate 2048-pt FFT upgrade — non-conflicting RTL (wave 1/3)

2026-04-21 01:52:32 +05:45

radar_params.vh

feat(fpga): integrate 2048-pt FFT upgrade — non-conflicting RTL (wave 1/3)

2026-04-21 01:52:32 +05:45

radar_receiver_final.v

fix(fpga): pre-bringup RTL hardening + test-suite hardening

2026-04-22 13:23:38 +05:45

radar_system_top_50t.v

Revert "fix(fpga): move IBUF+BUFIO+BUFR into 50T wrapper (same scope as pad)"

2026-04-20 21:47:19 +05:45

radar_system_top_te0712_dev.v

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radar_system_top_te0713_dev.v

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radar_system_top_te0713_umft601x_dev.v

feat(fpga): make FT2232H default USB interface, rewrite FT601 write FSM, add clock-loss watchdog

2026-04-16 16:18:52 +05:45

radar_system_top.v

merge(wave2): manual resolution of 6 shared files — fft-2048 × p0 audit

2026-04-21 02:12:04 +05:45

radar_transmitter.v

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range_bin_decimator.v

feat(fpga): integrate 2048-pt FFT upgrade — non-conflicting RTL (wave 1/3)

2026-04-21 01:52:32 +05:45

run_regression.sh

merge(wave2): manual resolution of 6 shared files — fft-2048 × p0 audit

2026-04-21 02:12:04 +05:45

rx_gain_control.v

feat(fpga): integrate 2048-pt FFT upgrade — non-conflicting RTL (wave 1/3)

2026-04-21 01:52:32 +05:45

short_chirp_i.mem

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short_chirp_q.mem

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usb_data_interface_ft2232h.v

merge(wave2): manual resolution of 6 shared files — fft-2048 × p0 audit

2026-04-21 02:12:04 +05:45

usb_data_interface.v

fix(fpga): correct USB frame-sync counter for 512x32 cell grid

2026-04-22 15:44:48 +05:45

xfft_16.v

…