Jason 25e1f76841 fix(fpga): PR-X.1.b — close F-7.4 on real Vivado xsim ...

Bench-verify the F-7.4 MMCM-lock gating (commit 6738f12) under real
Xilinx UNISIM primitives, not just the iverilog stub.

  ad9484_interface_400m.v
    Add `timescale 1ns / 1ps. Lone RTL file missing it; xelab refused
    to elaborate alongside TB+wrapper that both declared a timescale.

  tb/tb_ad9484_xsim.v
    Test Group 2 ("adc_dco_bufg toggles") moved below the first
    wait_for_adc_ready() — adc_dco_bufg now sources MMCM CLKOUT, which
    is gated until the MMCM SIM model locks (~4096 DCO cycles after
    reset deassert). Sampling pre-lock saw a stuck output, not a real
    BUFG defect.

    Test 17 SDR-ramp "no skips" tolerance 0 → 1 — Test 15 already
    grants a 6-sample startup-transient window for diff_one_count.
    Observed delta-other = 1 of 63 is the same pipeline-startup
    transient (first valid sample arrives before ramp launch
    aligns), not a demux bug.

  scripts/50t/run_ad9484_xsim.sh (new)
    xvlog + glbl.v + xelab -L unisims_ver -L secureip + xsim --runall.
    Mirrors run_xfft_xsim.sh / run_mf_chain_xsim.sh pattern.

Verification:
  remote Vivado 2025.2 xsim → 17 / 17 PASS (** ALL TESTS PASSED **)
  local iverilog regression  → 43 / 0 / 0 (was 37 / 0 / 6)

Closes PR-N #86 on the real simulator path.

2026-05-05 13:33:48 +05:45

..

constraints

fix(fpga): C-4 — replace IDDR DDR demux with negedge IFF for AD9484 SDR

2026-05-01 23:12:55 +05:45

formal

chirp-v2 PR-D: chirp_scheduler replaces radar_mode_controller; MF/MTI wave_sel-native

2026-04-30 20:52:32 +05:45

ip/xfft_2048_ip

fix(fpga): PR-O.8 — cfg_tdata 24->16 for Pipelined Streaming I/O

2026-05-02 10:08:00 +05:45

scripts

fix(fpga): PR-X.1.b — close F-7.4 on real Vivado xsim

2026-05-05 13:33:48 +05:45

tb

fix(fpga): PR-X.1.b — close F-7.4 on real Vivado xsim

2026-05-05 13:33:48 +05:45

.gitignore

…

ad9484_interface_400m.v

fix(fpga): PR-X.1.b — close F-7.4 on real Vivado xsim

2026-05-05 13:33:48 +05:45

adc_clk_mmcm_integration.md

…

adc_clk_mmcm.v

…

cdc_async_fifo.v

AUDIT-C11: replace Gray-CDC at CIC→FIR with home-grown async FIFO

2026-04-30 10:47:31 +05:45

cdc_modules.v

…

cfar_ca.v

docs(cfar): PR-M.4 — note Doppler-window dependency on CFAR alpha

2026-05-01 18:53:24 +05:45

chirp_reference_rom.v

chirp-v2 PR-C: chirp_reference_rom replaces chirp_memory_loader_param

2026-04-30 19:37:43 +05:45

chirp_scheduler.v

chirp-v2 PR-E: plfm_chirp_controller_v2 + scheduler-driven TX via async-FIFO

2026-04-30 21:51:46 +05:45

cic_decimator_4x_enhanced.v

…

dac_interface_single.v

…

ddc_400m.v

fix(fpga): PR-X.1 F-7.6 — correct offset-binary mid-scale conversion in DDC

2026-05-05 12:12:04 +05:45

ddc_input_interface.v

…

doppler_processor.v

fix(fpga): PR-Q.1 — stagger MEDIUM PRI 175→161 µs for 3-PRI Doppler CRT (C-5)

2026-05-02 13:37:06 +05:45

edge_detector.v

…

fft_engine_axi_bridge.v

fix(fpga): PR-O.8 — cfg_tdata 24->16 for Pipelined Streaming I/O

2026-05-02 10:08:00 +05:45

fft_engine.v

fix(fpga): PR-O — xFFT scaled mode + 32-bit MF chain widening

2026-05-02 08:33:06 +05:45

fft_twiddle_16.mem

…

fft_twiddle_1024.mem

…

fft_twiddle_2048.mem

…

fir_lowpass.v

AUDIT-S17: document fir_lowpass +4.96 dB DC gain and CIC-droop comp

2026-04-30 10:08:34 +05:45

fpga_self_test.v

AUDIT-S19/S20/S21: replace fpga_self_test tautologies with real arithmetic

2026-04-29 23:27:15 +05:45

frequency_matched_filter.v

fix(fpga): PR-O — xFFT scaled mode + 32-bit MF chain widening

2026-05-02 08:33:06 +05:45

matched_filter_multi_segment.v

fix(rx): PR-J.2 — pre-collect chirp + slide segments (LONG hang)

2026-05-01 15:07:19 +05:45

matched_filter_processing_chain.v

fix(fpga): PR-O — xFFT scaled mode + 32-bit MF chain widening

2026-05-02 08:33:06 +05:45

mti_canceller.v

chirp-v2 PR-D: chirp_scheduler replaces radar_mode_controller; MF/MTI wave_sel-native

2026-04-30 20:52:32 +05:45

nco_400m_enhanced.v

…

plfm_chirp_controller_v2.v

chirp-v2 PR-E: plfm_chirp_controller_v2 + scheduler-driven TX via async-FIFO

2026-04-30 21:51:46 +05:45

radar_params.vh

fix(fpga): PR-Q.1 — stagger MEDIUM PRI 175→161 µs for 3-PRI Doppler CRT (C-5)

2026-05-02 13:37:06 +05:45

radar_receiver_final.v

fix(fpga): PR-X.1 F-7.7 — wire AD9484 OR sticky to shared clear pulse

2026-05-05 12:15:15 +05:45

radar_system_top_50t.v

chirp-v2 PR-F follow-up 2: TB widenings + 50T include + comment

2026-05-01 04:35:08 +05:45

radar_system_top_te0712_dev.v

…

radar_system_top_te0713_dev.v

…

radar_system_top_te0713_umft601x_dev.v

fpga: split gpio_dig5/dig7 by fault class (AUDIT-S10)

2026-04-29 20:06:52 +05:45

radar_system_top.v

feat(rtl,gui): PR-U / M-8 — sub-frame enable mask routed end-to-end (C-5 hardening)

2026-05-02 17:49:16 +05:45

radar_transmitter.v

chirp-v2 PR-E: plfm_chirp_controller_v2 + scheduler-driven TX via async-FIFO

2026-04-30 21:51:46 +05:45

range_bin_decimator.v

AUDIT-S12: parameterize output_bin_count zero-literals in range_bin_decimator

2026-04-30 09:04:01 +05:45

run_regression.sh

ci(fpga): PR-M.3 — wire T-6 drift cosim into regression + CI deps

2026-05-01 18:53:09 +05:45

rx_gain_control.v

…

rx_long_seg0_i.mem

chirp-v2 PR-B: 3-waveform mem generator + 11 new .mem files

2026-04-30 17:46:08 +05:45

rx_long_seg0_q.mem

chirp-v2 PR-B: 3-waveform mem generator + 11 new .mem files

2026-04-30 17:46:08 +05:45

rx_long_seg1_i.mem

chirp-v2 PR-B: 3-waveform mem generator + 11 new .mem files

2026-04-30 17:46:08 +05:45

rx_long_seg1_q.mem

chirp-v2 PR-B: 3-waveform mem generator + 11 new .mem files

2026-04-30 17:46:08 +05:45

rx_medium_i.mem

chirp-v2 PR-B: 3-waveform mem generator + 11 new .mem files

2026-04-30 17:46:08 +05:45

rx_medium_q.mem

chirp-v2 PR-B: 3-waveform mem generator + 11 new .mem files

2026-04-30 17:46:08 +05:45

rx_short_i.mem

chirp-v2 PR-B: 3-waveform mem generator + 11 new .mem files

2026-04-30 17:46:08 +05:45

rx_short_q.mem

chirp-v2 PR-B: 3-waveform mem generator + 11 new .mem files

2026-04-30 17:46:08 +05:45

tx_long_lut.mem

chirp-v2 PR-B: 3-waveform mem generator + 11 new .mem files

2026-04-30 17:46:08 +05:45

tx_medium_lut.mem

chirp-v2 PR-B: 3-waveform mem generator + 11 new .mem files

2026-04-30 17:46:08 +05:45

tx_short_lut.mem

chirp-v2 PR-B: 3-waveform mem generator + 11 new .mem files

2026-04-30 17:46:08 +05:45

usb_data_interface_ft2232h.v

feat(rtl,gui): PR-U / M-8 — sub-frame enable mask routed end-to-end (C-5 hardening)

2026-05-02 17:49:16 +05:45

usb_data_interface.v

AUDIT-C16: parameterize NUM_CELLS + sample_counter width for 200T

2026-04-29 23:01:41 +05:45

xfft_16.v

…

xfft_2048.v

fix(fpga): PR-O.8.1 — drop stale BFP-era ports, fix xsim include path

2026-05-02 10:20:10 +05:45