mirror of
https://github.com/NawfalMotii79/PLFM_RADAR.git
synced 2026-06-09 23:17:33 +00:00
Jason
0c82de54a2
Bug: bridge advanced in_count and asserted tlast on din_valid alone, ignoring the IP's tready handshake. With LogiCORE FFT v9.1 in nonrealtime throttle mode (per .xci), tready can deassert briefly during BFP normalization or pipeline events, silently dropping input samples and shifting tlast off-by-N. Fix: add 1-deep skid buffer + AXI-correct handshake. Phase 1 drains the active beat when the IP accepts it (and shifts skid up); Phase 2 loads new upstream samples respecting post-handshake slot availability. Track accept_count separately from in_count to drive the S_FEED->S_DRAIN transition on the Nth accepted beat. Sustained 2+ cycle backpressure exhausts the skid and sets overflow_sticky for debug visibility. Audit cross-refs (AUDIT-C10): - "tready ignored" - CONFIRMED, fixed here - "SCALE_SCH unset" - REFUTED (BFP mode uses tuser, not cfg_tdata) - "output ordering not configured" - REFUTED (.xci natural_order) Verification: new tb_fft_engine_axi_bridge.v with stub xfft_2048 exercises 4 backpressure patterns (none / dip-at-3 / dip-at-100 / 3-cycle sustained). Quick regression 30/30 PASS.
734 lines
25 KiB
Bash
Executable File
734 lines
25 KiB
Bash
Executable File
#!/bin/bash
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# ===========================================================================
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# FPGA Regression Test Runner for AERIS-10 Radar
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# Phase 0: Vivado-style lint (catches issues iverilog silently accepts)
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# Phase 1+: Compile and run all verified iverilog testbenches
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#
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# Usage: ./run_regression.sh [--quick] [--skip-lint]
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# --quick Skip long-running integration tests (receiver golden, system TB)
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# --skip-lint Skip Phase 0 lint checks (not recommended)
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#
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# Exit code: 0 if all tests pass, 1 if any fail
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# ===========================================================================
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set -euo pipefail
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SCRIPT_DIR="$(cd "$(dirname "$0")" && pwd)"
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cd "$SCRIPT_DIR"
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QUICK=0
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SKIP_LINT=0
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for arg in "$@"; do
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case "$arg" in
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--quick) QUICK=1 ;;
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--skip-lint) SKIP_LINT=1 ;;
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esac
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done
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PASS=0
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FAIL=0
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SKIP=0
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LINT_WARN=0
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LINT_ERR=0
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ERRORS=""
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# Colors (if terminal supports it)
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RED='\033[0;31m'
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GREEN='\033[0;32m'
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YELLOW='\033[0;33m'
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CYAN='\033[0;36m'
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NC='\033[0m' # No Color
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# ===========================================================================
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# PHASE 0: VIVADO-STYLE LINT
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# Two layers:
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# (A) iverilog -Wall full-design compile — parse for serious warnings
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# (B) Custom regex checks for patterns Vivado treats as errors
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# ===========================================================================
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# Production RTL file list (same as system TB minus testbench files)
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# Uses ADC stub for IBUFDS/BUFIO primitives that iverilog can't parse
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PROD_RTL=(
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radar_system_top.v
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radar_transmitter.v
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dac_interface_single.v
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plfm_chirp_controller.v
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radar_receiver_final.v
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tb/ad9484_interface_400m_stub.v
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ddc_400m.v
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nco_400m_enhanced.v
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cic_decimator_4x_enhanced.v
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cdc_modules.v
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fir_lowpass.v
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ddc_input_interface.v
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chirp_memory_loader_param.v
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matched_filter_multi_segment.v
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matched_filter_processing_chain.v
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range_bin_decimator.v
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doppler_processor.v
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xfft_16.v
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fft_engine.v
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xfft_2048.v
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fft_engine_axi_bridge.v
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frequency_matched_filter.v
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usb_data_interface.v
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usb_data_interface_ft2232h.v
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edge_detector.v
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radar_mode_controller.v
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rx_gain_control.v
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cfar_ca.v
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mti_canceller.v
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fpga_self_test.v
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)
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# Source-only RTL (not instantiated at top level, but should still be lint-clean)
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# Note: ad9484_interface_400m.v is excluded — it uses Xilinx primitives
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# (IBUFDS, BUFIO, BUFG, IDDR) that iverilog cannot compile. The production
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# design uses tb/ad9484_interface_400m_stub.v for simulation instead.
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EXTRA_RTL=(
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)
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# ---------------------------------------------------------------------------
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# Shared RTL file lists for integration / system tests
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# Centralised here so a new module only needs adding once.
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# ---------------------------------------------------------------------------
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# Receiver chain (used by golden generate/compare tests)
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RECEIVER_RTL=(
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radar_receiver_final.v
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radar_mode_controller.v
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tb/ad9484_interface_400m_stub.v
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ddc_400m.v nco_400m_enhanced.v cic_decimator_4x_enhanced.v
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cdc_modules.v fir_lowpass.v ddc_input_interface.v
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chirp_memory_loader_param.v
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matched_filter_multi_segment.v matched_filter_processing_chain.v
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range_bin_decimator.v doppler_processor.v xfft_16.v fft_engine.v
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xfft_2048.v fft_engine_axi_bridge.v
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frequency_matched_filter.v
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rx_gain_control.v mti_canceller.v
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)
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# Full system top (receiver chain + TX + USB + detection + self-test)
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SYSTEM_RTL=(
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radar_system_top.v
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radar_transmitter.v dac_interface_single.v plfm_chirp_controller.v
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"${RECEIVER_RTL[@]}"
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usb_data_interface.v usb_data_interface_ft2232h.v edge_detector.v
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cfar_ca.v fpga_self_test.v
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)
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# ---- Layer A: iverilog -Wall compilation ----
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run_lint_iverilog() {
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local label="$1"
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shift
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local files=("$@")
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local warn_file="/tmp/iverilog_lint_$$_${label}.log"
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printf " %-45s " "iverilog -Wall ($label)"
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if ! iverilog -g2001 -DSIMULATION -Wall -o /dev/null "${files[@]}" 2>"$warn_file"; then
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# Hard compile error — always fatal
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echo -e "${RED}COMPILE ERROR${NC}"
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while IFS= read -r line; do
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echo " $line"
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done < "$warn_file"
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LINT_ERR=$((LINT_ERR + 1))
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rm -f "$warn_file"
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return 1
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fi
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# Parse warnings — classify as error-level or info-level
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local err_count=0
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local info_count=0
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local err_lines=""
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while IFS= read -r line; do
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# Part-select out of range — Vivado Synth 8-524 (ERROR in Vivado)
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if echo "$line" | grep -q 'Part select.*is selecting after the vector\|out of bound bits'; then
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err_count=$((err_count + 1))
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err_lines="$err_lines\n ${RED}[VIVADO-ERR]${NC} $line"
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# Port width mismatch / connection mismatch
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elif echo "$line" | grep -q 'port.*does not match\|Port.*mismatch'; then
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err_count=$((err_count + 1))
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err_lines="$err_lines\n ${RED}[VIVADO-ERR]${NC} $line"
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# Informational warnings (timescale, dangling ports, array sensitivity)
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elif echo "$line" | grep -q 'timescale\|dangling\|sensitive to all'; then
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info_count=$((info_count + 1))
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# Unknown warning — report but don't fail
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elif [[ -n "$line" ]]; then
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info_count=$((info_count + 1))
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fi
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done < "$warn_file"
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if [[ "$err_count" -gt 0 ]]; then
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echo -e "${RED}FAIL${NC} ($err_count Vivado-class errors, $info_count info)"
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echo -e "$err_lines"
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LINT_ERR=$((LINT_ERR + err_count))
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else
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echo -e "${GREEN}PASS${NC} ($info_count info warnings)"
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fi
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rm -f "$warn_file"
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}
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# ---- Layer B: Custom regex static checks ----
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# Catches patterns that Vivado treats as errors/warnings but iverilog ignores
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run_lint_static() {
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printf " %-45s " "Static RTL checks"
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local err_count=0
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local warn_count=0
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local err_lines=""
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local warn_lines=""
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for f in "$@"; do
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[[ -f "$f" ]] || continue
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# Skip testbench files (tb/ directory) — only lint production RTL
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case "$f" in tb/*) continue ;; esac
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local linenum=0
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while IFS= read -r line; do
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linenum=$((linenum + 1))
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# --- CHECK 1: Part-select with literal range on reg ---
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# Pattern: identifier[N:M] where N exceeds declared width
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# (iverilog catches this, but belt-and-suspenders)
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# --- CHECK 2: case/casex/casez without default (non-full case) ---
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# Vivado SYNTH-6 / inferred latch warning
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# Heuristic: look for case/casex/casez, then check if 'default' appears
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# before the matching 'endcase'. This is approximate — full parsing
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# would need a real parser. We flag 'case' lines so the developer
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# can manually verify.
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# (Handled below as a multi-line check)
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# --- CHECK 3: Blocking assignment (=) inside always @(posedge ...) ---
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# Vivado SYNTH-5 warning for inferred latches / race conditions
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# Only flag if the always block is clocked (posedge/negedge)
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# This is a heuristic — we check for '= ' that isn't '<=', '==', '!='
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# inside an always block header containing 'posedge' or 'negedge'.
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# (Too complex for line-by-line — skip for now, handled by testbenches)
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# --- CHECK 4: Multi-driven register (assign + always on same signal) ---
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# (Would need cross-file analysis — skip for v1)
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done < "$f"
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done
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# --- Multi-line check: case without default ---
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for f in "$@"; do
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[[ -f "$f" ]] || continue
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case "$f" in tb/*) continue ;; esac
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# Find case blocks and check for default
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# Use awk to find case..endcase blocks missing 'default'
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local missing_defaults
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missing_defaults=$(awk '
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/^[[:space:]]*(case|casex|casez)[[:space:]]*\(/ {
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case_line = NR
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case_file = FILENAME
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has_default = 0
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in_case = 1
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next
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}
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in_case && /default[[:space:]]*:/ {
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has_default = 1
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}
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in_case && /endcase/ {
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if (!has_default) {
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printf "%s:%d: case statement without default\n", FILENAME, case_line
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}
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in_case = 0
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}
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' "$f" 2>/dev/null)
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if [[ -n "$missing_defaults" ]]; then
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while IFS= read -r hit; do
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warn_count=$((warn_count + 1))
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warn_lines="$warn_lines\n ${YELLOW}[SYNTH-6]${NC} $hit"
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done <<< "$missing_defaults"
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fi
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done
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# CHECK 5 ($readmemh in synth code) and CHECK 6 (unused includes)
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# require multi-line ifdef tracking / cross-file analysis. Not feasible
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# with line-by-line regex. Omitted — use Vivado lint instead.
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if [[ "$err_count" -gt 0 ]]; then
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echo -e "${RED}FAIL${NC} ($err_count errors, $warn_count warnings)"
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echo -e "$err_lines"
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LINT_ERR=$((LINT_ERR + err_count))
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elif [[ "$warn_count" -gt 0 ]]; then
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echo -e "${YELLOW}WARN${NC} ($warn_count warnings)"
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echo -e "$warn_lines"
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LINT_WARN=$((LINT_WARN + warn_count))
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else
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echo -e "${GREEN}PASS${NC}"
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fi
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}
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# ---------------------------------------------------------------------------
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# Helper: compile, run, and compare a matched-filter co-sim scenario
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# run_mf_cosim <scenario_name> <define_flag>
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# ---------------------------------------------------------------------------
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run_mf_cosim() {
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local name="$1"
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local define="$2"
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local vvp="tb/tb_mf_cosim_${name}.vvp"
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local scenario_lower="$name"
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printf " %-45s " "MF Co-Sim ($name)"
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# Compile — build command as string to handle optional define
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local cmd="iverilog -g2001 -DSIMULATION"
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if [[ -n "$define" ]]; then
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cmd="$cmd $define"
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fi
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cmd="$cmd -o $vvp tb/tb_mf_cosim.v matched_filter_processing_chain.v fft_engine.v xfft_2048.v fft_engine_axi_bridge.v frequency_matched_filter.v chirp_memory_loader_param.v"
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if ! eval "$cmd" 2>/tmp/iverilog_err_$$; then
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echo -e "${RED}COMPILE FAIL${NC}"
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ERRORS="$ERRORS\n MF Co-Sim ($name): compile error ($(head -1 /tmp/iverilog_err_$$))"
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FAIL=$((FAIL + 1))
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return
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fi
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# Run TB
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local output
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output=$(timeout 120 vvp "$vvp" 2>&1) || true
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rm -f "$vvp"
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# Check TB internal pass/fail
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local tb_fail
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tb_fail=$(echo "$output" | grep -Ec '^\[FAIL' || true)
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if [[ "$tb_fail" -gt 0 ]]; then
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echo -e "${RED}FAIL${NC} (TB internal failure)"
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ERRORS="$ERRORS\n MF Co-Sim ($name): TB internal failure"
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FAIL=$((FAIL + 1))
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return
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fi
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# Run Python compare
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if command -v python3 >/dev/null 2>&1; then
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local compare_out
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local compare_rc=0
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compare_out=$(python3 tb/cosim/compare_mf.py "$scenario_lower" 2>&1) || compare_rc=$?
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if [[ "$compare_rc" -ne 0 ]]; then
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echo -e "${RED}FAIL${NC} (compare_mf.py mismatch)"
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ERRORS="$ERRORS\n MF Co-Sim ($name): Python compare failed"
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FAIL=$((FAIL + 1))
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return
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fi
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else
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echo -e "${YELLOW}SKIP${NC} (RTL passed, python3 not found — compare skipped)"
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SKIP=$((SKIP + 1))
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return
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fi
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echo -e "${GREEN}PASS${NC} (RTL + Python compare)"
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PASS=$((PASS + 1))
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}
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# ---------------------------------------------------------------------------
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# Helper: compile, run, and compare a Doppler co-sim scenario
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# run_doppler_cosim <scenario_name> <define_flag>
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# ---------------------------------------------------------------------------
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run_doppler_cosim() {
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local name="$1"
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local define="$2"
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local vvp="tb/tb_doppler_cosim_${name}.vvp"
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printf " %-45s " "Doppler Co-Sim ($name)"
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# Compile — build command as string to handle optional define
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local cmd="iverilog -g2001 -DSIMULATION"
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if [[ -n "$define" ]]; then
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cmd="$cmd $define"
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fi
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cmd="$cmd -o $vvp tb/tb_doppler_cosim.v doppler_processor.v xfft_16.v fft_engine.v"
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if ! eval "$cmd" 2>/tmp/iverilog_err_$$; then
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echo -e "${RED}COMPILE FAIL${NC}"
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ERRORS="$ERRORS\n Doppler Co-Sim ($name): compile error ($(head -1 /tmp/iverilog_err_$$))"
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FAIL=$((FAIL + 1))
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return
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fi
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# Run TB
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local output
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output=$(timeout 120 vvp "$vvp" 2>&1) || true
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rm -f "$vvp"
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# Check TB internal pass/fail
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local tb_fail
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tb_fail=$(echo "$output" | grep -Ec '^\[FAIL' || true)
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if [[ "$tb_fail" -gt 0 ]]; then
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echo -e "${RED}FAIL${NC} (TB internal failure)"
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ERRORS="$ERRORS\n Doppler Co-Sim ($name): TB internal failure"
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FAIL=$((FAIL + 1))
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return
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fi
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# Run Python compare
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if command -v python3 >/dev/null 2>&1; then
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local compare_out
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local compare_rc=0
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compare_out=$(python3 tb/cosim/compare_doppler.py "$name" 2>&1) || compare_rc=$?
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if [[ "$compare_rc" -ne 0 ]]; then
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echo -e "${RED}FAIL${NC} (compare_doppler.py mismatch)"
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ERRORS="$ERRORS\n Doppler Co-Sim ($name): Python compare failed"
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FAIL=$((FAIL + 1))
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return
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fi
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else
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echo -e "${YELLOW}SKIP${NC} (RTL passed, python3 not found — compare skipped)"
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SKIP=$((SKIP + 1))
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return
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fi
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echo -e "${GREEN}PASS${NC} (RTL + Python compare)"
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PASS=$((PASS + 1))
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}
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|
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# ---------------------------------------------------------------------------
|
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# Helper: compile and run a single testbench
|
|
# run_test <name> <vvp_path> <iverilog_args...>
|
|
# ---------------------------------------------------------------------------
|
|
run_test() {
|
|
# Optional: --timeout=N as first arg overrides default 120s
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|
local timeout_secs=120
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|
if [[ "$1" == --timeout=* ]]; then
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timeout_secs="${1#--timeout=}"
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shift
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fi
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|
|
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local name="$1"
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local vvp="$2"
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shift 2
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local args=("$@")
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|
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printf " %-45s " "$name"
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|
|
# Compile
|
|
if ! iverilog -g2001 -DSIMULATION -o "$vvp" "${args[@]}" 2>/tmp/iverilog_err_$$; then
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echo -e "${RED}COMPILE FAIL${NC}"
|
|
ERRORS="$ERRORS\n $name: compile error ($(head -1 /tmp/iverilog_err_$$))"
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|
FAIL=$((FAIL + 1))
|
|
return
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fi
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|
|
# Run
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|
local output
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|
output=$(timeout "$timeout_secs" vvp "$vvp" 2>&1) || true
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|
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# Count PASS/FAIL in output (testbenches use explicit [PASS]/[FAIL] markers)
|
|
# Match `[PASS]` and `[PASS <digits>]` (and same for FAIL). Excludes
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# informational tags like `[FAIL-INFO]` (used for known unrelated bugs,
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# e.g. RX-NEW-1 fft_engine bin-shift in tb_matched_filter_processing_chain.v)
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# which would otherwise false-fire as real failures.
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local test_pass test_fail
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|
test_pass=$(echo "$output" | grep -Ec '^\[PASS( [0-9]+)?\]' || true)
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|
test_fail=$(echo "$output" | grep -Ec '^\[FAIL( [0-9]+)?\]' || true)
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|
|
|
if [[ "$test_fail" -gt 0 ]]; then
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|
echo -e "${RED}FAIL${NC} (pass=$test_pass, fail=$test_fail)"
|
|
ERRORS="$ERRORS\n $name: $test_fail failure(s)"
|
|
FAIL=$((FAIL + 1))
|
|
elif [[ "$test_pass" -gt 0 ]]; then
|
|
echo -e "${GREEN}PASS${NC} ($test_pass checks)"
|
|
PASS=$((PASS + 1))
|
|
else
|
|
# No PASS/FAIL markers — check for clean completion
|
|
if echo "$output" | grep -qi 'finish\|complete\|done'; then
|
|
echo -e "${GREEN}PASS${NC} (completed)"
|
|
PASS=$((PASS + 1))
|
|
else
|
|
echo -e "${YELLOW}UNKNOWN${NC} (no PASS/FAIL markers)"
|
|
ERRORS="$ERRORS\n $name: no pass/fail markers in output"
|
|
FAIL=$((FAIL + 1))
|
|
fi
|
|
fi
|
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|
|
rm -f "$vvp"
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|
}
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|
|
# ===========================================================================
|
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echo "============================================"
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echo " AERIS-10 FPGA Regression Test Suite"
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echo "============================================"
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echo ""
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echo "Date: $(date)"
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echo "iverilog: $(iverilog -V 2>&1 | head -1)"
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echo ""
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# ===========================================================================
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# PHASE 0: LINT (Vivado-class error detection)
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# ===========================================================================
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if [[ "$SKIP_LINT" -eq 0 ]]; then
|
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echo "--- PHASE 0: LINT (Vivado-class checks) ---"
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|
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# Layer A: iverilog -Wall on full production design
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run_lint_iverilog "production" "${PROD_RTL[@]}"
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|
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# Layer A: standalone modules not in top-level hierarchy
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# (use ${EXTRA_RTL[@]+...} guard so empty array doesn't trip set -u)
|
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if [[ ${#EXTRA_RTL[@]} -gt 0 ]]; then
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for extra in "${EXTRA_RTL[@]}"; do
|
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if [[ -f "$extra" ]]; then
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run_lint_iverilog "$(basename "$extra" .v)" "$extra"
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fi
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done
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fi
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# Layer B: custom static regex checks
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if [[ ${#EXTRA_RTL[@]} -gt 0 ]]; then
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ALL_RTL=("${PROD_RTL[@]}" "${EXTRA_RTL[@]}")
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else
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ALL_RTL=("${PROD_RTL[@]}")
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fi
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run_lint_static "${ALL_RTL[@]}"
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|
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echo ""
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if [[ "$LINT_ERR" -gt 0 ]]; then
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echo -e "${RED} LINT FAILED: $LINT_ERR Vivado-class error(s) detected.${NC}"
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echo " Fix lint errors before pushing to Vivado. Aborting regression."
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echo ""
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exit 1
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elif [[ "$LINT_WARN" -gt 0 ]]; then
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echo -e "${YELLOW} LINT: $LINT_WARN advisory warning(s) (non-blocking)${NC}"
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else
|
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echo -e "${GREEN} LINT: All checks passed${NC}"
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|
fi
|
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echo ""
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|
else
|
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echo "--- PHASE 0: LINT (skipped via --skip-lint) ---"
|
|
echo ""
|
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fi
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# ===========================================================================
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# PHASE 1: UNIT TESTS — Changed Modules (HIGH PRIORITY)
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# ===========================================================================
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echo "--- PHASE 1: Changed Modules ---"
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run_test "CIC Decimator" \
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tb/tb_cic_reg.vvp \
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tb/tb_cic_decimator.v cic_decimator_4x_enhanced.v
|
|
|
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run_test "Chirp Controller (BRAM)" \
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tb/tb_chirp_reg.vvp \
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tb/tb_chirp_controller.v plfm_chirp_controller.v
|
|
|
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run_test "Chirp Contract" \
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tb/tb_chirp_ctr_reg.vvp \
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tb/tb_chirp_contract.v plfm_chirp_controller.v
|
|
|
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run_doppler_cosim "stationary" ""
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run_doppler_cosim "moving" "-DSCENARIO_MOVING"
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run_doppler_cosim "two_targets" "-DSCENARIO_TWO"
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|
|
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run_test "Threshold Detector (detection bugs)" \
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tb/tb_threshold_detector.vvp \
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tb/tb_threshold_detector.v
|
|
|
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run_test "RX Gain Control (digital gain)" \
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|
tb/tb_rx_gain_control.vvp \
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|
tb/tb_rx_gain_control.v rx_gain_control.v
|
|
|
|
run_test "MTI Canceller (ground clutter)" \
|
|
tb/tb_mti_canceller.vvp \
|
|
tb/tb_mti_canceller.v mti_canceller.v
|
|
|
|
run_test "CFAR CA Detector" \
|
|
tb/tb_cfar_ca.vvp \
|
|
tb/tb_cfar_ca.v cfar_ca.v
|
|
|
|
run_test "FPGA Self-Test" \
|
|
tb/tb_fpga_self_test.vvp \
|
|
tb/tb_fpga_self_test.v fpga_self_test.v
|
|
|
|
run_test "FFT AXI Bridge tready handshake (AUDIT-C10)" \
|
|
tb/tb_fft_engine_axi_bridge.vvp \
|
|
tb/tb_fft_engine_axi_bridge.v fft_engine_axi_bridge.v
|
|
|
|
echo ""
|
|
|
|
# ===========================================================================
|
|
# PHASE 2: INTEGRATION TESTS
|
|
# ===========================================================================
|
|
echo "--- PHASE 2: Integration Tests ---"
|
|
|
|
run_test "DDC Chain (NCO→CIC→FIR)" \
|
|
tb/tb_ddc_reg.vvp \
|
|
tb/tb_ddc_cosim.v ddc_400m.v nco_400m_enhanced.v \
|
|
cic_decimator_4x_enhanced.v fir_lowpass.v cdc_modules.v
|
|
|
|
# Real-data co-simulation: committed golden hex vs RTL (exact match required).
|
|
# These catch architecture mismatches (e.g. 32-pt → dual 16-pt Doppler FFT)
|
|
# that self-blessing golden-generate/compare tests cannot detect.
|
|
run_test "Doppler Real-Data (ADI CN0566, exact match)" \
|
|
tb/tb_doppler_realdata.vvp \
|
|
tb/tb_doppler_realdata.v doppler_processor.v xfft_16.v fft_engine.v
|
|
|
|
run_test "Full-Chain Real-Data (decim→Doppler, exact match)" \
|
|
tb/tb_fullchain_realdata.vvp \
|
|
tb/tb_fullchain_realdata.v range_bin_decimator.v \
|
|
doppler_processor.v xfft_16.v fft_engine.v
|
|
|
|
if [[ "$QUICK" -eq 0 ]]; then
|
|
# Receiver integration (structural + bounds + pulse assertions).
|
|
# Replaces the earlier "Receiver golden generate/compare" pair, which was
|
|
# self-blessing (both passes ran identical RTL on identical stimulus, so
|
|
# it passed regardless of bugs). Real co-sim coverage is now provided by
|
|
# tb_doppler_realdata.v and tb_fullchain_realdata.v (Python goldens,
|
|
# exact match); this integration test exercises the full RX pipeline
|
|
# (ADC stub → DDC → MF → Decim → Doppler) and verifies that
|
|
# doppler_frame_done is a single-cycle pulse at module boundaries.
|
|
run_test --timeout=600 "Receiver Integration (tb_radar_receiver_final)" \
|
|
tb/tb_rx_final_reg.vvp \
|
|
tb/tb_radar_receiver_final.v "${RECEIVER_RTL[@]}"
|
|
|
|
# Full system top (monitoring-only, legacy)
|
|
run_test "System Top (radar_system_tb)" \
|
|
tb/tb_system_reg.vvp \
|
|
tb/radar_system_tb.v "${SYSTEM_RTL[@]}"
|
|
|
|
# E2E integration (46 strict checks: TX, RX, USB R/W, CDC, safety, reset)
|
|
run_test "System E2E (tb_system_e2e)" \
|
|
tb/tb_system_e2e_reg.vvp \
|
|
tb/tb_system_e2e.v "${SYSTEM_RTL[@]}"
|
|
|
|
# USB_MODE=1 (FT2232H production) variants of system tests
|
|
run_test "System Top USB_MODE=1 (FT2232H)" \
|
|
tb/tb_system_ft2232h_reg.vvp \
|
|
-DUSB_MODE_1 \
|
|
tb/radar_system_tb.v "${SYSTEM_RTL[@]}"
|
|
|
|
run_test "System E2E USB_MODE=1 (FT2232H)" \
|
|
tb/tb_system_e2e_ft2232h_reg.vvp \
|
|
-DUSB_MODE_1 \
|
|
tb/tb_system_e2e.v "${SYSTEM_RTL[@]}"
|
|
else
|
|
echo " (skipped receiver integration + system top + E2E + USB_MODE=1 variants — use without --quick)"
|
|
SKIP=$((SKIP + 5))
|
|
fi
|
|
|
|
echo ""
|
|
|
|
# ===========================================================================
|
|
# PHASE 2b: MATCHED FILTER CO-SIMULATION (RTL vs Python golden reference)
|
|
# Runs tb_mf_cosim.v for 4 scenarios, then compare_mf.py validates output
|
|
# against committed Python golden CSV files. In SIMULATION mode, thresholds
|
|
# are generous (behavioral vs fixed-point twiddles differ) — validates
|
|
# state machine mechanics, output count, and energy sanity.
|
|
# ===========================================================================
|
|
echo "--- PHASE 2b: Matched Filter Co-Sim ---"
|
|
|
|
run_mf_cosim "chirp" ""
|
|
run_mf_cosim "dc" "-DSCENARIO_DC"
|
|
run_mf_cosim "impulse" "-DSCENARIO_IMPULSE"
|
|
run_mf_cosim "tone5" "-DSCENARIO_TONE5"
|
|
|
|
echo ""
|
|
|
|
# ===========================================================================
|
|
# PHASE 3: UNIT TESTS — Signal Processing
|
|
# ===========================================================================
|
|
echo "--- PHASE 3: Signal Processing ---"
|
|
|
|
run_test "FFT Engine" \
|
|
tb/tb_fft_reg.vvp \
|
|
tb/tb_fft_engine.v fft_engine.v
|
|
|
|
run_test "NCO 400MHz" \
|
|
tb/tb_nco_reg.vvp \
|
|
tb/tb_nco_400m.v nco_400m_enhanced.v
|
|
|
|
run_test "FIR Lowpass" \
|
|
tb/tb_fir_reg.vvp \
|
|
tb/tb_fir_lowpass.v fir_lowpass.v
|
|
|
|
run_test --timeout=600 "Matched Filter Chain" \
|
|
tb/tb_mf_reg.vvp \
|
|
tb/tb_matched_filter_processing_chain.v matched_filter_processing_chain.v \
|
|
fft_engine.v xfft_2048.v fft_engine_axi_bridge.v \
|
|
chirp_memory_loader_param.v frequency_matched_filter.v
|
|
|
|
# RX-B regression coverage: chain pipeline depth + full-chain
|
|
# autocorrelation peak position. Both run the production fft_engine
|
|
# (no SIMULATION-only behavioural FFT exists). Long-running because
|
|
# the production FFT is BRAM-pipelined (~153k cycles per chain pass).
|
|
run_test --timeout=120 "RX-B Chain Pipeline Latency (tb_rxb_latency_measure)" \
|
|
tb/tb_rxb_lat_reg.vvp \
|
|
tb/tb_rxb_latency_measure.v matched_filter_processing_chain.v \
|
|
fft_engine.v xfft_2048.v fft_engine_axi_bridge.v frequency_matched_filter.v
|
|
|
|
run_test --timeout=600 "RX-B Full-Chain Autocorrelation (tb_rxb_fullchain_latency)" \
|
|
tb/tb_rxb_fc_reg.vvp \
|
|
tb/tb_rxb_fullchain_latency.v matched_filter_multi_segment.v \
|
|
matched_filter_processing_chain.v fft_engine.v xfft_2048.v \
|
|
fft_engine_axi_bridge.v frequency_matched_filter.v \
|
|
chirp_memory_loader_param.v
|
|
|
|
echo ""
|
|
|
|
# ===========================================================================
|
|
# PHASE 4: UNIT TESTS — Infrastructure
|
|
# ===========================================================================
|
|
echo "--- PHASE 4: Infrastructure ---"
|
|
|
|
run_test "CDC Modules (3 variants)" \
|
|
tb/tb_cdc_reg.vvp \
|
|
tb/tb_cdc_modules.v cdc_modules.v
|
|
|
|
run_test "Edge Detector" \
|
|
tb/tb_edge_reg.vvp \
|
|
tb/tb_edge_detector.v edge_detector.v
|
|
|
|
run_test "USB Data Interface" \
|
|
tb/tb_usb_reg.vvp \
|
|
tb/tb_usb_data_interface.v usb_data_interface.v
|
|
|
|
run_test "Range Bin Decimator" \
|
|
tb/tb_rbd_reg.vvp \
|
|
tb/tb_range_bin_decimator.v range_bin_decimator.v
|
|
|
|
run_test "Radar Mode Controller" \
|
|
tb/tb_rmc_reg.vvp \
|
|
tb/tb_radar_mode_controller.v radar_mode_controller.v
|
|
|
|
echo ""
|
|
|
|
# ===========================================================================
|
|
# SUMMARY
|
|
# ===========================================================================
|
|
TOTAL=$((PASS + FAIL + SKIP))
|
|
echo "============================================"
|
|
echo " RESULTS"
|
|
echo "============================================"
|
|
if [[ "$SKIP_LINT" -eq 0 ]]; then
|
|
if [[ "$LINT_ERR" -gt 0 ]]; then
|
|
echo -e " Lint: ${RED}$LINT_ERR error(s)${NC}, $LINT_WARN warning(s)"
|
|
elif [[ "$LINT_WARN" -gt 0 ]]; then
|
|
echo -e " Lint: ${GREEN}0 errors${NC}, ${YELLOW}$LINT_WARN warning(s)${NC}"
|
|
else
|
|
echo -e " Lint: ${GREEN}clean${NC}"
|
|
fi
|
|
fi
|
|
echo " Tests: $PASS passed, $FAIL failed, $SKIP skipped / $TOTAL total"
|
|
echo "============================================"
|
|
|
|
if [[ -n "$ERRORS" ]]; then
|
|
echo ""
|
|
echo "Failures:"
|
|
echo -e "$ERRORS"
|
|
fi
|
|
|
|
echo ""
|
|
|
|
# Exit with error if any failures
|
|
if [[ "$FAIL" -gt 0 ]]; then
|
|
exit 1
|
|
fi
|
|
|
|
exit 0
|