Jason 049f7b5d14 fix(fpga): PR-Q.1 — stagger MEDIUM PRI 175→161 µs for 3-PRI Doppler CRT (C-5) ...

Bumps RP_DEF_MEDIUM_LISTEN_CYCLES 17000 → 15600 so MEDIUM PRI = 161 µs,
distinct from SHORT (175 µs) and LONG (167 µs). Three coprime PRIs let
the host run 3-PRI Chinese-Remainder unfolding on Doppler aliases beyond
the per-sub-frame ±~41 m/s unambiguous range — closes the FPGA half of
audit C-5 (PR-F Doppler ambiguity unfolding).

Stagger choice (proposal B):
  SHORT  175 µs — chirp 1   + listen 174
  MEDIUM 161 µs — chirp 5   + listen 156   (PR-Q, was 175)
  LONG   167 µs — chirp 30  + listen 137

In 3 km mode LONG is blind (4500 m blind zone) → SHORT-vs-MEDIUM
(Δ=14 µs / 8 %) is the operative pair; in 20 km mode MEDIUM-vs-LONG
(Δ=6 µs / 4 %) carries the long-range slice that has SNR for both.
Listens picked to differ by ≥5 % so the alias resolver is robust against
the 5.1 m/s/bin Doppler quantization.

Architecture is unchanged — chirp_scheduler.v already takes per-waveform
host_*_listen_cycles. doppler_processor.v / cfar_ca.v are PRI-agnostic
and just tag Doppler outputs with sub_frame ID; host-side CRT lives in
v7/processing.py (PR-Q.5, follow-on).

Files:
  radar_params.vh:240        RP_DEF_MEDIUM_LISTEN_CYCLES 17000 → 15600
  radar_params.vh:217-228    block comment: stagger rationale + Δ math
  radar_system_top.v:273     port-list comment: default 17000 → 15600
  radar_system_top.v:278-282 staggered-PRI block comment: 3-ladder PRI
  doppler_processor.v:25-30  reference v7/processing.py CRT unfolder
  tb/tb_radar_receiver_final.v:199-202  list MEDIUM=15600 in real-values

Validation: full iverilog regression 42 PASS / 0 FAIL / 1 SKIP (pre-
existing scipy availability) — same baseline as post-PR-O.8. No TB
default-value asserts touched (tb_system_opcodes / tb_usb_protocol_v2
both use literal 16500 for opcode 0x18 round-trip).

Follow-on: PR-Q.2 (cosim T_PRI_MEDIUM align + golden regen), PR-Q.4-7
(v7 GUI 3-PRI CRT unfolder + AMBIGUOUS confidence display), PR-Q.8
(memory close-out). MCU executeChirpSequence is live but PRI-agnostic
in production mode 2'b01 (FPGA auto-scan) — pre-existing 2-ladder
staleness vs chirp-v2 3-ladder, defer to PR-H or dedicated MCU PR.

2026-05-02 13:37:06 +05:45

..

constraints

fix(fpga): C-4 — replace IDDR DDR demux with negedge IFF for AD9484 SDR

2026-05-01 23:12:55 +05:45

formal

chirp-v2 PR-D: chirp_scheduler replaces radar_mode_controller; MF/MTI wave_sel-native

2026-04-30 20:52:32 +05:45

ip/xfft_2048_ip

fix(fpga): PR-O.8 — cfg_tdata 24->16 for Pipelined Streaming I/O

2026-05-02 10:08:00 +05:45

scripts

test(fpga): xsim runner for tb_matched_filter_processing_chain

2026-05-02 11:16:17 +05:45

tb

fix(fpga): PR-Q.1 — stagger MEDIUM PRI 175→161 µs for 3-PRI Doppler CRT (C-5)

2026-05-02 13:37:06 +05:45

.gitignore

feat(fpga): swap matched-filter chain to Xilinx LogiCORE FFT v9.1 IP

2026-04-23 12:39:33 +05:45

ad9484_interface_400m.v

fix(fpga): C-4 — replace IDDR DDR demux with negedge IFF for AD9484 SDR

2026-05-01 23:12:55 +05:45

adc_clk_mmcm_integration.md

Gap 7 MMCM jitter cleaner + CIC comb CREG pipeline + XDC clock-name fix

2026-03-19 22:59:46 +02:00

adc_clk_mmcm.v

fix: FPGA timing margins (WNS +0.002→+0.080ns) + 11 bug fixes from code review

2026-04-14 00:08:26 +05:45

cdc_async_fifo.v

AUDIT-C11: replace Gray-CDC at CIC→FIR with home-grown async FIFO

2026-04-30 10:47:31 +05:45

cdc_modules.v

fix(pre-bringup): second-batch P1/P2/P3 audit findings

2026-04-20 14:28:22 +05:45

cfar_ca.v

docs(cfar): PR-M.4 — note Doppler-window dependency on CFAR alpha

2026-05-01 18:53:24 +05:45

chirp_reference_rom.v

chirp-v2 PR-C: chirp_reference_rom replaces chirp_memory_loader_param

2026-04-30 19:37:43 +05:45

chirp_scheduler.v

chirp-v2 PR-E: plfm_chirp_controller_v2 + scheduler-driven TX via async-FIFO

2026-04-30 21:51:46 +05:45

cic_decimator_4x_enhanced.v

perf(fpga): move CIC comb stages to fabric — 80→70 DSPs (-10)

2026-04-23 11:32:03 +05:45

dac_interface_single.v

…

ddc_400m.v

AUDIT-C11: replace Gray-CDC at CIC→FIR with home-grown async FIFO

2026-04-30 10:47:31 +05:45

ddc_input_interface.v

…

doppler_processor.v

fix(fpga): PR-Q.1 — stagger MEDIUM PRI 175→161 µs for 3-PRI Doppler CRT (C-5)

2026-05-02 13:37:06 +05:45

edge_detector.v

…

fft_engine_axi_bridge.v

fix(fpga): PR-O.8 — cfg_tdata 24->16 for Pipelined Streaming I/O

2026-05-02 10:08:00 +05:45

fft_engine.v

fix(fpga): PR-O — xFFT scaled mode + 32-bit MF chain widening

2026-05-02 08:33:06 +05:45

fft_twiddle_16.mem

Fix staggered-PRF Doppler processing with dual 16-point FFTs

2026-03-27 23:05:28 +02:00

fft_twiddle_1024.mem

…

fft_twiddle_2048.mem

feat(fpga): integrate 2048-pt FFT upgrade — non-conflicting RTL (wave 1/3)

2026-04-21 01:52:32 +05:45

fir_lowpass.v

AUDIT-S17: document fir_lowpass +4.96 dB DC gain and CIC-droop comp

2026-04-30 10:08:34 +05:45

fpga_self_test.v

AUDIT-S19/S20/S21: replace fpga_self_test tautologies with real arithmetic

2026-04-29 23:27:15 +05:45

frequency_matched_filter.v

fix(fpga): PR-O — xFFT scaled mode + 32-bit MF chain widening

2026-05-02 08:33:06 +05:45

matched_filter_multi_segment.v

fix(rx): PR-J.2 — pre-collect chirp + slide segments (LONG hang)

2026-05-01 15:07:19 +05:45

matched_filter_processing_chain.v

fix(fpga): PR-O — xFFT scaled mode + 32-bit MF chain widening

2026-05-02 08:33:06 +05:45

mti_canceller.v

chirp-v2 PR-D: chirp_scheduler replaces radar_mode_controller; MF/MTI wave_sel-native

2026-04-30 20:52:32 +05:45

nco_400m_enhanced.v

fix(fpga): registered reset fan-out at 400 MHz; default USB to FT2232H

2026-04-18 20:34:52 +05:45

plfm_chirp_controller_v2.v

chirp-v2 PR-E: plfm_chirp_controller_v2 + scheduler-driven TX via async-FIFO

2026-04-30 21:51:46 +05:45

radar_params.vh

fix(fpga): PR-Q.1 — stagger MEDIUM PRI 175→161 µs for 3-PRI Doppler CRT (C-5)

2026-05-02 13:37:06 +05:45

radar_receiver_final.v

chirp-v2 PR-G: header/body consistency + runtime MEDIUM ladder

2026-05-01 11:10:06 +05:45

radar_system_top_50t.v

chirp-v2 PR-F follow-up 2: TB widenings + 50T include + comment

2026-05-01 04:35:08 +05:45

radar_system_top_te0712_dev.v

…

radar_system_top_te0713_dev.v

…

radar_system_top_te0713_umft601x_dev.v

fpga: split gpio_dig5/dig7 by fault class (AUDIT-S10)

2026-04-29 20:06:52 +05:45

radar_system_top.v

fix(fpga): PR-Q.1 — stagger MEDIUM PRI 175→161 µs for 3-PRI Doppler CRT (C-5)

2026-05-02 13:37:06 +05:45

radar_transmitter.v

chirp-v2 PR-E: plfm_chirp_controller_v2 + scheduler-driven TX via async-FIFO

2026-04-30 21:51:46 +05:45

range_bin_decimator.v

AUDIT-S12: parameterize output_bin_count zero-literals in range_bin_decimator

2026-04-30 09:04:01 +05:45

run_regression.sh

ci(fpga): PR-M.3 — wire T-6 drift cosim into regression + CI deps

2026-05-01 18:53:09 +05:45

rx_gain_control.v

feat(fpga): integrate 2048-pt FFT upgrade — non-conflicting RTL (wave 1/3)

2026-04-21 01:52:32 +05:45

rx_long_seg0_i.mem

chirp-v2 PR-B: 3-waveform mem generator + 11 new .mem files

2026-04-30 17:46:08 +05:45

rx_long_seg0_q.mem

chirp-v2 PR-B: 3-waveform mem generator + 11 new .mem files

2026-04-30 17:46:08 +05:45

rx_long_seg1_i.mem

chirp-v2 PR-B: 3-waveform mem generator + 11 new .mem files

2026-04-30 17:46:08 +05:45

rx_long_seg1_q.mem

chirp-v2 PR-B: 3-waveform mem generator + 11 new .mem files

2026-04-30 17:46:08 +05:45

rx_medium_i.mem

chirp-v2 PR-B: 3-waveform mem generator + 11 new .mem files

2026-04-30 17:46:08 +05:45

rx_medium_q.mem

chirp-v2 PR-B: 3-waveform mem generator + 11 new .mem files

2026-04-30 17:46:08 +05:45

rx_short_i.mem

chirp-v2 PR-B: 3-waveform mem generator + 11 new .mem files

2026-04-30 17:46:08 +05:45

rx_short_q.mem

chirp-v2 PR-B: 3-waveform mem generator + 11 new .mem files

2026-04-30 17:46:08 +05:45

tx_long_lut.mem

chirp-v2 PR-B: 3-waveform mem generator + 11 new .mem files

2026-04-30 17:46:08 +05:45

tx_medium_lut.mem

chirp-v2 PR-B: 3-waveform mem generator + 11 new .mem files

2026-04-30 17:46:08 +05:45

tx_short_lut.mem

chirp-v2 PR-B: 3-waveform mem generator + 11 new .mem files

2026-04-30 17:46:08 +05:45

usb_data_interface_ft2232h.v

chirp-v2 PR-G: header/body consistency + runtime MEDIUM ladder

2026-05-01 11:10:06 +05:45

usb_data_interface.v

AUDIT-C16: parameterize NUM_CELLS + sample_counter width for 200T

2026-04-29 23:01:41 +05:45

xfft_16.v

fix(test,docs): remove dead xfft_32 files, update test infra for dual-16 FFT, add regression guide

2026-04-07 02:51:48 +03:00

xfft_2048.v

fix(fpga): PR-O.8.1 — drop stale BFP-era ports, fix xsim include path

2026-05-02 10:20:10 +05:45