mirror of
https://github.com/NawfalMotii79/PLFM_RADAR.git
synced 2026-06-08 14:44:56 +00:00
Jason
0728d931c4
Closeout pass for the G-series 3-ladder chirp + adaptive-escalation work.
Cleanup, watchdog/fallback, lint, full regression — final sign-off.
Cleanup + watchdog/fallback: already wired during earlier audit waves
(track watchdog in chirp_scheduler RP_DEF_TRACK_WATCHDOG_FRAMES, RESERVED
fallback in plfm_chirp_controller_v2, range-decim watchdog in
radar_system_top with gpio_dig7 surfacing, F-3.* MCU error path).
Verified — no residual TODO/FIXME in production RTL or MCU.
Regression infra: tb/cosim/compare_independent.py SKIP-detection bug —
importlib.util.find_spec("scipy.signal") raises ModuleNotFoundError when
the parent scipy package is itself absent (instead of returning None as
the surrounding logic assumed). Wrap in try/except so the regression
runner gets the intended rc=2 SKIP marker rather than a crash that masks
the rest of the script.
Lint sweep: ruff full-repo → 0 errors. Two changes:
- pyproject.toml broadens 5_Simulations/Antenna/**.py exemption from
just T20+ERA to the full set of script-ergonomics rules
(RUF001/002/003 Greek µ/λ/π/θ in physical-units strings, E501 long
matplotlib/numpy lines, RUF005/015/046, E70x one-line setup, B007
tuple-unpack loop vars, B905, BLE001 diag try/except, C401, RET504,
SIM118, PERF40x, ARG001, E402). These are sim/analysis scripts, not
production code — keep substantive bug rules (F unused, B core
bugbears) but drop stylistic noise.
- Auto-fix sweep: 31x F541 (f-string-no-placeholder), 3x F401 (unused
sys import), 2x F841 (dead leftover ref_pat / phases_quant in
array_factor_adar1000_aeris10.py).
.gitignore: cover 9_Firmware/9_2_FPGA/tb/cosim/mf_chain_autocorr.csv
(matched_filter cosim writes here now; was already covered for tb/ but
not tb/cosim/).
Regression baseline (radar_venv):
FPGA : 42/43 — 1 pre-existing T-6 drift cosim fail surfaced by the
SKIP fix above. Three sub-checks now red because PR-O moved
xFFT/MF chain to LogiCORE v9.1 *Scaled* mode (1/2 per stage,
1/2^11 total for N=2048) but compare_independent.py's invariants
(FFT-impulse uniform-spectrum, MF peak-at-injected-delay, MF
peak/median ≥ 5) were written assuming UNSCALED FFT. Not
introduced by this PR — was hidden by the SKIP-detection crash.
Defer to PR-M.4: redesign T-6 invariants (or input amplitudes)
to match scaled-mode arithmetic.
MCU : 34/34 binary suites pass.
GUI : test_v7 150/150 pass.
uv.lock: scipy resolution catch-up (declared in pyproject dev group all
along; lock just hadn't been refreshed after pyproject edits landed).
Bench-side checks: none — this PR is repo hygiene, no firmware/RTL
behaviour change.
61 lines
1.7 KiB
Plaintext
61 lines
1.7 KiB
Plaintext
# Verilog simulation artifacts
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*.vvp
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*.vcd
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# Debug / scratch RTL (not part of the design)
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9_Firmware/9_2_FPGA/debug_*.v
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9_Firmware/9_2_FPGA/tb/tb_fft_debug*.v
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9_Firmware/9_2_FPGA/tb/tb_fft_mini*.v
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9_Firmware/9_2_FPGA/tb/tb_bram_debug.v
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# Local simulation artifacts and CSV outputs
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9_Firmware/9_2_FPGA/cic_*.csv
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9_Firmware/9_2_FPGA/fir_*.csv
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9_Firmware/9_2_FPGA/nco_*.csv
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9_Firmware/9_2_FPGA/ddc_*.csv
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9_Firmware/9_2_FPGA/mf_pipeline_output.csv
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9_Firmware/9_2_FPGA/mf_chain_autocorr.csv
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9_Firmware/9_2_FPGA/rbd_mode00_ramp.csv
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9_Firmware/9_2_FPGA/rbd_mode01_peak.csv
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9_Firmware/9_2_FPGA/rbd_mode10_avg.csv
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9_Firmware/9_2_FPGA/rbd_mode10_ramp.csv
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9_Firmware/9_2_FPGA/rmc_autoscan.csv
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9_Firmware/9_2_FPGA/tb/mf_chain_autocorr.csv
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9_Firmware/9_2_FPGA/tb/rbd_mode00_ramp.csv
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9_Firmware/9_2_FPGA/tb/rbd_mode01_peak.csv
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9_Firmware/9_2_FPGA/tb/rbd_mode10_avg.csv
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9_Firmware/9_2_FPGA/tb/rbd_mode10_ramp.csv
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9_Firmware/9_2_FPGA/tb/rmc_autoscan.csv
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9_Firmware/9_2_FPGA/tb_usb_data_interface.csv
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# Co-sim intermediate CSVs (regenerated by scripts)
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9_Firmware/9_2_FPGA/tb/cosim/rtl_doppler_*.csv
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9_Firmware/9_2_FPGA/tb/cosim/mf_chain_autocorr.csv
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9_Firmware/9_2_FPGA/tb/cosim/compare_doppler_*.csv
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9_Firmware/9_2_FPGA/tb/cosim/rtl_multiseg_*.csv
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# macOS
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.DS_Store
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# Python
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__pycache__/
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*.pyc
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# Local organization/archival folders (not part of repo source)
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10_docs/
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# Local simulation workspaces and generated outputs
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5_Simulations/generated/
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5_Simulations/aeris10_antenna_sim.py
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5_Simulations/aeris10_radar_sim.py
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# Local FPGA report dumps and scratch constraints
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9_Firmware/9_2_FPGA/reports/
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9_Firmware/9_2_FPGA/synth_only.xdc
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# Local timing closure report snapshots
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build*_reports/
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# UART capture logs (generated by tools/uart_capture.py)
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logs/
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