<!--This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License (CC BY-SA) with Design Exception 1.0-->
<eagle version="7.1.0">
<drawing>
<library>
<packages>
<package name="BGA324C80P18X18_1500X1500X150">
</package>
</packages>
<symbols>
<symbol name="XC7S50-1CSGA324C_BANK0">
<pin name="VCCADC_0" direction="pwr"/>
<pin name="VCCBATT_0" direction="pwr"/>
<pin name="VCCO_0" direction="pwr"/>
<pin name="VP_0" direction="pwr"/>
<pin name="VREFP_0" direction="pwr"/>
<pin name="CFGBVS_0" direction="in"/>
<pin name="DONE_0" direction="in"/>
<pin name="PROGRAM_B_0" direction="in"/>
<pin name="TCK_0" direction="in" function="clk"/>
<pin name="TDI_0" direction="in"/>
<pin name="CCLK_0" function="clk"/>
<pin name="DXN_0"/>
<pin name="DXP_0"/>
<pin name="TMS_0"/>
<pin name="M0_0" direction="pas"/>
<pin name="M1_0" direction="pas"/>
<pin name="M2_0" direction="pas"/>
<pin name="INIT_B_0" direction="out"/>
<pin name="TDO_0" direction="out"/>
<pin name="GNDADC_0" direction="pwr"/>
<pin name="VN_0" direction="pwr"/>
<pin name="VREFN_0" direction="pwr"/>
</symbol>
<symbol name="XC7S50-1CSGA324C_BANK14">
<pin name="VCCO_14" direction="pwr"/>
<pin name="IO_0_14"/>
<pin name="IO_25_14"/>
<pin name="IO_L10N_T1_D15_14"/>
<pin name="IO_L10P_T1_D14_14"/>
<pin name="IO_L11N_T1_SRCC_14"/>
<pin name="IO_L11P_T1_SRCC_14"/>
<pin name="IO_L12N_T1_MRCC_14"/>
<pin name="IO_L12P_T1_MRCC_14"/>
<pin name="IO_L13N_T2_MRCC_14"/>
<pin name="IO_L13P_T2_MRCC_14"/>
<pin name="IO_L14N_T2_SRCC_14"/>
<pin name="IO_L14P_T2_SRCC_14"/>
<pin name="IO_L15N_T2_DQS_DOUT_CSO_B_14"/>
<pin name="IO_L15P_T2_DQS_RDWR_B_14"/>
<pin name="IO_L16N_T2_D31_14"/>
<pin name="IO_L16P_T2_CSI_B_14"/>
<pin name="IO_L17N_T2_D29_14"/>
<pin name="IO_L17P_T2_D30_14"/>
<pin name="IO_L18N_T2_D27_14"/>
<pin name="IO_L18P_T2_D28_14"/>
<pin name="IO_L19N_T3_D25_VREF_14"/>
<pin name="IO_L19P_T3_D26_14"/>
<pin name="IO_L1N_T0_D01_DIN_14"/>
<pin name="IO_L1P_T0_D00_MOSI_14"/>
<pin name="IO_L20N_T3_D23_14"/>
<pin name="IO_L20P_T3_D24_14"/>
<pin name="IO_L21N_T3_DQS_D22_14"/>
<pin name="IO_L21P_T3_DQS_14"/>
<pin name="IO_L22N_T3_D20_14"/>
<pin name="IO_L22P_T3_D21_14"/>
<pin name="IO_L23N_T3_D18_14"/>
<pin name="IO_L23P_T3_D19_14"/>
<pin name="IO_L24N_T3_D16_14"/>
<pin name="IO_L24P_T3_D17_14"/>
<pin name="IO_L2N_T0_D03_14"/>
<pin name="IO_L2P_T0_D02_14"/>
<pin name="IO_L3N_T0_DQS_EMCCLK_14"/>
<pin name="IO_L3P_T0_DQS_PUDC_B_14"/>
<pin name="IO_L4N_T0_D05_14"/>
<pin name="IO_L4P_T0_D04_14"/>
<pin name="IO_L5N_T0_D07_14"/>
<pin name="IO_L5P_T0_D06_14"/>
<pin name="IO_L6N_T0_D08_VREF_14"/>
<pin name="IO_L6P_T0_FCS_B_14"/>
<pin name="IO_L7N_T1_D10_14"/>
<pin name="IO_L7P_T1_D09_14"/>
<pin name="IO_L8N_T1_D12_14"/>
<pin name="IO_L8P_T1_D11_14"/>
<pin name="IO_L9N_T1_DQS_D13_14"/>
<pin name="IO_L9P_T1_DQS_14"/>
</symbol>
<symbol name="XC7S50-1CSGA324C_BANK15">
<pin name="VCCO_15" direction="pwr"/>
<pin name="IO_0_15"/>
<pin name="IO_25_15"/>
<pin name="IO_L10N_T1_AD11N_15"/>
<pin name="IO_L10P_T1_AD11P_15"/>
<pin name="IO_L11N_T1_SRCC_15"/>
<pin name="IO_L11P_T1_SRCC_15"/>
<pin name="IO_L12N_T1_MRCC_15"/>
<pin name="IO_L12P_T1_MRCC_15"/>
<pin name="IO_L13N_T2_MRCC_15"/>
<pin name="IO_L13P_T2_MRCC_15"/>
<pin name="IO_L14N_T2_SRCC_15"/>
<pin name="IO_L14P_T2_SRCC_15"/>
<pin name="IO_L15N_T2_DQS_15"/>
<pin name="IO_L15P_T2_DQS_15"/>
<pin name="IO_L16N_T2_15"/>
<pin name="IO_L16P_T2_15"/>
<pin name="IO_L17N_T2_15"/>
<pin name="IO_L17P_T2_15"/>
<pin name="IO_L18N_T2_15"/>
<pin name="IO_L18P_T2_15"/>
<pin name="IO_L19N_T3_VREF_15"/>
<pin name="IO_L19P_T3_15"/>
<pin name="IO_L1N_T0_AD0N_15"/>
<pin name="IO_L1P_T0_AD0P_15"/>
<pin name="IO_L20N_T3_15"/>
<pin name="IO_L20P_T3_15"/>
<pin name="IO_L21N_T3_DQS_15"/>
<pin name="IO_L21P_T3_DQS_15"/>
<pin name="IO_L22N_T3_15"/>
<pin name="IO_L22P_T3_15"/>
<pin name="IO_L23N_T3_15"/>
<pin name="IO_L23P_T3_15"/>
<pin name="IO_L24N_T3_RS0_15"/>
<pin name="IO_L24P_T3_RS1_15"/>
<pin name="IO_L2N_T0_AD8N_15"/>
<pin name="IO_L2P_T0_AD8P_15"/>
<pin name="IO_L3N_T0_DQS_AD1N_15"/>
<pin name="IO_L3P_T0_DQS_AD1P_15"/>
<pin name="IO_L4N_T0_15"/>
<pin name="IO_L4P_T0_15"/>
<pin name="IO_L5N_T0_AD9N_15"/>
<pin name="IO_L5P_T0_AD9P_15"/>
<pin name="IO_L6N_T0_VREF_15"/>
<pin name="IO_L6P_T0_15"/>
<pin name="IO_L7N_T1_AD2N_15"/>
<pin name="IO_L7P_T1_AD2P_15"/>
<pin name="IO_L8N_T1_AD10N_15"/>
<pin name="IO_L8P_T1_AD10P_15"/>
<pin name="IO_L9N_T1_DQS_AD3N_15"/>
<pin name="IO_L9P_T1_DQS_AD3P_15"/>
</symbol>
<symbol name="XC7S50-1CSGA324C_BANK16">
<pin name="VCCO_16" direction="pwr"/>
<pin name="IO_L11N_T1_SRCC_16"/>
<pin name="IO_L11P_T1_SRCC_16"/>
<pin name="IO_L12N_T1_MRCC_16"/>
<pin name="IO_L12P_T1_MRCC_16"/>
<pin name="IO_L13N_T2_MRCC_16"/>
<pin name="IO_L13P_T2_MRCC_16"/>
<pin name="IO_L14N_T2_SRCC_16"/>
<pin name="IO_L14P_T2_SRCC_16"/>
<pin name="IO_L19N_T3_VREF_16"/>
<pin name="IO_L6N_T0_VREF_16"/>
</symbol>
<symbol name="XC7S50-1CSGA324C_BANK34">
<pin name="VCCO_34" direction="pwr"/>
<pin name="IO_0_34"/>
<pin name="IO_25_34"/>
<pin name="IO_L10N_T1_34"/>
<pin name="IO_L10P_T1_34"/>
<pin name="IO_L11N_T1_SRCC_34"/>
<pin name="IO_L11P_T1_SRCC_34"/>
<pin name="IO_L12N_T1_MRCC_34"/>
<pin name="IO_L12P_T1_MRCC_34"/>
<pin name="IO_L13N_T2_MRCC_34"/>
<pin name="IO_L13P_T2_MRCC_34"/>
<pin name="IO_L14N_T2_SRCC_34"/>
<pin name="IO_L14P_T2_SRCC_34"/>
<pin name="IO_L15N_T2_DQS_34"/>
<pin name="IO_L15P_T2_DQS_34"/>
<pin name="IO_L16N_T2_34"/>
<pin name="IO_L16P_T2_34"/>
<pin name="IO_L17N_T2_34"/>
<pin name="IO_L17P_T2_34"/>
<pin name="IO_L18N_T2_34"/>
<pin name="IO_L18P_T2_34"/>
<pin name="IO_L19N_T3_VREF_34"/>
<pin name="IO_L19P_T3_34"/>
<pin name="IO_L1N_T0_34"/>
<pin name="IO_L1P_T0_34"/>
<pin name="IO_L20N_T3_34"/>
<pin name="IO_L20P_T3_34"/>
<pin name="IO_L21N_T3_DQS_34"/>
<pin name="IO_L21P_T3_DQS_34"/>
<pin name="IO_L22N_T3_34"/>
<pin name="IO_L22P_T3_34"/>
<pin name="IO_L23N_T3_34"/>
<pin name="IO_L23P_T3_34"/>
<pin name="IO_L24N_T3_34"/>
<pin name="IO_L24P_T3_34"/>
<pin name="IO_L2N_T0_34"/>
<pin name="IO_L2P_T0_34"/>
<pin name="IO_L3N_T0_DQS_34"/>
<pin name="IO_L3P_T0_DQS_34"/>
<pin name="IO_L4N_T0_34"/>
<pin name="IO_L4P_T0_34"/>
<pin name="IO_L5N_T0_34"/>
<pin name="IO_L5P_T0_34"/>
<pin name="IO_L6N_T0_VREF_34"/>
<pin name="IO_L6P_T0_34"/>
<pin name="IO_L7N_T1_34"/>
<pin name="IO_L7P_T1_34"/>
<pin name="IO_L8N_T1_34"/>
<pin name="IO_L8P_T1_34"/>
<pin name="IO_L9N_T1_DQS_34"/>
<pin name="IO_L9P_T1_DQS_34"/>
</symbol>
<symbol name="XC7S50-1CSGA324C_BANK35">
<pin name="VCCO_35" direction="pwr"/>
<pin name="IO_0_35"/>
<pin name="IO_25_35"/>
<pin name="IO_L10N_T1_AD15N_35"/>
<pin name="IO_L10P_T1_AD15P_35"/>
<pin name="IO_L11N_T1_SRCC_35"/>
<pin name="IO_L11P_T1_SRCC_35"/>
<pin name="IO_L12N_T1_MRCC_35"/>
<pin name="IO_L12P_T1_MRCC_35"/>
<pin name="IO_L13N_T2_MRCC_35"/>
<pin name="IO_L13P_T2_MRCC_35"/>
<pin name="IO_L14N_T2_SRCC_35"/>
<pin name="IO_L14P_T2_SRCC_35"/>
<pin name="IO_L15N_T2_DQS_35"/>
<pin name="IO_L15P_T2_DQS_35"/>
<pin name="IO_L16N_T2_35"/>
<pin name="IO_L16P_T2_35"/>
<pin name="IO_L17N_T2_35"/>
<pin name="IO_L17P_T2_35"/>
<pin name="IO_L18N_T2_35"/>
<pin name="IO_L18P_T2_35"/>
<pin name="IO_L19N_T3_VREF_35"/>
<pin name="IO_L19P_T3_35"/>
<pin name="IO_L1N_T0_AD4N_35"/>
<pin name="IO_L1P_T0_AD4P_35"/>
<pin name="IO_L20N_T3_35"/>
<pin name="IO_L20P_T3_35"/>
<pin name="IO_L21N_T3_DQS_35"/>
<pin name="IO_L21P_T3_DQS_35"/>
<pin name="IO_L22N_T3_35"/>
<pin name="IO_L22P_T3_35"/>
<pin name="IO_L23N_T3_35"/>
<pin name="IO_L23P_T3_35"/>
<pin name="IO_L24N_T3_35"/>
<pin name="IO_L24P_T3_35"/>
<pin name="IO_L2N_T0_AD12N_35"/>
<pin name="IO_L2P_T0_AD12P_35"/>
<pin name="IO_L3N_T0_DQS_AD5N_35"/>
<pin name="IO_L3P_T0_DQS_AD5P_35"/>
<pin name="IO_L4N_T0_35"/>
<pin name="IO_L4P_T0_35"/>
<pin name="IO_L5N_T0_AD13N_35"/>
<pin name="IO_L5P_T0_AD13P_35"/>
<pin name="IO_L6N_T0_VREF_35"/>
<pin name="IO_L6P_T0_35"/>
<pin name="IO_L7N_T1_AD6N_35"/>
<pin name="IO_L7P_T1_AD6P_35"/>
<pin name="IO_L8N_T1_AD14N_35"/>
<pin name="IO_L8P_T1_AD14P_35"/>
<pin name="IO_L9N_T1_DQS_AD7N_35"/>
<pin name="IO_L9P_T1_DQS_AD7P_35"/>
</symbol>
<symbol name="XC7S50-1CSGA324C_POWER">
<pin name="VCCAUX" direction="pwr"/>
<pin name="VCCBRAM" direction="pwr"/>
<pin name="VCCINT1" direction="pwr"/>
<pin name="VCCINT2" direction="pwr"/>
<pin name="GND1" direction="pwr"/>
<pin name="GND2" direction="pwr"/>
<pin name="GND3" direction="pwr"/>
<pin name="GND4" direction="pwr"/>
</symbol>
</symbols>
<devicesets>
<deviceset name="XC7S50-1CSGA324C" prefix="U">
<description> &lt;a href="https://pricing.snapeda.com/parts/XC7S50-1CSGA324C/Xilinx%20Inc./view-part?ref=eda"&gt;Check availability&lt;/a&gt;</description>
<gates>
<gate name="G$1" symbol="XC7S50-1CSGA324C_BANK0"/>
<gate name="G$2" symbol="XC7S50-1CSGA324C_BANK14"/>
<gate name="G$3" symbol="XC7S50-1CSGA324C_BANK15"/>
<gate name="G$4" symbol="XC7S50-1CSGA324C_BANK16"/>
<gate name="G$5" symbol="XC7S50-1CSGA324C_BANK34"/>
<gate name="G$6" symbol="XC7S50-1CSGA324C_BANK35"/>
<gate name="G$7" symbol="XC7S50-1CSGA324C_POWER"/>
</gates>
<devices>
<device name="" package="BGA324C80P18X18_1500X1500X150">
<connects>
<connect gate="G$1" pin="CCLK_0" pad="C8"/>
<connect gate="G$1" pin="CFGBVS_0" pad="V9"/>
<connect gate="G$1" pin="DONE_0" pad="V8"/>
<connect gate="G$1" pin="DXN_0" pad="L9"/>
<connect gate="G$1" pin="DXP_0" pad="L10"/>
<connect gate="G$1" pin="GNDADC_0" pad="H9"/>
<connect gate="G$1" pin="INIT_B_0" pad="U8"/>
<connect gate="G$1" pin="M0_0" pad="T10"/>
<connect gate="G$1" pin="M1_0" pad="U10"/>
<connect gate="G$1" pin="M2_0" pad="U9"/>
<connect gate="G$1" pin="PROGRAM_B_0" pad="R8"/>
<connect gate="G$1" pin="TCK_0" pad="D9"/>
<connect gate="G$1" pin="TDI_0" pad="R9"/>
<connect gate="G$1" pin="TDO_0" pad="T8"/>
<connect gate="G$1" pin="TMS_0" pad="T9"/>
<connect gate="G$1" pin="VCCADC_0" pad="H10"/>
<connect gate="G$1" pin="VCCBATT_0" pad="B8"/>
<connect gate="G$1" pin="VCCO_0" pad="D8 V10"/>
<connect gate="G$1" pin="VN_0" pad="K9"/>
<connect gate="G$1" pin="VP_0" pad="J10"/>
<connect gate="G$1" pin="VREFN_0" pad="J9"/>
<connect gate="G$1" pin="VREFP_0" pad="K10"/>
<connect gate="G$2" pin="IO_0_14" pad="L13"/>
<connect gate="G$2" pin="IO_25_14" pad="R12"/>
<connect gate="G$2" pin="IO_L10N_T1_D15_14" pad="T18"/>
<connect gate="G$2" pin="IO_L10P_T1_D14_14" pad="R18"/>
<connect gate="G$2" pin="IO_L11N_T1_SRCC_14" pad="P15"/>
<connect gate="G$2" pin="IO_L11P_T1_SRCC_14" pad="P14"/>
<connect gate="G$2" pin="IO_L12N_T1_MRCC_14" pad="P16"/>
<connect gate="G$2" pin="IO_L12P_T1_MRCC_14" pad="N15"/>
<connect gate="G$2" pin="IO_L13N_T2_MRCC_14" pad="T14"/>
<connect gate="G$2" pin="IO_L13P_T2_MRCC_14" pad="R14"/>
<connect gate="G$2" pin="IO_L14N_T2_SRCC_14" pad="R17"/>
<connect gate="G$2" pin="IO_L14P_T2_SRCC_14" pad="R16"/>
<connect gate="G$2" pin="IO_L15N_T2_DQS_DOUT_CSO_B_14" pad="U18"/>
<connect gate="G$2" pin="IO_L15P_T2_DQS_RDWR_B_14" pad="U17"/>
<connect gate="G$2" pin="IO_L16N_T2_D31_14" pad="V17"/>
<connect gate="G$2" pin="IO_L16P_T2_CSI_B_14" pad="U16"/>
<connect gate="G$2" pin="IO_L17N_T2_D29_14" pad="T15"/>
<connect gate="G$2" pin="IO_L17P_T2_D30_14" pad="R15"/>
<connect gate="G$2" pin="IO_L18N_T2_D27_14" pad="V16"/>
<connect gate="G$2" pin="IO_L18P_T2_D28_14" pad="U15"/>
<connect gate="G$2" pin="IO_L19N_T3_D25_VREF_14" pad="R13"/>
<connect gate="G$2" pin="IO_L19P_T3_D26_14" pad="P13"/>
<connect gate="G$2" pin="IO_L1N_T0_D01_DIN_14" pad="K18"/>
<connect gate="G$2" pin="IO_L1P_T0_D00_MOSI_14" pad="K17"/>
<connect gate="G$2" pin="IO_L20N_T3_D23_14" pad="V15"/>
<connect gate="G$2" pin="IO_L20P_T3_D24_14" pad="V14"/>
<connect gate="G$2" pin="IO_L21N_T3_DQS_D22_14" pad="V13"/>
<connect gate="G$2" pin="IO_L21P_T3_DQS_14" pad="U12"/>
<connect gate="G$2" pin="IO_L22N_T3_D20_14" pad="T13"/>
<connect gate="G$2" pin="IO_L22P_T3_D21_14" pad="T12"/>
<connect gate="G$2" pin="IO_L23N_T3_D18_14" pad="T11"/>
<connect gate="G$2" pin="IO_L23P_T3_D19_14" pad="R11"/>
<connect gate="G$2" pin="IO_L24N_T3_D16_14" pad="V12"/>
<connect gate="G$2" pin="IO_L24P_T3_D17_14" pad="U11"/>
<connect gate="G$2" pin="IO_L2N_T0_D03_14" pad="M15"/>
<connect gate="G$2" pin="IO_L2P_T0_D02_14" pad="L14"/>
<connect gate="G$2" pin="IO_L3N_T0_DQS_EMCCLK_14" pad="L16"/>
<connect gate="G$2" pin="IO_L3P_T0_DQS_PUDC_B_14" pad="L15"/>
<connect gate="G$2" pin="IO_L4N_T0_D05_14" pad="L18"/>
<connect gate="G$2" pin="IO_L4P_T0_D04_14" pad="L17"/>
<connect gate="G$2" pin="IO_L5N_T0_D07_14" pad="N14"/>
<connect gate="G$2" pin="IO_L5P_T0_D06_14" pad="M14"/>
<connect gate="G$2" pin="IO_L6N_T0_D08_VREF_14" pad="N13"/>
<connect gate="G$2" pin="IO_L6P_T0_FCS_B_14" pad="M13"/>
<connect gate="G$2" pin="IO_L7N_T1_D10_14" pad="M17"/>
<connect gate="G$2" pin="IO_L7P_T1_D09_14" pad="M16"/>
<connect gate="G$2" pin="IO_L8N_T1_D12_14" pad="N18"/>
<connect gate="G$2" pin="IO_L8P_T1_D11_14" pad="M18"/>
<connect gate="G$2" pin="IO_L9N_T1_DQS_D13_14" pad="P18"/>
<connect gate="G$2" pin="IO_L9P_T1_DQS_14" pad="P17"/>
<connect gate="G$2" pin="VCCO_14" pad="N17 T16 U13"/>
<connect gate="G$3" pin="IO_0_15" pad="G13"/>
<connect gate="G$3" pin="IO_25_15" pad="K13"/>
<connect gate="G$3" pin="IO_L10N_T1_AD11N_15" pad="E17"/>
<connect gate="G$3" pin="IO_L10P_T1_AD11P_15" pad="E16"/>
<connect gate="G$3" pin="IO_L11N_T1_SRCC_15" pad="C18"/>
<connect gate="G$3" pin="IO_L11P_T1_SRCC_15" pad="D18"/>
<connect gate="G$3" pin="IO_L12N_T1_MRCC_15" pad="D15"/>
<connect gate="G$3" pin="IO_L12P_T1_MRCC_15" pad="D14"/>
<connect gate="G$3" pin="IO_L13N_T2_MRCC_15" pad="F15"/>
<connect gate="G$3" pin="IO_L13P_T2_MRCC_15" pad="F14"/>
<connect gate="G$3" pin="IO_L14N_T2_SRCC_15" pad="G17"/>
<connect gate="G$3" pin="IO_L14P_T2_SRCC_15" pad="G16"/>
<connect gate="G$3" pin="IO_L15N_T2_DQS_15" pad="E15"/>
<connect gate="G$3" pin="IO_L15P_T2_DQS_15" pad="E14"/>
<connect gate="G$3" pin="IO_L16N_T2_15" pad="E18"/>
<connect gate="G$3" pin="IO_L16P_T2_15" pad="F18"/>
<connect gate="G$3" pin="IO_L17N_T2_15" pad="E13"/>
<connect gate="G$3" pin="IO_L17P_T2_15" pad="F13"/>
<connect gate="G$3" pin="IO_L18N_T2_15" pad="G15"/>
<connect gate="G$3" pin="IO_L18P_T2_15" pad="H15"/>
<connect gate="G$3" pin="IO_L19N_T3_VREF_15" pad="J16"/>
<connect gate="G$3" pin="IO_L19P_T3_15" pad="K16"/>
<connect gate="G$3" pin="IO_L1N_T0_AD0N_15" pad="A13"/>
<connect gate="G$3" pin="IO_L1P_T0_AD0P_15" pad="B13"/>
<connect gate="G$3" pin="IO_L20N_T3_15" pad="H14"/>
<connect gate="G$3" pin="IO_L20P_T3_15" pad="H13"/>
<connect gate="G$3" pin="IO_L21N_T3_DQS_15" pad="G18"/>
<connect gate="G$3" pin="IO_L21P_T3_DQS_15" pad="H18"/>
<connect gate="G$3" pin="IO_L22N_T3_15" pad="H17"/>
<connect gate="G$3" pin="IO_L22P_T3_15" pad="H16"/>
<connect gate="G$3" pin="IO_L23N_T3_15" pad="J15"/>
<connect gate="G$3" pin="IO_L23P_T3_15" pad="K14"/>
<connect gate="G$3" pin="IO_L24N_T3_RS0_15" pad="J14"/>
<connect gate="G$3" pin="IO_L24P_T3_RS1_15" pad="J13"/>
<connect gate="G$3" pin="IO_L2N_T0_AD8N_15" pad="A14"/>
<connect gate="G$3" pin="IO_L2P_T0_AD8P_15" pad="B14"/>
<connect gate="G$3" pin="IO_L3N_T0_DQS_AD1N_15" pad="A15"/>
<connect gate="G$3" pin="IO_L3P_T0_DQS_AD1P_15" pad="B15"/>
<connect gate="G$3" pin="IO_L4N_T0_15" pad="A16"/>
<connect gate="G$3" pin="IO_L4P_T0_15" pad="B16"/>
<connect gate="G$3" pin="IO_L5N_T0_AD9N_15" pad="D12"/>
<connect gate="G$3" pin="IO_L5P_T0_AD9P_15" pad="E12"/>
<connect gate="G$3" pin="IO_L6N_T0_VREF_15" pad="C14"/>
<connect gate="G$3" pin="IO_L6P_T0_15" pad="C13"/>
<connect gate="G$3" pin="IO_L7N_T1_AD2N_15" pad="A17"/>
<connect gate="G$3" pin="IO_L7P_T1_AD2P_15" pad="B17"/>
<connect gate="G$3" pin="IO_L8N_T1_AD10N_15" pad="B18"/>
<connect gate="G$3" pin="IO_L8P_T1_AD10P_15" pad="C17"/>
<connect gate="G$3" pin="IO_L9N_T1_DQS_AD3N_15" pad="D17"/>
<connect gate="G$3" pin="IO_L9P_T1_DQS_AD3P_15" pad="D16"/>
<connect gate="G$3" pin="VCCO_15" pad="C15 F16 J17"/>
<connect gate="G$4" pin="IO_L11N_T1_SRCC_16" pad="C9"/>
<connect gate="G$4" pin="IO_L11P_T1_SRCC_16" pad="C10"/>
<connect gate="G$4" pin="IO_L12N_T1_MRCC_16" pad="A9"/>
<connect gate="G$4" pin="IO_L12P_T1_MRCC_16" pad="A10"/>
<connect gate="G$4" pin="IO_L13N_T2_MRCC_16" pad="C11"/>
<connect gate="G$4" pin="IO_L13P_T2_MRCC_16" pad="C12"/>
<connect gate="G$4" pin="IO_L14N_T2_SRCC_16" pad="A11"/>
<connect gate="G$4" pin="IO_L14P_T2_SRCC_16" pad="B11"/>
<connect gate="G$4" pin="IO_L19N_T3_VREF_16" pad="D10"/>
<connect gate="G$4" pin="IO_L6N_T0_VREF_16" pad="D11"/>
<connect gate="G$4" pin="VCCO_16" pad="B10 B12"/>
<connect gate="G$5" pin="IO_0_34" pad="J6"/>
<connect gate="G$5" pin="IO_25_34" pad="P7"/>
<connect gate="G$5" pin="IO_L10N_T1_34" pad="N4"/>
<connect gate="G$5" pin="IO_L10P_T1_34" pad="N5"/>
<connect gate="G$5" pin="IO_L11N_T1_SRCC_34" pad="P1"/>
<connect gate="G$5" pin="IO_L11P_T1_SRCC_34" pad="P2"/>
<connect gate="G$5" pin="IO_L12N_T1_MRCC_34" pad="R1"/>
<connect gate="G$5" pin="IO_L12P_T1_MRCC_34" pad="R2"/>
<connect gate="G$5" pin="IO_L13N_T2_MRCC_34" pad="T2"/>
<connect gate="G$5" pin="IO_L13P_T2_MRCC_34" pad="R3"/>
<connect gate="G$5" pin="IO_L14N_T2_SRCC_34" pad="U1"/>
<connect gate="G$5" pin="IO_L14P_T2_SRCC_34" pad="T1"/>
<connect gate="G$5" pin="IO_L15N_T2_DQS_34" pad="U2"/>
<connect gate="G$5" pin="IO_L15P_T2_DQS_34" pad="U3"/>
<connect gate="G$5" pin="IO_L16N_T2_34" pad="V2"/>
<connect gate="G$5" pin="IO_L16P_T2_34" pad="V3"/>
<connect gate="G$5" pin="IO_L17N_T2_34" pad="V4"/>
<connect gate="G$5" pin="IO_L17P_T2_34" pad="V5"/>
<connect gate="G$5" pin="IO_L18N_T2_34" pad="T3"/>
<connect gate="G$5" pin="IO_L18P_T2_34" pad="R4"/>
<connect gate="G$5" pin="IO_L19N_T3_VREF_34" pad="P5"/>
<connect gate="G$5" pin="IO_L19P_T3_34" pad="P6"/>
<connect gate="G$5" pin="IO_L1N_T0_34" pad="L4"/>
<connect gate="G$5" pin="IO_L1P_T0_34" pad="K4"/>
<connect gate="G$5" pin="IO_L20N_T3_34" pad="V6"/>
<connect gate="G$5" pin="IO_L20P_T3_34" pad="V7"/>
<connect gate="G$5" pin="IO_L21N_T3_DQS_34" pad="T4"/>
<connect gate="G$5" pin="IO_L21P_T3_DQS_34" pad="R5"/>
<connect gate="G$5" pin="IO_L22N_T3_34" pad="T5"/>
<connect gate="G$5" pin="IO_L22P_T3_34" pad="T6"/>
<connect gate="G$5" pin="IO_L23N_T3_34" pad="R6"/>
<connect gate="G$5" pin="IO_L23P_T3_34" pad="R7"/>
<connect gate="G$5" pin="IO_L24N_T3_34" pad="U6"/>
<connect gate="G$5" pin="IO_L24P_T3_34" pad="U7"/>
<connect gate="G$5" pin="IO_L2N_T0_34" pad="K2"/>
<connect gate="G$5" pin="IO_L2P_T0_34" pad="K3"/>
<connect gate="G$5" pin="IO_L3N_T0_DQS_34" pad="L1"/>
<connect gate="G$5" pin="IO_L3P_T0_DQS_34" pad="K1"/>
<connect gate="G$5" pin="IO_L4N_T0_34" pad="L6"/>
<connect gate="G$5" pin="IO_L4P_T0_34" pad="K6"/>
<connect gate="G$5" pin="IO_L5N_T0_34" pad="M4"/>
<connect gate="G$5" pin="IO_L5P_T0_34" pad="L5"/>
<connect gate="G$5" pin="IO_L6N_T0_VREF_34" pad="M5"/>
<connect gate="G$5" pin="IO_L6P_T0_34" pad="M6"/>
<connect gate="G$5" pin="IO_L7N_T1_34" pad="M2"/>
<connect gate="G$5" pin="IO_L7P_T1_34" pad="M3"/>
<connect gate="G$5" pin="IO_L8N_T1_34" pad="N1"/>
<connect gate="G$5" pin="IO_L8P_T1_34" pad="M1"/>
<connect gate="G$5" pin="IO_L9N_T1_DQS_34" pad="N2"/>
<connect gate="G$5" pin="IO_L9P_T1_DQS_34" pad="N3"/>
<connect gate="G$5" pin="VCCO_34" pad="L3 P4 U5"/>
<connect gate="G$6" pin="IO_0_35" pad="F6"/>
<connect gate="G$6" pin="IO_25_35" pad="J5"/>
<connect gate="G$6" pin="IO_L10N_T1_AD15N_35" pad="A2"/>
<connect gate="G$6" pin="IO_L10P_T1_AD15P_35" pad="A3"/>
<connect gate="G$6" pin="IO_L11N_T1_SRCC_35" pad="B2"/>
<connect gate="G$6" pin="IO_L11P_T1_SRCC_35" pad="C2"/>
<connect gate="G$6" pin="IO_L12N_T1_MRCC_35" pad="B1"/>
<connect gate="G$6" pin="IO_L12P_T1_MRCC_35" pad="C1"/>
<connect gate="G$6" pin="IO_L13N_T2_MRCC_35" pad="E4"/>
<connect gate="G$6" pin="IO_L13P_T2_MRCC_35" pad="F4"/>
<connect gate="G$6" pin="IO_L14N_T2_SRCC_35" pad="D1"/>
<connect gate="G$6" pin="IO_L14P_T2_SRCC_35" pad="E1"/>
<connect gate="G$6" pin="IO_L15N_T2_DQS_35" pad="E3"/>
<connect gate="G$6" pin="IO_L15P_T2_DQS_35" pad="F3"/>
<connect gate="G$6" pin="IO_L16N_T2_35" pad="D2"/>
<connect gate="G$6" pin="IO_L16P_T2_35" pad="E2"/>
<connect gate="G$6" pin="IO_L17N_T2_35" pad="F5"/>
<connect gate="G$6" pin="IO_L17P_T2_35" pad="G5"/>
<connect gate="G$6" pin="IO_L18N_T2_35" pad="F1"/>
<connect gate="G$6" pin="IO_L18P_T2_35" pad="F2"/>
<connect gate="G$6" pin="IO_L19N_T3_VREF_35" pad="J3"/>
<connect gate="G$6" pin="IO_L19P_T3_35" pad="J4"/>
<connect gate="G$6" pin="IO_L1N_T0_AD4N_35" pad="A7"/>
<connect gate="G$6" pin="IO_L1P_T0_AD4P_35" pad="A8"/>
<connect gate="G$6" pin="IO_L20N_T3_35" pad="H2"/>
<connect gate="G$6" pin="IO_L20P_T3_35" pad="H3"/>
<connect gate="G$6" pin="IO_L21N_T3_DQS_35" pad="G1"/>
<connect gate="G$6" pin="IO_L21P_T3_DQS_35" pad="G2"/>
<connect gate="G$6" pin="IO_L22N_T3_35" pad="H4"/>
<connect gate="G$6" pin="IO_L22P_T3_35" pad="H5"/>
<connect gate="G$6" pin="IO_L23N_T3_35" pad="J1"/>
<connect gate="G$6" pin="IO_L23P_T3_35" pad="J2"/>
<connect gate="G$6" pin="IO_L24N_T3_35" pad="G6"/>
<connect gate="G$6" pin="IO_L24P_T3_35" pad="H6"/>
<connect gate="G$6" pin="IO_L2N_T0_AD12N_35" pad="B5"/>
<connect gate="G$6" pin="IO_L2P_T0_AD12P_35" pad="C5"/>
<connect gate="G$6" pin="IO_L3N_T0_DQS_AD5N_35" pad="C7"/>
<connect gate="G$6" pin="IO_L3P_T0_DQS_AD5P_35" pad="D7"/>
<connect gate="G$6" pin="IO_L4N_T0_35" pad="A6"/>
<connect gate="G$6" pin="IO_L4P_T0_35" pad="B7"/>
<connect gate="G$6" pin="IO_L5N_T0_AD13N_35" pad="D6"/>
<connect gate="G$6" pin="IO_L5P_T0_AD13P_35" pad="E6"/>
<connect gate="G$6" pin="IO_L6N_T0_VREF_35" pad="D5"/>
<connect gate="G$6" pin="IO_L6P_T0_35" pad="E5"/>
<connect gate="G$6" pin="IO_L7N_T1_AD6N_35" pad="B4"/>
<connect gate="G$6" pin="IO_L7P_T1_AD6P_35" pad="C4"/>
<connect gate="G$6" pin="IO_L8N_T1_AD14N_35" pad="B3"/>
<connect gate="G$6" pin="IO_L8P_T1_AD14P_35" pad="C3"/>
<connect gate="G$6" pin="IO_L9N_T1_DQS_AD7N_35" pad="A4"/>
<connect gate="G$6" pin="IO_L9P_T1_DQS_AD7P_35" pad="A5"/>
<connect gate="G$6" pin="VCCO_35" pad="B6 D4 G3"/>
<connect gate="G$7" pin="GND1" pad="A1 A12 A18 B9 C6 C16 D3 D13 E8 E10 F7 F9 F11 F17 G4"/>
<connect gate="G$7" pin="GND2" pad="G8 G10 G12 G14 H1 H7 H11 J8 J12 J18 K5 K7 K11 K15 L2"/>
<connect gate="G$7" pin="GND3" pad="L8 L12 M7 M9 M11 N6 N8 N10 N12 N16 P3 P9 P11 R10 T7"/>
<connect gate="G$7" pin="GND4" pad="T17 U4 U14 V1 V11 V18"/>
<connect gate="G$7" pin="VCCAUX" pad="F12 H12 K12 M12 P12"/>
<connect gate="G$7" pin="VCCBRAM" pad="L7 N7"/>
<connect gate="G$7" pin="VCCINT1" pad="E7 E9 E11 F8 F10 G7 G9 G11 H8 J7 J11 K8 L11 M8 M10"/>
<connect gate="G$7" pin="VCCINT2" pad="N9 N11 P8 P10"/>
</connects>
<technologies>
<technology name="">
<attribute name="MF" value="Xilinx Inc."/>
<attribute name="Description" value="
                        
                            Spartan®-7 Field Programmable Gate Array (FPGA) IC 210 2764800 52160 324-LFBGA, CSPBGA
                        
                    "/>
<attribute name="Package" value="LFBGA-324 Xilinx"/>
<attribute name="Price" value="None"/>
<attribute name="SnapEDA_Link" value="https://www.snapeda.com/parts/XC7S50-1CSGA324C/Xilinx/view-part/?ref=snap"/>
<attribute name="MP" value="XC7S50-1CSGA324C"/>
<attribute name="Availability" value="In Stock"/>
<attribute name="Check_prices" value="https://www.snapeda.com/parts/XC7S50-1CSGA324C/Xilinx/view-part/?ref=eda"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
</devicesets>
</library>
</drawing>
</eagle>
