<?xml version="1.0" encoding="utf-8"?>
<!DOCTYPE eagle SYSTEM "eagle.dtd">
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<drawing>
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<package name="UDFN8_8MA1_ADO">
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<package name="CONN_10118192-0002LF_AMP">
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<package name="ADT1-1+_MNC">
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<package name="RHL0020A">
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<package name="UFQFPN20_3X3_STM">
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<package name="LGA-14L_2P5X3X0P83_STM">
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<package name="HRP5_ROM">
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<package name="CONN_1805375_RSP">
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<symbols>
<symbol name="AD9361-CSH_A">
<pin name="RX2A_N" direction="in"/>
<pin name="RX2A_P" direction="in"/>
<pin name="DNC" direction="nc"/>
<pin name="VSSA_2" direction="pas"/>
<pin name="TX_MON2" direction="in"/>
<pin name="VSSA_3" direction="pas"/>
<pin name="TX2A_N" direction="out"/>
<pin name="TX2A_P" direction="out"/>
<pin name="TX2B_N" direction="out"/>
<pin name="TX2B_P" direction="out"/>
<pin name="VDDA1P1_TX_VCO" direction="pwr"/>
<pin name="TX_EXT_LO_IN" direction="in"/>
<pin name="VSSA_4" direction="pas"/>
<pin name="VSSA_5" direction="pas"/>
<pin name="AUXDAC1" direction="out"/>
<pin name="GPO_3" direction="out"/>
<pin name="GPO_2" direction="out"/>
<pin name="GPO_1" direction="out"/>
<pin name="GPO_0" direction="out"/>
<pin name="VDD_GPO" direction="pwr"/>
<pin name="VDDA_1P3_TX_LO" direction="pwr"/>
<pin name="VDDA1P3_TX_VCO_LDO" direction="pwr"/>
<pin name="TX_VCO_LDO_OUT" direction="out"/>
<pin name="VSSA_6" direction="pas"/>
<pin name="RX2C_P" direction="in"/>
<pin name="VSSA_7" direction="pas"/>
<pin name="AUXDAC2" direction="out"/>
<pin name="TEST/ENABLE" direction="pas"/>
<pin name="CTRL_IN0" direction="in"/>
<pin name="CTRL_IN1" direction="in"/>
<pin name="VSSA_8" direction="pas"/>
<pin name="VSSA_9" direction="pas"/>
<pin name="VSSA_10" direction="pas"/>
<pin name="VSSA_11" direction="pas"/>
<pin name="VSSA_12" direction="pas"/>
<pin name="VSSA_13" direction="pas"/>
<pin name="RX2C_N" direction="in"/>
<pin name="VDDA1P3_RX_RF" direction="pwr"/>
<pin name="VDDA1P3_RX_TX" direction="pwr"/>
<pin name="CTRL_OUT0" direction="out"/>
<pin name="CTRL_IN3" direction="in"/>
<pin name="CTRL_IN2" direction="in"/>
<pin name="P0_D9/TX_D4_P"/>
<pin name="P0_D7/TX_D3_P"/>
<pin name="P0_D5/TX_D2_P"/>
<pin name="P0_D3/TX_D1_P"/>
<pin name="P0_D1/TX_D0_P"/>
<pin name="VSSD_2" direction="pas"/>
<pin name="RX2B_P" direction="in"/>
<pin name="VDDA1P3_RX_LO" direction="pwr"/>
<pin name="VDDA1P3_TX_LO_BUFFER" direction="pwr"/>
<pin name="CTRL_OUT1" direction="out"/>
<pin name="CTRL_OUT2" direction="out"/>
<pin name="CTRL_OUT3" direction="out"/>
<pin name="P0_D11/TX_D5_P"/>
<pin name="P0_D8/TX_D4_N"/>
<pin name="P0_D6/TX_D3_N"/>
<pin name="P0_D4/TX_D2_N"/>
<pin name="P0_D2/TX_D1_N"/>
<pin name="P0_D0/TX_D0_N"/>
<pin name="RX2B_N" direction="in"/>
<pin name="VDDA1P3_RX_VCO_LDO" direction="pwr"/>
<pin name="VSSA" direction="pas"/>
<pin name="CTRL_OUT6" direction="out"/>
<pin name="CTRL_OUT5" direction="out"/>
<pin name="CTRL_OUT4" direction="out"/>
<pin name="VSSD_3" direction="pas"/>
<pin name="P0_D10/TX_D5_N"/>
<pin name="VSSD_4" direction="pas"/>
<pin name="FB_CLK_P" direction="in"/>
<pin name="VSSD" direction="pas"/>
<pin name="VDDD1P3_DIG" direction="pwr"/>
</symbol>
<symbol name="AD9361-CSH_B">
<pin name="RX_EXT_LO_IN" direction="pas"/>
<pin name="RX_VCO_LDO_OUT" direction="out"/>
<pin name="VDDA1P1_RX_VCO" direction="pwr"/>
<pin name="CTRL_OUT7" direction="out"/>
<pin name="EN_AGC" direction="in"/>
<pin name="ENABLE" direction="in"/>
<pin name="RX_FRAME_N" direction="pas"/>
<pin name="RX_FRAME_P" direction="pas"/>
<pin name="TX_FRAME_P" direction="pas"/>
<pin name="FB_CLK_N" direction="in"/>
<pin name="DATA_CLK_P" direction="pas"/>
<pin name="VSSD_2" direction="pas"/>
<pin name="RX1B_P" direction="in"/>
<pin name="VSSA_2" direction="pas"/>
<pin name="VSSA_3" direction="pas"/>
<pin name="TXNRX" direction="in"/>
<pin name="SYNC_IN" direction="in"/>
<pin name="VSSA_4" direction="pas"/>
<pin name="VSSD_3" direction="pas"/>
<pin name="P1_D11/RX_D5_P"/>
<pin name="TX_FRAME_N" direction="pas"/>
<pin name="VSSD_4" direction="pas"/>
<pin name="DATA_CLK_N" direction="pas"/>
<pin name="VDD_INTERFACE" direction="pwr"/>
<pin name="RX1B_N" direction="in"/>
<pin name="VSSA_5" direction="pas"/>
<pin name="VDDA1P3_RX_SYNTH" direction="pwr"/>
<pin name="SPI_DI" direction="in"/>
<pin name="SPI_CLK" direction="in"/>
<pin name="CLK_OUT" direction="out"/>
<pin name="P1_D10/RX_D5_N"/>
<pin name="P1_D9/RX_D4_P"/>
<pin name="P1_D7/RX_D3_P"/>
<pin name="P1_D5/RX_D2_P"/>
<pin name="P1_D3/RX_D1_P"/>
<pin name="P1_D1/RX_D0_P"/>
<pin name="RX1C_P" direction="in"/>
<pin name="VSSA_6" direction="pas"/>
<pin name="VDDA1P3_TX_SYNTH" direction="pwr"/>
<pin name="VDDA1P3_BB" direction="pwr"/>
<pin name="RESETB" direction="in"/>
<pin name="SPI_ENB" direction="in"/>
<pin name="P1_D8/RX_D4_N"/>
<pin name="P1_D6/RX_D3_N"/>
<pin name="P1_D4/RX_D2_N"/>
<pin name="P1_D2/RX_D1_N"/>
<pin name="P1_D0/RX_D0_N"/>
<pin name="VSSD" direction="pas"/>
<pin name="RX1C_N" direction="in"/>
<pin name="VSSA_7" direction="pas"/>
<pin name="VSSA_8" direction="pas"/>
<pin name="RBIAS" direction="pas"/>
<pin name="AUXADC" direction="in"/>
<pin name="SPI_DO" direction="out"/>
<pin name="VSSA_9" direction="pas"/>
<pin name="VSSA_10" direction="pas"/>
<pin name="VSSA_11" direction="pas"/>
<pin name="VSSA_12" direction="pas"/>
<pin name="VSSA_13" direction="pas"/>
<pin name="VSSA_14" direction="pas"/>
<pin name="RX1A_P" direction="in"/>
<pin name="RX1A_N" direction="in"/>
<pin name="DNC" direction="nc"/>
<pin name="VSSA_15" direction="pas"/>
<pin name="TX_MON1" direction="in"/>
<pin name="VSSA" direction="pas"/>
<pin name="TX1A_P" direction="out"/>
<pin name="TX1A_N" direction="out"/>
<pin name="TX1B_P" direction="out"/>
<pin name="TX1B_N" direction="out"/>
<pin name="XTALP" direction="in"/>
<pin name="XTALN" direction="in"/>
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<symbol name="SI5351A-B-GM">
<pin name="XA" direction="in"/>
<pin name="XB" direction="in"/>
<pin name="A0" direction="in"/>
<pin name="SCL" direction="in"/>
<pin name="SDA"/>
<pin name="SSEN" direction="in"/>
<pin name="OEB" direction="in"/>
<pin name="CLK3" direction="out"/>
<pin name="CLK2" direction="out"/>
<pin name="VDDOB" direction="pwr"/>
<pin name="VDDOA" direction="pwr"/>
<pin name="CLK1" direction="out"/>
<pin name="CLK0" direction="out"/>
<pin name="VDDOD" direction="pwr"/>
<pin name="CLK7" direction="out"/>
<pin name="CLK6" direction="out"/>
<pin name="CLK5" direction="out"/>
<pin name="VDDOC" direction="pwr"/>
<pin name="CLK4" direction="out"/>
<pin name="VDD" direction="pwr"/>
<pin name="EPAD" direction="pas"/>
</symbol>
<symbol name="XC7A100T-FGG484_A">
<pin name="IO_L1N_T0_AD4N_35"/>
<pin name="GND_2" direction="pas"/>
<pin name="GND_3" direction="pas"/>
<pin name="MGTPTXN0_216" direction="out"/>
<pin name="GND_4" direction="pas"/>
<pin name="MGTPTXN2_216" direction="out"/>
<pin name="GND_5" direction="pas"/>
<pin name="MGTPRXN0_216" direction="in"/>
<pin name="GND_6" direction="pas"/>
<pin name="IO_L1P_T0_AD4P_35"/>
<pin name="IO_L2N_T0_AD12N_35"/>
<pin name="GND_7" direction="pas"/>
<pin name="MGTPTXP0_216" direction="out"/>
<pin name="MGTAVTT_2" direction="pwr"/>
<pin name="MGTPTXP2_216" direction="out"/>
<pin name="MGTAVTT_3" direction="pwr"/>
<pin name="MGTPRXP0_216" direction="in"/>
<pin name="MGTAVTT_4" direction="pwr"/>
<pin name="VCCO_35_2" direction="pwr"/>
<pin name="IO_L2P_T0_AD12P_35"/>
<pin name="GND_8" direction="pas"/>
<pin name="MGTAVTT_5" direction="pwr"/>
<pin name="MGTPTXN1_216" direction="out"/>
<pin name="GND_9" direction="pas"/>
<pin name="MGTPTXN3_216" direction="out"/>
<pin name="MGTAVTT" direction="pwr"/>
<pin name="MGTPRXN3_216" direction="in"/>
<pin name="IO_L3N_T0_DQS_AD5N_35"/>
<pin name="IO_L4N_T0_35"/>
<pin name="GND_10" direction="pas"/>
<pin name="GND_11" direction="pas"/>
<pin name="MGTPTXP1_216" direction="out"/>
<pin name="MGTAVCC_2" direction="pwr"/>
<pin name="MGTPTXP3_216" direction="out"/>
<pin name="GND_12" direction="pas"/>
<pin name="MGTPRXP3_216" direction="in"/>
<pin name="IO_L3P_T0_DQS_AD5P_35"/>
<pin name="IO_L4P_T0_35"/>
<pin name="IO_L6N_T0_VREF_35"/>
<pin name="GND_13" direction="pas"/>
<pin name="GND_14" direction="pas"/>
<pin name="MGTREFCLK0N_216" direction="in"/>
<pin name="GND_15" direction="pas"/>
<pin name="MGTAVCC_3" direction="pwr"/>
<pin name="GND_16" direction="pas"/>
<pin name="IO_L5N_T0_AD13N_35"/>
<pin name="VCCO_35_3" direction="pwr"/>
<pin name="IO_L6P_T0_35"/>
<pin name="IO_0_35"/>
<pin name="GND_17" direction="pas"/>
<pin name="MGTREFCLK0P_216" direction="in"/>
<pin name="MGTAVCC_4" direction="pwr"/>
<pin name="MGTRREF_216" direction="in"/>
<pin name="MGTAVCC" direction="pwr"/>
<pin name="IO_L5P_T0_AD13P_35"/>
<pin name="IO_L8N_T1_AD14N_35"/>
<pin name="IO_L11N_T1_SRCC_35"/>
<pin name="IO_L12N_T1_MRCC_35"/>
<pin name="GND_18" direction="pas"/>
<pin name="GND_19" direction="pas"/>
<pin name="GND_20" direction="pas"/>
<pin name="GND_21" direction="pas"/>
<pin name="GND_22" direction="pas"/>
<pin name="GND_23" direction="pas"/>
<pin name="IO_L8P_T1_AD14P_35"/>
<pin name="IO_L11P_T1_SRCC_35"/>
<pin name="IO_L12P_T1_MRCC_35"/>
<pin name="IO_L10N_T1_AD15N_35"/>
<pin name="VCCO_35_4" direction="pwr"/>
<pin name="GND_24" direction="pas"/>
<pin name="VCCINT_2" direction="pwr"/>
<pin name="GND_25" direction="pas"/>
<pin name="IO_L7N_T1_AD6N_35"/>
<pin name="IO_L9N_T1_DQS_AD7N_35"/>
<pin name="VCCO_35" direction="pwr"/>
<pin name="IO_L13N_T2_MRCC_35"/>
<pin name="IO_L10P_T1_AD15P_35"/>
<pin name="IO_L17N_T2_35"/>
<pin name="VCCINT_3" direction="pwr"/>
<pin name="GND_26" direction="pas"/>
<pin name="VCCINT_4" direction="pwr"/>
<pin name="IO_L7P_T1_AD6P_35"/>
<pin name="IO_L9P_T1_DQS_AD7P_35"/>
<pin name="IO_L14N_T2_SRCC_35"/>
<pin name="IO_L13P_T2_MRCC_35"/>
<pin name="GND_27" direction="pas"/>
<pin name="IO_L17P_T2_35"/>
<pin name="GND_28" direction="pas"/>
<pin name="VCCINT_5" direction="pwr"/>
<pin name="GNDADC_0" direction="pas"/>
<pin name="IO_L15N_T2_DQS_35"/>
<pin name="GND" direction="pas"/>
<pin name="IO_L14P_T2_SRCC_35"/>
<pin name="IO_L18N_T2_35"/>
<pin name="IO_L18P_T2_35"/>
<pin name="IO_25_35"/>
<pin name="VCCINT" direction="pwr"/>
</symbol>
<symbol name="XC7A100T-FGG484_B">
<pin name="GND_2" direction="pas"/>
<pin name="VREFN_0" direction="pwr"/>
<pin name="IO_L15P_T2_DQS_35"/>
<pin name="IO_L16N_T2_35"/>
<pin name="IO_L16P_T2_35"/>
<pin name="VCCO_35_2" direction="pwr"/>
<pin name="IO_L23N_T3_35"/>
<pin name="IO_L23P_T3_35"/>
<pin name="GND_3" direction="pas"/>
<pin name="VCCINT_2" direction="pwr"/>
<pin name="VN_0" direction="in"/>
<pin name="VCCO_35" direction="pwr"/>
<pin name="IO_L22N_T3_35"/>
<pin name="IO_L19N_T3_VREF_35"/>
<pin name="IO_L19P_T3_35"/>
<pin name="IO_L24N_T3_35"/>
<pin name="GND_4" direction="pas"/>
<pin name="VCCINT_3" direction="pwr"/>
<pin name="GND_5" direction="pas"/>
<pin name="DXN_0" direction="pas"/>
<pin name="IO_L20N_T3_35"/>
<pin name="IO_L22P_T3_35"/>
<pin name="GND_6" direction="pas"/>
<pin name="IO_L21N_T3_DQS_35"/>
<pin name="IO_L21P_T3_DQS_35"/>
<pin name="IO_L24P_T3_35"/>
<pin name="GND_7" direction="pas"/>
<pin name="VCCINT_4" direction="pwr"/>
<pin name="GND_8" direction="pas"/>
<pin name="IO_L20P_T3_35"/>
<pin name="IO_L3N_T0_DQS_34"/>
<pin name="IO_L3P_T0_DQS_34"/>
<pin name="IO_L13P_T2_MRCC_34"/>
<pin name="VCCO_34_2" direction="pwr"/>
<pin name="IO_L17P_T2_34"/>
<pin name="VCCINT_5" direction="pwr"/>
<pin name="GND_9" direction="pas"/>
<pin name="VCCINT_6" direction="pwr"/>
<pin name="IO_L1P_T0_34"/>
<pin name="VCCO_34_3" direction="pwr"/>
<pin name="IO_0_34"/>
<pin name="IO_L13N_T2_MRCC_34"/>
<pin name="IO_L14P_T2_SRCC_34"/>
<pin name="IO_L17N_T2_34"/>
<pin name="GND_10" direction="pas"/>
<pin name="VCCINT" direction="pwr"/>
<pin name="GND_11" direction="pas"/>
<pin name="IO_L1N_T0_34"/>
<pin name="IO_L2P_T0_34"/>
<pin name="IO_L6P_T0_34"/>
<pin name="GND_12" direction="pas"/>
<pin name="IO_L14N_T2_SRCC_34"/>
<pin name="IO_L16P_T2_34"/>
<pin name="IO_25_34"/>
<pin name="CFGBVS_0" direction="in"/>
<pin name="M2_0" direction="in"/>
<pin name="GND_13" direction="pas"/>
<pin name="IO_L2N_T0_34"/>
<pin name="IO_L6N_T0_VREF_34"/>
<pin name="IO_L12P_T1_MRCC_34"/>
<pin name="IO_L16N_T2_34"/>
<pin name="VCCO_34_4" direction="pwr"/>
<pin name="IO_L19P_T3_34"/>
<pin name="IO_L21N_T3_DQS_34"/>
<pin name="IO_L21P_T3_DQS_34"/>
<pin name="IO_L5P_T0_34"/>
<pin name="IO_L4P_T0_34"/>
<pin name="VCCO_34" direction="pwr"/>
<pin name="IO_L12N_T1_MRCC_34"/>
<pin name="IO_L15N_T2_DQS_34"/>
<pin name="IO_L15P_T2_DQS_34"/>
<pin name="IO_L19N_T3_VREF_34"/>
<pin name="GND_14" direction="pas"/>
<pin name="IO_L24P_T3_34"/>
<pin name="IO_L5N_T0_34"/>
<pin name="IO_L4N_T0_34"/>
<pin name="IO_L9P_T1_DQS_34"/>
<pin name="IO_L11P_T1_SRCC_34"/>
<pin name="GND_15" direction="pas"/>
<pin name="IO_L18P_T2_34"/>
<pin name="IO_L23N_T3_34"/>
<pin name="IO_L23P_T3_34"/>
<pin name="IO_L24N_T3_34"/>
<pin name="MGTPRXN2_216" direction="in"/>
<pin name="GND_16" direction="pas"/>
<pin name="GND_17" direction="pas"/>
<pin name="IO_L10P_T1_16"/>
<pin name="IO_L10N_T1_16"/>
<pin name="IO_L9P_T1_DQS_16"/>
<pin name="IO_L9N_T1_DQS_16"/>
<pin name="VCCO_16" direction="pwr"/>
<pin name="IO_L17P_T2_16"/>
<pin name="IO_L17N_T2_16"/>
<pin name="IO_L16N_T2_16"/>
<pin name="IO_L21N_T3_DQS_16"/>
<pin name="GND" direction="pas"/>
<pin name="IO_L7P_T1_34"/>
</symbol>
<symbol name="XC7A100T-FGG484_C">
<pin name="GND_2" direction="pas"/>
<pin name="IO_L9N_T1_DQS_34"/>
<pin name="IO_L11N_T1_SRCC_34"/>
<pin name="IO_L10P_T1_34"/>
<pin name="IO_L18N_T2_34"/>
<pin name="VCCO_34_2" direction="pwr"/>
<pin name="IO_L22P_T3_34"/>
<pin name="IO_L8P_T1_13"/>
<pin name="IO_L7N_T1_34"/>
<pin name="IO_L8N_T1_34"/>
<pin name="IO_L8P_T1_34"/>
<pin name="VCCO_34" direction="pwr"/>
<pin name="IO_L10N_T1_34"/>
<pin name="IO_L20N_T3_34"/>
<pin name="IO_L20P_T3_34"/>
<pin name="IO_L22N_T3_34"/>
<pin name="GND_3" direction="pas"/>
<pin name="MGTPRXP2_216" direction="in"/>
<pin name="MGTAVTT" direction="pwr"/>
<pin name="GND_4" direction="pas"/>
<pin name="IO_L8N_T1_16"/>
<pin name="VCCO_16_2" direction="pwr"/>
<pin name="IO_L7P_T1_16"/>
<pin name="IO_L7N_T1_16"/>
<pin name="IO_L11P_T1_SRCC_16"/>
<pin name="IO_L11N_T1_SRCC_16"/>
<pin name="GND_5" direction="pas"/>
<pin name="IO_L16P_T2_16"/>
<pin name="IO_L21P_T3_DQS_16"/>
<pin name="IO_L20N_T3_16"/>
<pin name="GND_6" direction="pas"/>
<pin name="MGTPRXN1_216" direction="in"/>
<pin name="GND_7" direction="pas"/>
<pin name="IO_L8P_T1_16"/>
<pin name="IO_L3P_T0_DQS_16"/>
<pin name="IO_L3N_T0_DQS_16"/>
<pin name="GND_8" direction="pas"/>
<pin name="IO_L12N_T1_MRCC_16"/>
<pin name="IO_L13P_T2_MRCC_16"/>
<pin name="IO_L13N_T2_MRCC_16"/>
<pin name="IO_L19N_T3_VREF_16"/>
<pin name="VCCO_16_3" direction="pwr"/>
<pin name="IO_L20P_T3_16"/>
<pin name="MGTAVCC" direction="pwr"/>
<pin name="MGTPRXP1_216" direction="in"/>
<pin name="GND_9" direction="pas"/>
<pin name="GND_10" direction="pas"/>
<pin name="IO_L6P_T0_16"/>
<pin name="IO_L6N_T0_VREF_16"/>
<pin name="IO_L5N_T0_16"/>
<pin name="IO_L12P_T1_MRCC_16"/>
<pin name="VCCO_16_4" direction="pwr"/>
<pin name="IO_L14N_T2_SRCC_16"/>
<pin name="IO_L19P_T3_16"/>
<pin name="IO_L23N_T3_16"/>
<pin name="IO_L22N_T3_16"/>
<pin name="MGTREFCLK1N_216" direction="in"/>
<pin name="GND_11" direction="pas"/>
<pin name="VCCBATT_0" direction="pwr"/>
<pin name="IO_L4P_T0_16"/>
<pin name="IO_L4N_T0_16"/>
<pin name="VCCO_16_5" direction="pwr"/>
<pin name="IO_L5P_T0_16"/>
<pin name="IO_L2N_T0_16"/>
<pin name="IO_L15N_T2_DQS_16"/>
<pin name="IO_L14P_T2_SRCC_16"/>
<pin name="GND_12" direction="pas"/>
<pin name="IO_L23P_T3_16"/>
<pin name="IO_L22P_T3_16"/>
<pin name="MGTREFCLK1P_216" direction="in"/>
<pin name="GND_13" direction="pas"/>
<pin name="VCCO_0" direction="pwr"/>
<pin name="IO_L1P_T0_16"/>
<pin name="IO_L1N_T0_16"/>
<pin name="IO_0_16"/>
<pin name="IO_L2P_T0_16"/>
<pin name="GND_14" direction="pas"/>
<pin name="IO_L15P_T2_DQS_16"/>
<pin name="IO_L18P_T2_16"/>
<pin name="IO_L18N_T2_16"/>
<pin name="IO_25_16"/>
<pin name="VCCO_16" direction="pwr"/>
<pin name="GND_15" direction="pas"/>
<pin name="DONE_0"/>
<pin name="GND_16" direction="pas"/>
<pin name="IO_L1N_T0_AD0N_15"/>
<pin name="GND_17" direction="pas"/>
<pin name="IO_L2P_T0_AD8P_15"/>
<pin name="IO_L2N_T0_AD8N_15"/>
<pin name="IO_L4P_T0_15"/>
<pin name="IO_L4N_T0_15"/>
<pin name="VCCO_15" direction="pwr"/>
<pin name="IO_L8N_T1_AD10N_15"/>
<pin name="IO_L24P_T3_16"/>
<pin name="IO_L24N_T3_16"/>
<pin name="VCCINT" direction="pwr"/>
<pin name="GND" direction="pas"/>
</symbol>
<symbol name="XC7A100T-FGG484_D">
<pin name="VCCAUX_2" direction="pwr"/>
<pin name="IO_L1P_T0_AD0P_15"/>
<pin name="IO_L3N_T0_DQS_AD1N_15"/>
<pin name="IO_L5N_T0_AD9N_15"/>
<pin name="VCCO_15_2" direction="pwr"/>
<pin name="IO_L6P_T0_15"/>
<pin name="IO_L6N_T0_VREF_15"/>
<pin name="IO_L12N_T1_MRCC_15"/>
<pin name="IO_L8P_T1_AD10P_15"/>
<pin name="GND_2" direction="pas"/>
<pin name="IO_L7N_T1_AD2N_15"/>
<pin name="GND_3" direction="pas"/>
<pin name="VCCBRAM_2" direction="pwr"/>
<pin name="GND_4" direction="pas"/>
<pin name="VCCO_15_3" direction="pwr"/>
<pin name="IO_L3P_T0_DQS_AD1P_15"/>
<pin name="IO_L5P_T0_AD9P_15"/>
<pin name="IO_0_15"/>
<pin name="IO_L21N_T3_DQS_A18_15"/>
<pin name="GND_5" direction="pas"/>
<pin name="IO_L12P_T1_MRCC_15"/>
<pin name="IO_L11P_T1_SRCC_15"/>
<pin name="IO_L11N_T1_SRCC_15"/>
<pin name="IO_L7P_T1_AD2P_15"/>
<pin name="VCCADC_0" direction="pwr"/>
<pin name="GND_6" direction="pas"/>
<pin name="VCCAUX_3" direction="pwr"/>
<pin name="IO_L19P_T3_A22_15"/>
<pin name="IO_L19N_T3_A21_VREF_15"/>
<pin name="GND_7" direction="pas"/>
<pin name="IO_L23N_T3_FWE_B_15"/>
<pin name="IO_L21P_T3_DQS_15"/>
<pin name="IO_L13P_T2_MRCC_15"/>
<pin name="IO_L13N_T2_MRCC_15"/>
<pin name="VCCO_15_4" direction="pwr"/>
<pin name="IO_L9P_T1_DQS_AD3P_15"/>
<pin name="IO_L9N_T1_DQS_AD3N_15"/>
<pin name="VP_0" direction="in"/>
<pin name="VCCBRAM_3" direction="pwr"/>
<pin name="CCLK_0"/>
<pin name="IO_L20N_T3_A19_15"/>
<pin name="IO_L22P_T3_A17_15"/>
<pin name="IO_L22N_T3_A16_15"/>
<pin name="IO_L23P_T3_FOE_B_15"/>
<pin name="VCCO_15_5" direction="pwr"/>
<pin name="IO_L16N_T2_A27_15"/>
<pin name="IO_L14P_T2_SRCC_15"/>
<pin name="IO_L14N_T2_SRCC_15"/>
<pin name="IO_L10N_T1_AD11N_15"/>
<pin name="GND_8" direction="pas"/>
<pin name="VREFP_0" direction="pwr"/>
<pin name="GND_9" direction="pas"/>
<pin name="VCCAUX_4" direction="pwr"/>
<pin name="IO_L20P_T3_A20_15"/>
<pin name="VCCO_14_2" direction="pwr"/>
<pin name="IO_L24P_T3_RS1_15"/>
<pin name="IO_L24N_T3_RS0_15"/>
<pin name="IO_25_15"/>
<pin name="IO_L16P_T2_A28_15"/>
<pin name="GND_10" direction="pas"/>
<pin name="IO_L18N_T2_A23_15"/>
<pin name="IO_L10P_T1_AD11P_15"/>
<pin name="IO_L15N_T2_DQS_ADV_B_15"/>
<pin name="DXP_0" direction="pas"/>
<pin name="VCCBRAM" direction="pwr"/>
<pin name="PROGRAM_B_0" direction="in"/>
<pin name="IO_L23P_T3_A03_D19_14"/>
<pin name="IO_L23N_T3_A02_D18_14"/>
<pin name="IO_25_14"/>
<pin name="GND_11" direction="pas"/>
<pin name="IO_L21P_T3_DQS_14"/>
<pin name="IO_L17P_T2_A26_15"/>
<pin name="IO_L17N_T2_A25_15"/>
<pin name="IO_L18P_T2_A24_15"/>
<pin name="VCCO_15" direction="pwr"/>
<pin name="IO_L15P_T2_DQS_15"/>
<pin name="VCCINT" direction="pwr"/>
<pin name="GND_12" direction="pas"/>
<pin name="VCCAUX_5" direction="pwr"/>
<pin name="GND_13" direction="pas"/>
<pin name="IO_L19P_T3_A10_D26_14"/>
<pin name="IO_L22P_T3_A05_D21_14"/>
<pin name="IO_L24P_T3_A01_D17_14"/>
<pin name="IO_L21N_T3_DQS_A06_D22_14"/>
<pin name="VCCO_14_3" direction="pwr"/>
<pin name="IO_L5P_T0_D06_14"/>
<pin name="IO_0_14"/>
<pin name="IO_L2P_T0_D02_14"/>
<pin name="IO_L1P_T0_D00_MOSI_14"/>
<pin name="GND_14" direction="pas"/>
<pin name="VCCAUX" direction="pwr"/>
<pin name="GND" direction="pas"/>
<pin name="TDI_0" direction="in"/>
<pin name="IO_L19N_T3_A09_D25_VREF_14"/>
<pin name="VCCO_14" direction="pwr"/>
<pin name="IO_L22N_T3_A04_D20_14"/>
<pin name="IO_L24N_T3_A00_D16_14"/>
</symbol>
<symbol name="XC7A100T-FGG484_E">
<pin name="IO_L20P_T3_A08_D24_14"/>
<pin name="IO_L5N_T0_D07_14"/>
<pin name="GND_2" direction="pas"/>
<pin name="IO_L2N_T0_D03_14"/>
<pin name="IO_L1N_T0_D01_DIN_14"/>
<pin name="VCCINT" direction="pwr"/>
<pin name="GND_3" direction="pas"/>
<pin name="VCCO_0" direction="pwr"/>
<pin name="TMS_0" direction="in"/>
<pin name="IO_L15P_T2_DQS_13"/>
<pin name="IO_L15N_T2_DQS_13"/>
<pin name="IO_L17P_T2_13"/>
<pin name="GND_4" direction="pas"/>
<pin name="IO_L20N_T3_A07_D23_14"/>
<pin name="IO_L6P_T0_FCS_B_14"/>
<pin name="IO_L6N_T0_D08_VREF_14"/>
<pin name="IO_L4P_T0_D04_14"/>
<pin name="VCCO_14_2" direction="pwr"/>
<pin name="M1_0" direction="in"/>
<pin name="M0_0" direction="in"/>
<pin name="INIT_B_0"/>
<pin name="TDO_0" direction="out"/>
<pin name="GND_5" direction="pas"/>
<pin name="IO_L14P_T2_SRCC_13"/>
<pin name="IO_L17N_T2_13"/>
<pin name="IO_L18P_T2_A12_D28_14"/>
<pin name="IO_L18N_T2_A11_D27_14"/>
<pin name="VCCO_14_3" direction="pwr"/>
<pin name="IO_L11P_T1_SRCC_14"/>
<pin name="IO_L4N_T0_D05_14"/>
<pin name="IO_L3P_T0_DQS_PUDC_B_14"/>
<pin name="IO_L10P_T1_13"/>
<pin name="GND_6" direction="pas"/>
<pin name="TCK_0" direction="in"/>
<pin name="IO_L13P_T2_MRCC_13"/>
<pin name="IO_L13N_T2_MRCC_13"/>
<pin name="IO_L14N_T2_SRCC_13"/>
<pin name="VCCO_13_2" direction="pwr"/>
<pin name="IO_L16P_T2_CSI_B_14"/>
<pin name="IO_L14P_T2_SRCC_14"/>
<pin name="IO_L14N_T2_SRCC_14"/>
<pin name="IO_L11N_T1_SRCC_14"/>
<pin name="GND_7" direction="pas"/>
<pin name="IO_L3N_T0_DQS_EMCCLK_14"/>
<pin name="IO_L10N_T1_13"/>
<pin name="IO_L12P_T1_MRCC_13"/>
<pin name="IO_L12N_T1_MRCC_13"/>
<pin name="VCCO_13_3" direction="pwr"/>
<pin name="IO_L6P_T0_13"/>
<pin name="IO_L16P_T2_13"/>
<pin name="IO_L16N_T2_13"/>
<pin name="IO_L16N_T2_A15_D31_14"/>
<pin name="GND_8" direction="pas"/>
<pin name="IO_L12P_T1_MRCC_14"/>
<pin name="IO_L12N_T1_MRCC_14"/>
<pin name="IO_L7P_T1_D09_14"/>
<pin name="IO_L7N_T1_D10_14"/>
<pin name="VCCO_13_4" direction="pwr"/>
<pin name="IO_L11P_T1_SRCC_13"/>
<pin name="IO_L11N_T1_SRCC_13"/>
<pin name="IO_L5P_T0_13"/>
<pin name="IO_L6N_T0_VREF_13"/>
<pin name="GND_9" direction="pas"/>
<pin name="IO_L1P_T0_13"/>
<pin name="IO_0_13"/>
<pin name="IO_L13P_T2_MRCC_14"/>
<pin name="IO_L13N_T2_MRCC_14"/>
<pin name="VCCO_14" direction="pwr"/>
<pin name="IO_L9P_T1_DQS_14"/>
<pin name="IO_L9N_T1_DQS_D13_14"/>
<pin name="IO_L9P_T1_DQS_13"/>
<pin name="IO_L9N_T1_DQS_13"/>
<pin name="GND_10" direction="pas"/>
<pin name="IO_L3P_T0_DQS_13"/>
<pin name="IO_L5N_T0_13"/>
<pin name="IO_L4P_T0_13"/>
<pin name="IO_L1N_T0_13"/>
<pin name="VCCO_13_5" direction="pwr"/>
<pin name="IO_L17P_T2_A14_D30_14"/>
<pin name="IO_L15P_T2_DQS_RDWR_B_14"/>
<pin name="IO_L8P_T1_D11_14"/>
<pin name="IO_L8N_T1_D12_14"/>
<pin name="GND_11" direction="pas"/>
<pin name="IO_L8N_T1_13"/>
<pin name="IO_L7P_T1_13"/>
<pin name="IO_L7N_T1_13"/>
<pin name="IO_L3N_T0_DQS_13"/>
<pin name="VCCO_13" direction="pwr"/>
<pin name="IO_L4N_T0_13"/>
<pin name="IO_L2P_T0_13"/>
<pin name="IO_L2N_T0_13"/>
<pin name="IO_L17N_T2_A13_D29_14"/>
<pin name="GND" direction="pas"/>
<pin name="IO_L15N_T2_DQS_DOUT_CSO_B_14"/>
<pin name="IO_L10P_T1_D14_14"/>
<pin name="IO_L10N_T1_D15_14"/>
</symbol>
<symbol name="ADS1115_RUG_10">
<pin name="ADDR" direction="in"/>
<pin name="ALERT/RDY" direction="out"/>
<pin name="GND" direction="pwr"/>
<pin name="AIN0" direction="in"/>
<pin name="AIN1" direction="in"/>
<pin name="AIN2" direction="in"/>
<pin name="AIN3" direction="in"/>
<pin name="VDD" direction="pwr"/>
<pin name="SDA"/>
<pin name="SCL" direction="in"/>
</symbol>
<symbol name="FT232RNQ-REEL">
<pin name="VCCIO" direction="pwr"/>
<pin name="RXD" direction="in"/>
<pin name="RI" direction="in"/>
<pin name="GND_2" direction="pas"/>
<pin name="NC_2" direction="nc"/>
<pin name="DSR" direction="in"/>
<pin name="DCD" direction="in"/>
<pin name="CTS" direction="in"/>
<pin name="CBUS4"/>
<pin name="CBUS2"/>
<pin name="CBUS3"/>
<pin name="NC_3" direction="nc"/>
<pin name="NC_4" direction="nc"/>
<pin name="USBDP"/>
<pin name="USBDM"/>
<pin name="3V3OUT" direction="out"/>
<pin name="GND_3" direction="pas"/>
<pin name="RESET" direction="in"/>
<pin name="VCC" direction="pwr"/>
<pin name="GND" direction="pas"/>
<pin name="CBUS1"/>
<pin name="CBUS0"/>
<pin name="NC_5" direction="nc"/>
<pin name="AGND" direction="pas"/>
<pin name="NC_6" direction="nc"/>
<pin name="TEST" direction="in"/>
<pin name="OSCI" direction="in"/>
<pin name="OSCO" direction="out"/>
<pin name="NC" direction="nc"/>
<pin name="TXD" direction="out"/>
<pin name="DTR" direction="out"/>
<pin name="RTS" direction="out"/>
<pin name="EPAD" direction="pas"/>
</symbol>
<symbol name="LSM9DS1TR">
<pin name="VDDIO_2" direction="pwr"/>
<pin name="SCL/SPC"/>
<pin name="VDDIO" direction="pwr"/>
<pin name="SDA/SDI/SDO"/>
<pin name="SDO_A/G" direction="out"/>
<pin name="SDO_M" direction="out"/>
<pin name="CS_A/G"/>
<pin name="CS_M"/>
<pin name="DRDY_M"/>
<pin name="INT_M"/>
<pin name="INT1_A/G"/>
<pin name="INT2_A/G"/>
<pin name="DEN_A/G"/>
<pin name="RES_2" direction="pas"/>
<pin name="RES_3" direction="pas"/>
<pin name="RES_4" direction="pas"/>
<pin name="RES_5" direction="pas"/>
<pin name="RES" direction="pas"/>
<pin name="GND_2" direction="pwr"/>
<pin name="GND" direction="pwr"/>
<pin name="CAP" direction="pas"/>
<pin name="VDD_2" direction="pwr"/>
<pin name="VDD" direction="pwr"/>
<pin name="C1"/>
</symbol>
<symbol name="NEO-M8">
<pin name="SAFEBOOT_N" direction="in"/>
<pin name="D_SEL" direction="in"/>
<pin name="TIMEPULSE"/>
<pin name="EXTINT" direction="in"/>
<pin name="USB_DM"/>
<pin name="USB_DP"/>
<pin name="VDD_USB" direction="pwr"/>
<pin name="RESET_N" direction="in"/>
<pin name="VCC_RF" direction="pwr"/>
<pin name="GND_2" direction="pas"/>
<pin name="RF_IN" direction="in"/>
<pin name="GND_3" direction="pas"/>
<pin name="GND_4" direction="pas"/>
<pin name="LNA_EN" direction="out"/>
<pin name="RESERVED_2" direction="nc"/>
<pin name="RESERVED_3" direction="nc"/>
<pin name="RESERVED" direction="nc"/>
<pin name="SDA/SPI_CS_N"/>
<pin name="SCL/SPI_CLK"/>
<pin name="TXD/SPI_MISO" direction="out"/>
<pin name="RXD/SPI_MOSI" direction="in"/>
<pin name="V_BCKP" direction="pwr"/>
<pin name="VCC" direction="pwr"/>
<pin name="GND" direction="pas"/>
</symbol>
<symbol name="BMP388">
<pin name="VDDIO" direction="pwr"/>
<pin name="SCK" direction="pas"/>
<pin name="VSS_2" direction="pas"/>
<pin name="SDI" direction="pas"/>
<pin name="SDO" direction="pas"/>
<pin name="CSB" direction="pas"/>
<pin name="INT" direction="pas"/>
<pin name="VSS_3" direction="pas"/>
<pin name="VSS" direction="pas"/>
<pin name="VDD" direction="pwr"/>
</symbol>
<symbol name="STM32F746ZGT7_A">
<pin name="PA0"/>
<pin name="PA1"/>
<pin name="PA2"/>
<pin name="PA3"/>
<pin name="PA4"/>
<pin name="PA5"/>
<pin name="PA6"/>
<pin name="PA7"/>
<pin name="PA8"/>
<pin name="PA9"/>
<pin name="PA10"/>
<pin name="PA11"/>
<pin name="PA12"/>
<pin name="PA13"/>
<pin name="PA14"/>
<pin name="PA15"/>
<pin name="PB0"/>
<pin name="PB1"/>
<pin name="PB2"/>
<pin name="PB3"/>
<pin name="PB4"/>
<pin name="PB5"/>
<pin name="PB6"/>
<pin name="PB7"/>
<pin name="PB8"/>
<pin name="PB9"/>
<pin name="PB10"/>
<pin name="PB11"/>
<pin name="PB12"/>
<pin name="PB13"/>
<pin name="PB14"/>
<pin name="PB15"/>
<pin name="PC0"/>
<pin name="PC1"/>
<pin name="PC2"/>
<pin name="PC3"/>
<pin name="PC4"/>
<pin name="PC5"/>
<pin name="PC6"/>
<pin name="PC7"/>
<pin name="PC8"/>
<pin name="PC9"/>
<pin name="PC10"/>
<pin name="PC11"/>
<pin name="PC12"/>
<pin name="PC13"/>
<pin name="PC14"/>
<pin name="PC15"/>
<pin name="PD0"/>
<pin name="PD1"/>
<pin name="PD2"/>
<pin name="PD3"/>
<pin name="PD4"/>
<pin name="PD5"/>
<pin name="PD6"/>
<pin name="PD7"/>
<pin name="PD8"/>
<pin name="PD9"/>
<pin name="PD10"/>
<pin name="PD11"/>
<pin name="PD12"/>
<pin name="PD13"/>
<pin name="PD14"/>
<pin name="PD15"/>
</symbol>
<symbol name="STM32F746ZGT7_B">
<pin name="PE0"/>
<pin name="PE1"/>
<pin name="PE2"/>
<pin name="PE3"/>
<pin name="PE4"/>
<pin name="PE5"/>
<pin name="PE6"/>
<pin name="PE7"/>
<pin name="PE8"/>
<pin name="PE9"/>
<pin name="PE10"/>
<pin name="PE11"/>
<pin name="PE12"/>
<pin name="PE13"/>
<pin name="PE14"/>
<pin name="PE15"/>
<pin name="PF0"/>
<pin name="PF1"/>
<pin name="PF2"/>
<pin name="PF3"/>
<pin name="PF4"/>
<pin name="PF5"/>
<pin name="PF6"/>
<pin name="PF7"/>
<pin name="PF8"/>
<pin name="PF9"/>
<pin name="PF10"/>
<pin name="PF11"/>
<pin name="PF12"/>
<pin name="PF13"/>
<pin name="PF14"/>
<pin name="PF15"/>
<pin name="PG0"/>
<pin name="PG1"/>
<pin name="PG2"/>
<pin name="PG3"/>
<pin name="PG4"/>
<pin name="PG5"/>
<pin name="PG6"/>
<pin name="PG7"/>
<pin name="PG8"/>
<pin name="PG9"/>
<pin name="PG10"/>
<pin name="PG11"/>
<pin name="PG12"/>
<pin name="PG13"/>
<pin name="PG14"/>
<pin name="PG15"/>
<pin name="PH0"/>
<pin name="PH1"/>
<pin name="NRST"/>
<pin name="BOOT0" direction="in"/>
<pin name="PDR_ON"/>
</symbol>
<symbol name="STM32F746ZGT7_C">
<pin name="VSS_2" direction="pwr"/>
<pin name="VSS_3" direction="pwr"/>
<pin name="VSS_4" direction="pwr"/>
<pin name="VSS_5" direction="pwr"/>
<pin name="VSS_6" direction="pwr"/>
<pin name="VSS_7" direction="pwr"/>
<pin name="VSS_8" direction="pwr"/>
<pin name="VSS_9" direction="pwr"/>
<pin name="VSS" direction="pwr"/>
<pin name="VSSA" direction="pwr"/>
<pin name="VBAT" direction="pwr"/>
<pin name="VCAP_1" direction="pwr"/>
<pin name="VCAP_2" direction="pwr"/>
<pin name="VDD_2" direction="pwr"/>
<pin name="VDD_3" direction="pwr"/>
<pin name="VDD_4" direction="pwr"/>
<pin name="VDD_5" direction="pwr"/>
<pin name="VDD_6" direction="pwr"/>
<pin name="VDD_7" direction="pwr"/>
<pin name="VDD_8" direction="pwr"/>
<pin name="VDD_9" direction="pwr"/>
<pin name="VDD_10" direction="pwr"/>
<pin name="VDD_11" direction="pwr"/>
<pin name="VDD" direction="pwr"/>
<pin name="VDDA" direction="pwr"/>
<pin name="VREF+" direction="pwr"/>
<pin name="VDDUSB" direction="pwr"/>
</symbol>
<symbol name="MT25QL01GBBB1EW9-0SIT">
<pin name="S" direction="in"/>
<pin name="DQ1"/>
<pin name="W/DQ2"/>
<pin name="VSS_2" direction="pas"/>
<pin name="DQ0"/>
<pin name="C" direction="in"/>
<pin name="DQ3/HOLD"/>
<pin name="VCC" direction="pwr"/>
<pin name="VSS" direction="pas"/>
</symbol>
<symbol name="TCM2-63WX+">
<pin name="PRIMARY/GND_2" direction="pas"/>
<pin name="PRIMARY/GND" direction="pas"/>
<pin name="PRIMARY_DOT" direction="pas"/>
<pin name="SECONDARY" direction="pas"/>
<pin name="NC" direction="pas"/>
<pin name="SECONDARY_DOT" direction="pas"/>
</symbol>
<symbol name="ADP1755ACPZ-R7">
<pin name="VIN_2" direction="pwr"/>
<pin name="VIN_3" direction="pwr"/>
<pin name="VIN_4" direction="pwr"/>
<pin name="EN" direction="in"/>
<pin name="PG" direction="out"/>
<pin name="GND" direction="pas"/>
<pin name="SS" direction="pas"/>
<pin name="NC" direction="nc"/>
<pin name="ADJ" direction="pas"/>
<pin name="VOUT_2" direction="pwr"/>
<pin name="VOUT_3" direction="pwr"/>
<pin name="VOUT_4" direction="pwr"/>
<pin name="VOUT_5" direction="pwr"/>
<pin name="VOUT" direction="pwr"/>
<pin name="VIN_5" direction="pwr"/>
<pin name="VIN" direction="pwr"/>
<pin name="EPAD" direction="pas"/>
</symbol>
<symbol name="ADP2164ACPZ-R7">
<pin name="VIN" direction="pas"/>
<pin name="PVIN_2" direction="pas"/>
<pin name="PVIN" direction="pas"/>
<pin name="PGOOD" direction="pas"/>
<pin name="EN" direction="pas"/>
<pin name="FB" direction="pas"/>
<pin name="RT" direction="pas"/>
<pin name="TRK" direction="pas"/>
<pin name="SW_2" direction="pas"/>
<pin name="SW_3" direction="pas"/>
<pin name="SW" direction="pas"/>
<pin name="SYNC" direction="pas"/>
<pin name="GND" direction="pas"/>
<pin name="PGND_2" direction="pas"/>
<pin name="PGND_3" direction="pas"/>
<pin name="PGND" direction="pas"/>
<pin name="EP" direction="pas"/>
</symbol>
<symbol name="MAX20029ATIA/V+">
<pin name="EN1" direction="in"/>
<pin name="PV1" direction="in"/>
<pin name="LX1" direction="pas"/>
<pin name="PGND1" direction="pwr"/>
<pin name="PGND2" direction="pwr"/>
<pin name="LX2" direction="pas"/>
<pin name="PV2" direction="in"/>
<pin name="OUTS2" direction="in"/>
<pin name="EN2" direction="in"/>
<pin name="PG2" direction="out"/>
<pin name="GND_2" direction="pwr"/>
<pin name="PG3" direction="out"/>
<pin name="EN3" direction="in"/>
<pin name="OUTS3" direction="in"/>
<pin name="PV3" direction="in"/>
<pin name="LX3" direction="pas"/>
<pin name="PGND3" direction="pwr"/>
<pin name="PGND4" direction="pwr"/>
<pin name="LX4" direction="pas"/>
<pin name="PV4" direction="in"/>
<pin name="EN4" direction="in"/>
<pin name="OUTS4" direction="in"/>
<pin name="PG4" direction="out"/>
<pin name="GND" direction="pwr"/>
<pin name="SYNC" direction="in"/>
<pin name="VA" direction="pas"/>
<pin name="PG1" direction="out"/>
<pin name="OUTS1" direction="in"/>
<pin name="EPAD" direction="in"/>
</symbol>
<symbol name="CYUSB3014-BZXI_A">
<pin name="U3VSSQ" direction="pwr"/>
<pin name="U3RXVDDQ" direction="pwr"/>
<pin name="SSRXM" direction="in"/>
<pin name="SSRXP" direction="in"/>
<pin name="AVDD" direction="pwr"/>
<pin name="VSS_2" direction="pwr"/>
<pin name="DP" direction="pas"/>
<pin name="VIO4" direction="pas"/>
<pin name="FSLC[0]" direction="in"/>
<pin name="R_USB3" direction="pas"/>
<pin name="FSLC[1]" direction="in"/>
<pin name="U3TXVDDQ" direction="pwr"/>
<pin name="CVDDQ" direction="pwr"/>
<pin name="AVSS" direction="pwr"/>
<pin name="VSS_3" direction="pwr"/>
<pin name="VSS_4" direction="pwr"/>
<pin name="GPIO[54]" direction="pas"/>
<pin name="GPIO[55]" direction="pas"/>
<pin name="VDD_2" direction="pwr"/>
<pin name="GPIO[57]" direction="pas"/>
<pin name="!RESET" direction="in"/>
<pin name="XTALIN" direction="in"/>
<pin name="R_USB2" direction="pas"/>
<pin name="OTG_ID" direction="in"/>
<pin name="GPIO[50]" direction="pas"/>
<pin name="GPIO[51]" direction="pas"/>
<pin name="GPIO[52]" direction="pas"/>
<pin name="CLKIN_32_2" direction="in"/>
<pin name="CLKIN_32" direction="in"/>
<pin name="FSLC[2]" direction="in"/>
<pin name="TDI" direction="in"/>
<pin name="TMS" direction="in"/>
<pin name="TCK" direction="in"/>
<pin name="SSTXP" direction="out"/>
<pin name="SSTXM" direction="out"/>
<pin name="XTALOUT" direction="out"/>
<pin name="GPIO[53]" direction="pas"/>
<pin name="GPIO[56]" direction="pas"/>
<pin name="VSS_5" direction="pwr"/>
<pin name="I2C_GPIO[58]" direction="pas"/>
<pin name="GPIO[47]" direction="pas"/>
<pin name="VSS_6" direction="pwr"/>
<pin name="VIO3" direction="pas"/>
<pin name="GPIO[49]" direction="pas"/>
<pin name="GPIO[48]" direction="pas"/>
<pin name="VDD" direction="pwr"/>
<pin name="VIO2" direction="pas"/>
<pin name="GPIO[45]" direction="pas"/>
<pin name="GPIO[44]" direction="pas"/>
<pin name="GPIO[41]" direction="pas"/>
<pin name="GPIO[46]" direction="pas"/>
<pin name="GPIO[2]" direction="pas"/>
<pin name="GPIO[5]" direction="pas"/>
<pin name="GPIO[1]" direction="pas"/>
<pin name="VSS" direction="pwr"/>
<pin name="GPIO[42]" direction="pas"/>
<pin name="GPIO[43]" direction="pas"/>
<pin name="GPIO[30]" direction="pas"/>
<pin name="GPIO[25]" direction="pas"/>
<pin name="GPIO[22]" direction="pas"/>
<pin name="GPIO[21]" direction="pas"/>
</symbol>
<symbol name="CYUSB3014-BZXI_B">
<pin name="GPIO[15]" direction="pas"/>
<pin name="GPIO[4]" direction="pas"/>
<pin name="VDD_2" direction="pwr"/>
<pin name="GPIO[39]" direction="pas"/>
<pin name="GPIO[40]" direction="pas"/>
<pin name="GPIO[31]" direction="pas"/>
<pin name="GPIO[29]" direction="pas"/>
<pin name="GPIO[26]" direction="pas"/>
<pin name="GPIO[20]" direction="pas"/>
<pin name="GPIO[24]" direction="pas"/>
<pin name="GPIO[7]" direction="pas"/>
<pin name="GPIO[38]" direction="pas"/>
<pin name="GPIO[36]" direction="pas"/>
<pin name="GPIO[37]" direction="pas"/>
<pin name="GPIO[34]" direction="pas"/>
<pin name="GPIO[28]" direction="pas"/>
<pin name="GPIO[16]" direction="pas"/>
<pin name="GPIO[19]" direction="pas"/>
<pin name="GPIO[14]" direction="pas"/>
<pin name="GPIO[9]" direction="pas"/>
<pin name="GPIO[35]" direction="pas"/>
<pin name="GPIO[33]" direction="pas"/>
<pin name="VSS_2" direction="pwr"/>
<pin name="VSS_3" direction="pwr"/>
<pin name="GPIO[27]" direction="pas"/>
<pin name="GPIO[23]" direction="pas"/>
<pin name="GPIO[18]" direction="pas"/>
<pin name="GPIO[17]" direction="pas"/>
<pin name="GPIO[13]" direction="pas"/>
<pin name="VSS_4" direction="pwr"/>
<pin name="!TRST" direction="in"/>
<pin name="VSS_5" direction="pwr"/>
<pin name="VSS_6" direction="pwr"/>
<pin name="GPIO[32]" direction="pas"/>
<pin name="VDD_3" direction="pwr"/>
<pin name="VSS_7" direction="pwr"/>
<pin name="VDD_4" direction="pwr"/>
<pin name="!INT" direction="pas"/>
<pin name="VIO1_2" direction="pas"/>
<pin name="DM" direction="pas"/>
<pin name="NC" direction="nc"/>
<pin name="VDD_5" direction="pwr"/>
<pin name="TDO" direction="out"/>
<pin name="VIO5" direction="pas"/>
<pin name="I2C_GPIO[59]" direction="pas"/>
<pin name="O[60]" direction="out"/>
<pin name="VBATT" direction="pwr"/>
<pin name="VBUS" direction="pwr"/>
<pin name="GPIO[0]" direction="pas"/>
<pin name="VDD_6" direction="pwr"/>
<pin name="GPIO[3]" direction="pas"/>
<pin name="VSS_8" direction="pwr"/>
<pin name="GPIO[6]" direction="pas"/>
<pin name="VIO1" direction="pas"/>
<pin name="GPIO[8]" direction="pas"/>
<pin name="VDD" direction="pwr"/>
<pin name="GPIO[12]" direction="pas"/>
<pin name="GPIO[10]" direction="pas"/>
<pin name="GPIO[11]" direction="pas"/>
<pin name="VSS" direction="pwr"/>
</symbol>
<symbol name="LUSB359300">
<pin name="VBUS" direction="pwr"/>
<pin name="D-"/>
<pin name="D+"/>
<pin name="GND" direction="pas"/>
<pin name="STDA_SSRX-" direction="in"/>
<pin name="STDA_SSRX+" direction="in"/>
<pin name="GND_DRAIN" direction="pas"/>
<pin name="STDAA_SSTX-" direction="out"/>
<pin name="STDAA_SSTX+" direction="out"/>
</symbol>
<symbol name="AT25XE041B-MHNHR-T">
<pin name="!CS" direction="in"/>
<pin name="SO"/>
<pin name="!WP" direction="in"/>
<pin name="GND_2" direction="pas"/>
<pin name="SI"/>
<pin name="SCK" direction="in"/>
<pin name="!HOLD" direction="in"/>
<pin name="VCC" direction="pwr"/>
<pin name="GND" direction="pas"/>
</symbol>
<symbol name="XTAL4_CX3225SB">
<pin name="HOT_2" direction="pas"/>
<pin name="GND_2" direction="pas"/>
<pin name="HOT" direction="pas"/>
<pin name="GND" direction="pas"/>
</symbol>
<symbol name="CRYSTALH">
<pin name="1" direction="pas"/>
<pin name="2" direction="pas"/>
</symbol>
<symbol name="CRYSTALV">
<pin name="2" direction="pas"/>
<pin name="1" direction="pas"/>
</symbol>
<symbol name="XTAL_1-3_2-4GND">
<pin name="1" direction="pas"/>
<pin name="2" direction="pas"/>
<pin name="3" direction="pas"/>
<pin name="4" direction="pas"/>
</symbol>
<symbol name="ADS1115LIDGSR">
<pin name="ADDR" direction="in"/>
<pin name="ALERT/RDY" direction="out"/>
<pin name="GND" direction="pas"/>
<pin name="AIN0" direction="in"/>
<pin name="AIN1" direction="in"/>
<pin name="AIN2" direction="in"/>
<pin name="AIN3" direction="in"/>
<pin name="VDD" direction="pwr"/>
<pin name="SDA"/>
<pin name="SCL" direction="in"/>
</symbol>
<symbol name="MT25QL01GBBB8E12-0AUT">
<pin name="NC" direction="nc"/>
<pin name="RFU_2" direction="nc"/>
<pin name="RESET" direction="in"/>
<pin name="RFU_3" direction="nc"/>
<pin name="RFU_4" direction="nc"/>
<pin name="C" direction="in"/>
<pin name="VSS" direction="pas"/>
<pin name="VCC" direction="pwr"/>
<pin name="RFU_5" direction="nc"/>
<pin name="RFU_6" direction="nc"/>
<pin name="S" direction="in"/>
<pin name="RFU_7" direction="nc"/>
<pin name="W/DQ2"/>
<pin name="RFU_8" direction="nc"/>
<pin name="RFU_9" direction="nc"/>
<pin name="DQ1"/>
<pin name="DQ0"/>
<pin name="DQ3/HOLD"/>
<pin name="RFU_10" direction="nc"/>
<pin name="RFU_11" direction="nc"/>
<pin name="RFU_12" direction="nc"/>
<pin name="RFU_13" direction="nc"/>
<pin name="RFU_14" direction="nc"/>
<pin name="RFU" direction="nc"/>
</symbol>
<symbol name="CONN_COAX_3GND_1">
<pin name="SIGNAL" direction="pas"/>
<pin name="GND_2" direction="pas"/>
<pin name="GND_3" direction="pas"/>
<pin name="GND" direction="pas"/>
</symbol>
<symbol name="CONN_COAX_3GND_2">
<pin name="SIGNAL" direction="pas"/>
<pin name="GND_2" direction="pas"/>
<pin name="GND_3" direction="pas"/>
<pin name="GND" direction="pas"/>
</symbol>
<symbol name="CONN_COAX_3GND_3">
<pin name="SIGNAL" direction="pas"/>
<pin name="GND_2" direction="pas"/>
<pin name="GND_3" direction="pas"/>
<pin name="GND" direction="pas"/>
</symbol>
<symbol name="CONN_483910003">
<pin name="VBUS" direction="pas"/>
<pin name="D-" direction="pas"/>
<pin name="D+" direction="pas"/>
<pin name="GND" direction="pas"/>
<pin name="STDA_SSRX-" direction="pas"/>
<pin name="STDA_SSRX+" direction="pas"/>
<pin name="GND_DRAIN" direction="pas"/>
<pin name="STDA_SSTX-" direction="pas"/>
<pin name="STDA_SSTX+" direction="pas"/>
</symbol>
<symbol name="CONN_483910003_2">
<pin name="VBUS" direction="pas"/>
<pin name="D-" direction="pas"/>
<pin name="D+" direction="pas"/>
<pin name="GND" direction="pas"/>
<pin name="STDA_SSRX-" direction="pas"/>
<pin name="STDA_SSRX+" direction="pas"/>
<pin name="GND_DRAIN" direction="pas"/>
<pin name="STDA_SSTX-" direction="pas"/>
<pin name="STDA_SSTX+" direction="pas"/>
</symbol>
<symbol name="CONN_483910003_3">
<pin name="VBUS" direction="pas"/>
<pin name="D-" direction="pas"/>
<pin name="D+" direction="pas"/>
<pin name="GND" direction="pas"/>
<pin name="STDA_SSRX-" direction="pas"/>
<pin name="STDA_SSRX+" direction="pas"/>
<pin name="GND_DRAIN" direction="pas"/>
<pin name="STDA_SSTX-" direction="pas"/>
<pin name="STDA_SSTX+" direction="pas"/>
</symbol>
<symbol name="484050003">
<pin name="VBUS" direction="pwr"/>
<pin name="D-"/>
<pin name="D+"/>
<pin name="GND" direction="pas"/>
<pin name="STDA_SSRX-" direction="pas"/>
<pin name="STDA_SSRX+" direction="pas"/>
<pin name="GND_DRAIN" direction="pas"/>
<pin name="STDA_SSTX-" direction="pas"/>
<pin name="STDA_SSTX+" direction="pas"/>
</symbol>
<symbol name="AD9203ARUZ">
<pin name="DRVSS" direction="pas"/>
<pin name="DRVDD" direction="pwr"/>
<pin name="D0" direction="pas"/>
<pin name="D1" direction="pas"/>
<pin name="D2" direction="pas"/>
<pin name="D3" direction="pas"/>
<pin name="D4" direction="pas"/>
<pin name="D5" direction="pas"/>
<pin name="D6" direction="pas"/>
<pin name="D7" direction="pas"/>
<pin name="D8" direction="pas"/>
<pin name="D9" direction="pas"/>
<pin name="OTR" direction="pas"/>
<pin name="DFS" direction="pas"/>
<pin name="CLK" direction="pas"/>
<pin name="3-STATE" direction="pas"/>
<pin name="STBY" direction="pas"/>
<pin name="REFSENSE" direction="pas"/>
<pin name="CLAMP" direction="pas"/>
<pin name="CLAMPIN" direction="pas"/>
<pin name="PWRCON" direction="pas"/>
<pin name="REFTF" direction="pas"/>
<pin name="VREF" direction="pas"/>
<pin name="REFBF" direction="pas"/>
<pin name="AINP" direction="pas"/>
<pin name="AINN" direction="pas"/>
<pin name="AVSS" direction="pas"/>
<pin name="AVDD" direction="pwr"/>
</symbol>
<symbol name="AD8028ARM-REEL7">
<pin name="VOUTA" direction="pas"/>
<pin name="-INA" direction="pas"/>
<pin name="+INA" direction="pas"/>
<pin name="-VS" direction="pwr"/>
<pin name="DISABLE!/SELECTA" direction="pas"/>
<pin name="DISABLE!/SELECTB" direction="pas"/>
<pin name="+INB" direction="pas"/>
<pin name="-INB" direction="pas"/>
<pin name="VOUTB" direction="pas"/>
<pin name="+VS" direction="pwr"/>
</symbol>
<symbol name="LM2662M">
<pin name="FC" direction="pas"/>
<pin name="C1+" direction="pas"/>
<pin name="GND" direction="pas"/>
<pin name="C1-" direction="pas"/>
<pin name="OUT" direction="out"/>
<pin name="LV" direction="pas"/>
<pin name="OSC" direction="pas"/>
<pin name="V+" direction="in"/>
</symbol>
<symbol name="MAX2829ETN+">
<pin name="B6" direction="in"/>
<pin name="VCC_2" direction="pwr"/>
<pin name="B7" direction="in"/>
<pin name="RXRFL" direction="in"/>
<pin name="GND_2" direction="pwr"/>
<pin name="RXRFH" direction="in"/>
<pin name="GND_3" direction="pwr"/>
<pin name="TXRFH+" direction="out"/>
<pin name="TXRFH-" direction="out"/>
<pin name="VCC_3" direction="pwr"/>
<pin name="TXRFL+" direction="out"/>
<pin name="TXRFL-" direction="out"/>
<pin name="TXENA" direction="in"/>
<pin name="PABIAS" direction="out"/>
<pin name="VCC_4" direction="pwr"/>
<pin name="TXBBI+" direction="in"/>
<pin name="TXBBI-" direction="in"/>
<pin name="TXBBQ+" direction="in"/>
<pin name="TXBBQ-" direction="in"/>
<pin name="VCC_5" direction="pwr"/>
<pin name="RBIAS" direction="in"/>
<pin name="VCC_6" direction="pwr"/>
<pin name="VREF" direction="out"/>
<pin name="GND_4" direction="pwr"/>
<pin name="VCC_7" direction="pwr"/>
<pin name="DIN" direction="in"/>
<pin name="SCLK" direction="in"/>
<pin name="!CS" direction="in"/>
<pin name="LD" direction="out"/>
<pin name="ROSC" direction="in"/>
<pin name="VCC_8" direction="pwr"/>
<pin name="GND_5" direction="pwr"/>
<pin name="CPOUT" direction="out"/>
<pin name="GND_6" direction="pwr"/>
<pin name="GND_7" direction="pwr"/>
<pin name="TUNE" direction="in"/>
<pin name="BYPASS" direction="pas"/>
<pin name="VCC_9" direction="pwr"/>
<pin name="!SHDN" direction="in"/>
<pin name="RSSI" direction="out"/>
<pin name="RXENA" direction="in"/>
<pin name="RXHP" direction="in"/>
<pin name="RXBBQ-" direction="out"/>
<pin name="RXBBQ+" direction="out"/>
<pin name="RXBBI-" direction="out"/>
<pin name="RXBBI+" direction="out"/>
<pin name="VCC_10" direction="pwr"/>
<pin name="B1" direction="in"/>
<pin name="VCC_11" direction="pwr"/>
<pin name="B2" direction="in"/>
<pin name="GND" direction="pwr"/>
<pin name="VCC_12" direction="pwr"/>
<pin name="B3" direction="in"/>
<pin name="B4" direction="in"/>
<pin name="VCC" direction="pwr"/>
<pin name="B5" direction="in"/>
<pin name="EPAD" direction="pas"/>
</symbol>
<symbol name="QPA9501SR">
<pin name="NC_2" direction="nc"/>
<pin name="GND_2" direction="pas"/>
<pin name="RF_IN" direction="in"/>
<pin name="GND_3" direction="pas"/>
<pin name="PA_EN" direction="pas"/>
<pin name="NC_3" direction="nc"/>
<pin name="DET_ALT" direction="out"/>
<pin name="NC" direction="nc"/>
<pin name="VCC3_2" direction="pwr"/>
<pin name="DET" direction="out"/>
<pin name="GND_4" direction="pas"/>
<pin name="GND_5" direction="pas"/>
<pin name="RF_OUT" direction="out"/>
<pin name="GND_6" direction="pas"/>
<pin name="GND_7" direction="pas"/>
<pin name="GND_8" direction="pas"/>
<pin name="GND" direction="pas"/>
<pin name="VCC3" direction="pwr"/>
<pin name="VCC2" direction="pwr"/>
<pin name="VCC1" direction="pwr"/>
<pin name="RF/DCGND" direction="pas"/>
</symbol>
<symbol name="MMZ25332BT1">
<pin name="N.C" direction="pas"/>
<pin name="RFIN_2" direction="in"/>
<pin name="RFIN" direction="in"/>
<pin name="VBA1"/>
<pin name="VBA2"/>
<pin name="VBIAS"/>
<pin name="VCC2/RFOUT_2"/>
<pin name="VCC2/RFOUT_3"/>
<pin name="VCC2/RFOUT"/>
<pin name="PDET"/>
<pin name="VCC1_2" direction="pwr"/>
<pin name="VCC1" direction="pwr"/>
<pin name="HTAB" direction="pas"/>
</symbol>
<symbol name="CONN_030P_000C_1">
<pin name="1" direction="pas"/>
<pin name="2" direction="pas"/>
<pin name="3" direction="pas"/>
<pin name="4" direction="pas"/>
<pin name="5" direction="pas"/>
<pin name="6" direction="pas"/>
<pin name="7" direction="pas"/>
<pin name="8" direction="pas"/>
<pin name="9" direction="pas"/>
<pin name="10" direction="pas"/>
<pin name="11" direction="pas"/>
<pin name="12" direction="pas"/>
<pin name="13" direction="pas"/>
<pin name="14" direction="pas"/>
<pin name="15" direction="pas"/>
<pin name="16" direction="pas"/>
<pin name="17" direction="pas"/>
<pin name="18" direction="pas"/>
<pin name="19" direction="pas"/>
<pin name="20" direction="pas"/>
<pin name="21" direction="pas"/>
<pin name="22" direction="pas"/>
<pin name="23" direction="pas"/>
<pin name="24" direction="pas"/>
<pin name="25" direction="pas"/>
<pin name="26" direction="pas"/>
<pin name="27" direction="pas"/>
<pin name="28" direction="pas"/>
<pin name="29" direction="pas"/>
<pin name="30" direction="pas"/>
</symbol>
<symbol name="CONN_030P_000C_2">
<pin name="1" direction="pas"/>
<pin name="2" direction="pas"/>
<pin name="3" direction="pas"/>
<pin name="4" direction="pas"/>
<pin name="5" direction="pas"/>
<pin name="6" direction="pas"/>
<pin name="7" direction="pas"/>
<pin name="8" direction="pas"/>
<pin name="9" direction="pas"/>
<pin name="10" direction="pas"/>
<pin name="11" direction="pas"/>
<pin name="12" direction="pas"/>
<pin name="13" direction="pas"/>
<pin name="14" direction="pas"/>
<pin name="15" direction="pas"/>
<pin name="16" direction="pas"/>
<pin name="17" direction="pas"/>
<pin name="18" direction="pas"/>
<pin name="19" direction="pas"/>
<pin name="20" direction="pas"/>
<pin name="21" direction="pas"/>
<pin name="22" direction="pas"/>
<pin name="23" direction="pas"/>
<pin name="24" direction="pas"/>
<pin name="25" direction="pas"/>
<pin name="26" direction="pas"/>
<pin name="27" direction="pas"/>
<pin name="28" direction="pas"/>
<pin name="29" direction="pas"/>
<pin name="30" direction="pas"/>
</symbol>
<symbol name="CONN_030P_000C_3">
<pin name="1" direction="pas"/>
<pin name="2" direction="pas"/>
<pin name="3" direction="pas"/>
<pin name="4" direction="pas"/>
<pin name="5" direction="pas"/>
<pin name="6" direction="pas"/>
<pin name="7" direction="pas"/>
<pin name="8" direction="pas"/>
<pin name="9" direction="pas"/>
<pin name="10" direction="pas"/>
<pin name="11" direction="pas"/>
<pin name="12" direction="pas"/>
<pin name="13" direction="pas"/>
<pin name="14" direction="pas"/>
<pin name="15" direction="pas"/>
<pin name="16" direction="pas"/>
<pin name="17" direction="pas"/>
<pin name="18" direction="pas"/>
<pin name="19" direction="pas"/>
<pin name="20" direction="pas"/>
<pin name="21" direction="pas"/>
<pin name="22" direction="pas"/>
<pin name="23" direction="pas"/>
<pin name="24" direction="pas"/>
<pin name="25" direction="pas"/>
<pin name="26" direction="pas"/>
<pin name="27" direction="pas"/>
<pin name="28" direction="pas"/>
<pin name="29" direction="pas"/>
<pin name="30" direction="pas"/>
</symbol>
<symbol name="LM1084IS-3.3">
<pin name="ADJ/GND" direction="pas"/>
<pin name="VOUT" direction="out"/>
<pin name="VIN" direction="in"/>
<pin name="4" direction="pas"/>
</symbol>
<symbol name="TRANS_N-LDMOS_1D_2G_3S">
<pin name="D" direction="pas"/>
<pin name="S" direction="pas"/>
<pin name="G" direction="pas"/>
</symbol>
<symbol name="TRANS_N-MOSFET_1G_2D_3S">
<pin name="D" direction="pas"/>
<pin name="S" direction="pas"/>
<pin name="G" direction="pas"/>
</symbol>
<symbol name="CONN_005P_000C_1">
<pin name="1" direction="pas"/>
<pin name="2" direction="pas"/>
<pin name="3" direction="pas"/>
<pin name="4" direction="pas"/>
<pin name="5" direction="pas"/>
</symbol>
<symbol name="CONN_005P_000C_2">
<pin name="1" direction="pas"/>
<pin name="2" direction="pas"/>
<pin name="3" direction="pas"/>
<pin name="4" direction="pas"/>
<pin name="5" direction="pas"/>
</symbol>
<symbol name="CONN_005P_000C_3">
<pin name="1" direction="pas"/>
<pin name="2" direction="pas"/>
<pin name="3" direction="pas"/>
<pin name="4" direction="pas"/>
<pin name="5" direction="pas"/>
</symbol>
<symbol name="ADT1-1+">
<pin name="1" direction="pas"/>
<pin name="2" direction="pas"/>
<pin name="3" direction="pas"/>
<pin name="4" direction="pas"/>
<pin name="5" direction="pas"/>
<pin name="6" direction="pas"/>
</symbol>
<symbol name="TPS61088RHL">
<pin name="VCC" direction="pwr"/>
<pin name="EN" direction="in"/>
<pin name="FSW" direction="in"/>
<pin name="SW_2" direction="pwr"/>
<pin name="SW_3" direction="pwr"/>
<pin name="SW_4" direction="pwr"/>
<pin name="SW" direction="pwr"/>
<pin name="BOOT" direction="pwr"/>
<pin name="VIN" direction="pwr"/>
<pin name="SS" direction="in"/>
<pin name="NC_2" direction="pas"/>
<pin name="NC" direction="pas"/>
<pin name="MODE" direction="in"/>
<pin name="VOUT_2" direction="pwr"/>
<pin name="VOUT_3" direction="pwr"/>
<pin name="VOUT" direction="pwr"/>
<pin name="FB" direction="in"/>
<pin name="COMP" direction="out"/>
<pin name="ILIM" direction="in"/>
<pin name="AGND" direction="pwr"/>
<pin name="PGND" direction="pwr"/>
</symbol>
<symbol name="STM32C011F4U6TR">
<pin name="PA0"/>
<pin name="PA1"/>
<pin name="PA2"/>
<pin name="PA3"/>
<pin name="PA4"/>
<pin name="PA5"/>
<pin name="PA6"/>
<pin name="PA7"/>
<pin name="PA8"/>
<pin name="PA11[PA9]"/>
<pin name="PA12[PA10]"/>
<pin name="PA13"/>
<pin name="PA14-BOOT0"/>
<pin name="PB6"/>
<pin name="PB7"/>
<pin name="VSS/VSSA" direction="pwr"/>
<pin name="PC14-OSCX_IN"/>
<pin name="PC15-OSCX_OUT"/>
<pin name="PF2-NRST"/>
<pin name="VDD/VDDA" direction="pwr"/>
</symbol>
<symbol name="LSM6DS3TR">
<pin name="SDO/SA0" direction="out"/>
<pin name="SDX" direction="pas"/>
<pin name="SCX" direction="pas"/>
<pin name="INT1" direction="pas"/>
<pin name="VDDIO" direction="pwr"/>
<pin name="GND_2" direction="pas"/>
<pin name="GND" direction="pas"/>
<pin name="VDD" direction="pwr"/>
<pin name="INT2" direction="pas"/>
<pin name="NC_2" direction="nc"/>
<pin name="NC" direction="nc"/>
<pin name="CS" direction="pas"/>
<pin name="SCL" direction="pas"/>
<pin name="SDA" direction="pas"/>
</symbol>
<symbol name="TPS62162DSG">
<pin name="PGND" direction="pwr"/>
<pin name="VIN" direction="pwr"/>
<pin name="EN" direction="in"/>
<pin name="AGND" direction="pwr"/>
<pin name="FB" direction="in"/>
<pin name="VOS" direction="in"/>
<pin name="SW" direction="pwr"/>
<pin name="PG" direction="hiz"/>
<pin name="PAD" direction="pwr"/>
</symbol>
<symbol name="TPSM863252RDX">
<pin name="VIN" direction="pwr"/>
<pin name="SW" direction="pas"/>
<pin name="VOUT" direction="pwr"/>
<pin name="PGND" direction="pwr"/>
<pin name="PG" direction="oc"/>
<pin name="EN" direction="in"/>
<pin name="FB" direction="pas"/>
</symbol>
<symbol name="TPS65253RHD">
<pin name="ROSC" direction="in"/>
<pin name="FB1" direction="in"/>
<pin name="CMP1" direction="out"/>
<pin name="SS1" direction="in"/>
<pin name="RLIM1" direction="in"/>
<pin name="EN1" direction="in"/>
<pin name="BST1" direction="pwr"/>
<pin name="VIN1" direction="pwr"/>
<pin name="LX1_2" direction="pwr"/>
<pin name="LX1" direction="pwr"/>
<pin name="LX2_2" direction="pwr"/>
<pin name="LX2" direction="pwr"/>
<pin name="VIN2" direction="pwr"/>
<pin name="BST2" direction="pwr"/>
<pin name="EN2" direction="in"/>
<pin name="RLIM2" direction="in"/>
<pin name="SS2" direction="in"/>
<pin name="CMP2" direction="out"/>
<pin name="FB2" direction="in"/>
<pin name="LOW_P" direction="in"/>
<pin name="V7V" direction="pwr"/>
<pin name="V3V" direction="pwr"/>
<pin name="GND_2" direction="pwr"/>
<pin name="PGOOD" direction="oc"/>
<pin name="GND_3" direction="pwr"/>
<pin name="GND_4" direction="pwr"/>
<pin name="GND_5" direction="pwr"/>
<pin name="GND" direction="pwr"/>
<pin name="PAD" direction="pwr"/>
</symbol>
<symbol name="BAJ2DD0WHFP-TR">
<pin name="CTL" direction="pas"/>
<pin name="VCC" direction="pwr"/>
<pin name="N.C./GND" direction="nc"/>
<pin name="OUT" direction="out"/>
<pin name="N.C." direction="nc"/>
<pin name="EPAD" direction="pas"/>
</symbol>
<symbol name="CONN_002P_000C_1">
<pin name="1" direction="pas"/>
<pin name="2" direction="pas"/>
</symbol>
<symbol name="CONN_002P_000C_2">
<pin name="1" direction="pas"/>
<pin name="2" direction="pas"/>
</symbol>
<symbol name="CONN_002P_000C_3">
<pin name="1" direction="pas"/>
<pin name="2" direction="pas"/>
</symbol>
<symbol name="ADV7611">
<pin name="HPA_A/INT2" direction="out"/>
<pin name="CVDD_2" direction="pwr"/>
<pin name="RXA_C-" direction="in"/>
<pin name="RXA_C+" direction="in"/>
<pin name="TVDD_2" direction="pwr"/>
<pin name="RXA_0-" direction="in"/>
<pin name="RXA_0+" direction="in"/>
<pin name="TVDD_3" direction="pwr"/>
<pin name="RXA_1-" direction="in"/>
<pin name="RXA_1+" direction="in"/>
<pin name="TVDD" direction="pwr"/>
<pin name="RXA_2-" direction="in"/>
<pin name="RXA_2+" direction="in"/>
<pin name="CVDD" direction="pwr"/>
<pin name="P23" direction="out"/>
<pin name="P22" direction="out"/>
<pin name="P21" direction="out"/>
<pin name="P20" direction="out"/>
<pin name="P19" direction="out"/>
<pin name="P18" direction="out"/>
<pin name="P17" direction="out"/>
<pin name="P16" direction="out"/>
<pin name="DVDDIO_2" direction="pwr"/>
<pin name="DVDD_2" direction="pwr"/>
<pin name="LLC" direction="out"/>
<pin name="P15" direction="out"/>
<pin name="P14" direction="out"/>
<pin name="P13" direction="out"/>
<pin name="P12" direction="out"/>
<pin name="P11" direction="out"/>
<pin name="P10" direction="out"/>
<pin name="P9" direction="out"/>
<pin name="P8" direction="out"/>
<pin name="DVDDIO_3" direction="pwr"/>
<pin name="P7" direction="out"/>
<pin name="P6" direction="out"/>
<pin name="P5" direction="out"/>
<pin name="P4" direction="out"/>
<pin name="P3" direction="out"/>
<pin name="DVDD_3" direction="pwr"/>
<pin name="P2" direction="out"/>
<pin name="P1" direction="out"/>
<pin name="P0" direction="out"/>
<pin name="DVDDIO" direction="pwr"/>
<pin name="DE" direction="in"/>
<pin name="HS" direction="out"/>
<pin name="VS/FIELD/ALSB"/>
<pin name="AP" direction="out"/>
<pin name="SCLK/INT2" direction="out"/>
<pin name="LRCLK" direction="pas"/>
<pin name="MCLK/INT2" direction="out"/>
<pin name="DVDD_4" direction="pwr"/>
<pin name="SCL" direction="in"/>
<pin name="SDA"/>
<pin name="INT1" direction="out"/>
<pin name="!RESET" direction="in"/>
<pin name="PVDD" direction="pwr"/>
<pin name="XTALP" direction="pas"/>
<pin name="XTALN" direction="pas"/>
<pin name="DVDD" direction="pwr"/>
<pin name="CEC"/>
<pin name="DDCA_SCL" direction="in"/>
<pin name="DDCA_SDA" direction="in"/>
<pin name="RXA_5V" direction="in"/>
<pin name="GND" direction="pas"/>
</symbol>
<symbol name="MCP4728A0-E/UN">
<pin name="VDD" direction="pwr"/>
<pin name="SCL" direction="in"/>
<pin name="SDA"/>
<pin name="!LDAC" direction="in"/>
<pin name="RDY/!BSY" direction="out"/>
<pin name="VOUTA" direction="out"/>
<pin name="VOUTB" direction="out"/>
<pin name="VOUTC" direction="out"/>
<pin name="VOUTD" direction="out"/>
<pin name="VSS" direction="pwr"/>
</symbol>
<symbol name="XC7A100T-2FTG256I_A">
<pin name="IO_L1N_T0_34"/>
<pin name="IO_L1P_T0_34"/>
<pin name="IO_L2N_T0_34"/>
<pin name="IO_L2P_T0_34"/>
<pin name="IO_L3N_T0_DQS_34"/>
<pin name="IO_L3N_T0_DQS_EMCCLK_14"/>
<pin name="IO_L3P_T0_DQS_34"/>
<pin name="IO_L3P_T0_DQS_PUDC_B_14"/>
<pin name="IO_L4N_T0_15"/>
<pin name="IO_L4N_T0_34"/>
<pin name="IO_L4N_T0_35"/>
<pin name="IO_L4P_T0_15"/>
<pin name="IO_L4P_T0_34"/>
<pin name="IO_L4P_T0_35"/>
<pin name="IO_L5N_T0_34"/>
<pin name="IO_L5P_T0_34"/>
<pin name="IO_L6P_T0_15"/>
<pin name="IO_L6P_T0_34"/>
<pin name="IO_L6P_T0_35"/>
<pin name="IO_L6P_T0_FCS_B_14"/>
<pin name="IO_L7N_T1_34"/>
<pin name="IO_L7P_T1_34"/>
<pin name="IO_L8N_T1_34"/>
<pin name="IO_L8P_T1_34"/>
<pin name="IO_L9N_T1_DQS_34"/>
<pin name="IO_L9P_T1_DQS_14"/>
<pin name="IO_L9P_T1_DQS_34"/>
<pin name="IO_L10P_T1_34"/>
<pin name="IO_L11N_T1_SRCC_14"/>
<pin name="IO_L11N_T1_SRCC_15"/>
<pin name="IO_L11N_T1_SRCC_35"/>
<pin name="IO_L11P_T1_SRCC_14"/>
<pin name="IO_L11P_T1_SRCC_15"/>
<pin name="IO_L11P_T1_SRCC_35"/>
<pin name="IO_L12N_T1_MRCC_14"/>
<pin name="IO_L12N_T1_MRCC_15"/>
<pin name="IO_L12N_T1_MRCC_35"/>
<pin name="IO_L12P_T1_MRCC_14"/>
<pin name="IO_L12P_T1_MRCC_15"/>
<pin name="IO_L12P_T1_MRCC_35"/>
<pin name="IO_L13N_T2_MRCC_14"/>
<pin name="IO_L13N_T2_MRCC_15"/>
<pin name="IO_L13N_T2_MRCC_35"/>
<pin name="IO_L13P_T2_MRCC_14"/>
<pin name="IO_L13P_T2_MRCC_15"/>
<pin name="IO_L13P_T2_MRCC_35"/>
<pin name="IO_L14N_T2_SRCC_14"/>
<pin name="IO_L14N_T2_SRCC_15"/>
<pin name="IO_L14N_T2_SRCC_35"/>
<pin name="IO_L14P_T2_SRCC_14"/>
<pin name="IO_L1N_T0_AD0N_15"/>
<pin name="IO_L1N_T0_AD4N_35"/>
<pin name="IO_L1N_T0_D01_DIN_14"/>
<pin name="IO_L1P_T0_AD0P_15"/>
<pin name="IO_L1P_T0_AD4P_35"/>
<pin name="IO_L1P_T0_D00_MOSI_14"/>
<pin name="IO_L2N_T0_AD12N_35"/>
<pin name="IO_L2N_T0_AD8N_15"/>
<pin name="IO_L2N_T0_D03_14"/>
<pin name="IO_L2P_T0_AD12P_35"/>
<pin name="IO_L2P_T0_AD8P_15"/>
<pin name="IO_L2P_T0_D02_14"/>
<pin name="IO_L3N_T0_DQS_AD1N_15"/>
<pin name="IO_L3N_T0_DQS_AD5N_35"/>
<pin name="IO_L3P_T0_DQS_AD1P_15"/>
<pin name="IO_L3P_T0_DQS_AD5P_35"/>
<pin name="IO_L4N_T0_D05_14"/>
<pin name="IO_L4P_T0_D04_14"/>
<pin name="IO_L5N_T0_AD13N_35"/>
<pin name="IO_L5N_T0_AD9N_15"/>
<pin name="IO_L5N_T0_D07_14"/>
<pin name="IO_L5P_T0_AD13P_35"/>
<pin name="IO_L5P_T0_AD9P_15"/>
<pin name="IO_L5P_T0_D06_14"/>
<pin name="IO_L7N_T1_AD2N_15"/>
<pin name="IO_L7N_T1_AD6N_35"/>
<pin name="IO_L7N_T1_D10_14"/>
<pin name="IO_L7P_T1_AD2P_15"/>
<pin name="IO_L7P_T1_AD6P_35"/>
<pin name="IO_L7P_T1_D09_14"/>
<pin name="IO_L8N_T1_AD10N_15"/>
<pin name="IO_L8N_T1_AD14N_35"/>
<pin name="IO_L8N_T1_D12_14"/>
<pin name="IO_L8P_T1_AD10P_15"/>
<pin name="IO_L8P_T1_AD14P_35"/>
<pin name="IO_L8P_T1_D11_14"/>
<pin name="IO_L9N_T1_DQS_AD3N_15"/>
<pin name="IO_L9N_T1_DQS_AD7N_35"/>
<pin name="IO_L9N_T1_DQS_D13_14"/>
<pin name="IO_L9P_T1_DQS_AD3P_15"/>
<pin name="IO_L9P_T1_DQS_AD7P_35"/>
<pin name="IO_L10N_T1_AD11N_15"/>
<pin name="IO_L10N_T1_AD15N_35"/>
<pin name="IO_L10N_T1_D15_14"/>
<pin name="IO_L10P_T1_AD11P_15"/>
<pin name="IO_L10P_T1_AD15P_35"/>
<pin name="IO_L10P_T1_D14_14"/>
<pin name="IO_L16N_T2_A15_D31_14"/>
<pin name="IO_L17N_T2_A13_D29_14"/>
<pin name="IO_L17P_T2_A14_D30_14"/>
</symbol>
<symbol name="XC7A100T-2FTG256I_B">
<pin name="IO_L14P_T2_SRCC_15"/>
<pin name="IO_L14P_T2_SRCC_35"/>
<pin name="IO_L15N_T2_DQS_35"/>
<pin name="IO_L15N_T2_DQS_ADV_B_15"/>
<pin name="IO_L15P_T2_DQS_15"/>
<pin name="IO_L15P_T2_DQS_35"/>
<pin name="IO_L15P_T2_DQS_RDWR_B_14"/>
<pin name="IO_L16N_T2_35"/>
<pin name="IO_L16N_T2_A27_15"/>
<pin name="IO_L16P_T2_35"/>
<pin name="IO_L16P_T2_A28_15"/>
<pin name="IO_L16P_T2_CSI_B_14"/>
<pin name="IO_L17N_T2_35"/>
<pin name="IO_L17N_T2_A25_15"/>
<pin name="IO_L17P_T2_35"/>
<pin name="IO_L17P_T2_A26_15"/>
<pin name="IO_L18N_T2_35"/>
<pin name="IO_L18N_T2_A23_15"/>
<pin name="IO_L18P_T2_35"/>
<pin name="IO_L18P_T2_A24_15"/>
<pin name="IO_L19P_T3_35"/>
<pin name="IO_L19P_T3_A22_15"/>
<pin name="IO_L20N_T3_35"/>
<pin name="IO_L20N_T3_A19_15"/>
<pin name="IO_L20P_T3_35"/>
<pin name="IO_L20P_T3_A20_15"/>
<pin name="IO_L21N_T3_DQS_35"/>
<pin name="IO_L21N_T3_DQS_A18_15"/>
<pin name="IO_L21P_T3_DQS_14"/>
<pin name="IO_L21P_T3_DQS_15"/>
<pin name="IO_L21P_T3_DQS_35"/>
<pin name="IO_L22N_T3_35"/>
<pin name="IO_L22N_T3_A16_15"/>
<pin name="IO_L22P_T3_35"/>
<pin name="IO_L22P_T3_A17_15"/>
<pin name="IO_L23N_T3_35"/>
<pin name="IO_L23N_T3_FWE_B_15"/>
<pin name="IO_L23P_T3_35"/>
<pin name="IO_L23P_T3_FOE_B_15"/>
<pin name="IO_L24N_T3_35"/>
<pin name="IO_L24N_T3_RS0_15"/>
<pin name="IO_L24P_T3_35"/>
<pin name="IO_L24P_T3_RS1_15"/>
<pin name="IO_L18N_T2_A11_D27_14"/>
<pin name="IO_L18P_T2_A12_D28_14"/>
<pin name="IO_L19P_T3_A10_D26_14"/>
<pin name="IO_L20N_T3_A07_D23_14"/>
<pin name="IO_L20P_T3_A08_D24_14"/>
<pin name="IO_L21N_T3_DQS_A06_D22_14"/>
<pin name="IO_L22N_T3_A04_D20_14"/>
<pin name="IO_L22P_T3_A05_D21_14"/>
<pin name="IO_L23N_T3_A02_D18_14"/>
<pin name="IO_L23P_T3_A03_D19_14"/>
<pin name="IO_L24N_T3_A00_D16_14"/>
<pin name="IO_L24P_T3_A01_D17_14"/>
</symbol>
<symbol name="XC7A100T-2FTG256I_C">
<pin name="IO_L6N_T0_D08_VREF_14"/>
<pin name="IO_L6N_T0_VREF_15"/>
<pin name="IO_L6N_T0_VREF_34"/>
<pin name="IO_L6N_T0_VREF_35"/>
<pin name="IO_L19N_T3_A09_D25_VREF_14"/>
<pin name="IO_L19N_T3_A21_VREF_15"/>
<pin name="IO_L19N_T3_VREF_35"/>
<pin name="VCCADC_0" direction="pwr"/>
<pin name="VCCAUX_2" direction="pwr"/>
<pin name="VCCAUX_3" direction="pwr"/>
<pin name="VCCAUX_4" direction="pwr"/>
<pin name="VCCAUX" direction="pwr"/>
<pin name="VCCBATT_0" direction="pwr"/>
<pin name="VCCBRAM_2" direction="pwr"/>
<pin name="VCCBRAM" direction="pwr"/>
<pin name="VCCINT_2" direction="pwr"/>
<pin name="VCCINT_3" direction="pwr"/>
<pin name="VCCINT_4" direction="pwr"/>
<pin name="VCCINT_5" direction="pwr"/>
<pin name="VCCINT_6" direction="pwr"/>
<pin name="VCCINT_7" direction="pwr"/>
<pin name="VCCINT" direction="pwr"/>
<pin name="VCCO_0" direction="pwr"/>
<pin name="VCCO_14_2" direction="pwr"/>
<pin name="VCCO_14_3" direction="pwr"/>
<pin name="VCCO_14_4" direction="pwr"/>
<pin name="VCCO_14_5" direction="pwr"/>
<pin name="VCCO_14_6" direction="pwr"/>
<pin name="VCCO_14" direction="pwr"/>
<pin name="VCCO_15_2" direction="pwr"/>
<pin name="VCCO_15_3" direction="pwr"/>
<pin name="VCCO_15_4" direction="pwr"/>
<pin name="VCCO_15_5" direction="pwr"/>
<pin name="VCCO_15_6" direction="pwr"/>
<pin name="VCCO_15" direction="pwr"/>
<pin name="VCCO_34_2" direction="pwr"/>
<pin name="VCCO_34_3" direction="pwr"/>
<pin name="VCCO_34" direction="pwr"/>
<pin name="VCCO_35_2" direction="pwr"/>
<pin name="VCCO_35_3" direction="pwr"/>
<pin name="VCCO_35_4" direction="pwr"/>
<pin name="VCCO_35_5" direction="pwr"/>
<pin name="VCCO_35_6" direction="pwr"/>
<pin name="VCCO_35" direction="pwr"/>
</symbol>
<symbol name="XC7A100T-2FTG256I">
<pin name="CFGBVS_0" direction="in"/>
<pin name="INIT_B_0"/>
<pin name="M0_0" direction="in"/>
<pin name="M1_0" direction="in"/>
<pin name="M2_0" direction="in"/>
<pin name="PROGRAM_B_0" direction="in"/>
<pin name="TCK_0" direction="in"/>
<pin name="TDI_0" direction="in"/>
<pin name="TMS_0" direction="in"/>
<pin name="VN_0" direction="in"/>
<pin name="VP_0" direction="in"/>
<pin name="CCLK_0"/>
<pin name="DONE_0"/>
<pin name="DXN_0" direction="pas"/>
<pin name="DXP_0" direction="pas"/>
<pin name="IO_L15N_T2_DQS_DOUT_CSO_B_14"/>
<pin name="TDO_0" direction="out"/>
<pin name="IO_0_14"/>
<pin name="IO_0_15"/>
<pin name="IO_0_34"/>
<pin name="IO_0_35"/>
<pin name="IO_25_14"/>
<pin name="IO_25_15"/>
<pin name="IO_25_35"/>
</symbol>
<symbol name="XC7A100T-2FTG256I_D">
<pin name="VREFN_0" direction="pwr"/>
<pin name="VREFP_0" direction="pwr"/>
<pin name="GND_2" direction="pas"/>
<pin name="GND_3" direction="pas"/>
<pin name="GND_4" direction="pas"/>
<pin name="GND_5" direction="pas"/>
<pin name="GND_6" direction="pas"/>
<pin name="GND_7" direction="pas"/>
<pin name="GND_8" direction="pas"/>
<pin name="GND_9" direction="pas"/>
<pin name="GND_10" direction="pas"/>
<pin name="GND_11" direction="pas"/>
<pin name="GND_12" direction="pas"/>
<pin name="GND_13" direction="pas"/>
<pin name="GND_14" direction="pas"/>
<pin name="GND_15" direction="pas"/>
<pin name="GND_16" direction="pas"/>
<pin name="GND_17" direction="pas"/>
<pin name="GND_18" direction="pas"/>
<pin name="GND_19" direction="pas"/>
<pin name="GND_20" direction="pas"/>
<pin name="GND_21" direction="pas"/>
<pin name="GND_22" direction="pas"/>
<pin name="GND_23" direction="pas"/>
<pin name="GND_24" direction="pas"/>
<pin name="GND_25" direction="pas"/>
<pin name="GND_26" direction="pas"/>
<pin name="GND_27" direction="pas"/>
<pin name="GND_28" direction="pas"/>
<pin name="GND_29" direction="pas"/>
<pin name="GND_30" direction="pas"/>
<pin name="GND" direction="pas"/>
<pin name="GNDADC_0" direction="pas"/>
</symbol>
<symbol name="STM32F103C8T6">
<pin name="PA0-WKUP"/>
<pin name="PA1"/>
<pin name="PA2"/>
<pin name="PA3"/>
<pin name="PA4"/>
<pin name="PA5"/>
<pin name="PA6"/>
<pin name="PA7"/>
<pin name="PA8"/>
<pin name="PA9"/>
<pin name="PA10"/>
<pin name="PA11"/>
<pin name="PA12"/>
<pin name="PA13"/>
<pin name="PA14"/>
<pin name="PA15"/>
<pin name="PB0"/>
<pin name="PB1"/>
<pin name="PB2"/>
<pin name="PB3"/>
<pin name="PB4"/>
<pin name="PB5"/>
<pin name="PB6"/>
<pin name="PB7"/>
<pin name="PB8"/>
<pin name="PB9"/>
<pin name="PB10"/>
<pin name="PB11"/>
<pin name="PB12"/>
<pin name="PB13"/>
<pin name="PB14"/>
<pin name="PB15"/>
<pin name="PC13"/>
<pin name="PC14-OSC32_IN"/>
<pin name="PC15-OSC32_OUT"/>
<pin name="NRST"/>
<pin name="BOOT0" direction="in"/>
<pin name="OSC_IN" direction="in"/>
<pin name="OSC_OUT" direction="out"/>
</symbol>
<symbol name="STM32F103C8T6_02">
<pin name="VSS_1" direction="pwr"/>
<pin name="VSS_2" direction="pwr"/>
<pin name="VSS_3" direction="pwr"/>
<pin name="VSSA" direction="pwr"/>
<pin name="VDD_1" direction="pwr"/>
<pin name="VDD_2" direction="pwr"/>
<pin name="VDD_3" direction="pwr"/>
<pin name="VDDA" direction="pwr"/>
<pin name="VBAT" direction="pwr"/>
</symbol>
<symbol name="SW1_1-2_3-4">
<pin name="1" direction="pas"/>
<pin name="3" direction="pas"/>
<pin name="2" direction="pas"/>
<pin name="4" direction="pas"/>
</symbol>
<symbol name="TC1262-3.3VDBTR">
<pin name="VIN" direction="pas"/>
<pin name="GND" direction="pas"/>
<pin name="VOUT" direction="pas"/>
</symbol>
</symbols>
<devicesets>
<deviceset name="AD9361BBC-CSH" prefix="U">
<gates>
<gate name="A" symbol="AD9361-CSH_A"/>
<gate name="B" symbol="AD9361-CSH_B"/>
</gates>
<devices>
<device name="" package="BC-144-7_ADI">
<connects>
<connect gate="A" pin="AUXDAC1" pad="B3"/>
<connect gate="A" pin="AUXDAC2" pad="C3"/>
<connect gate="A" pin="CTRL_IN0" pad="C5"/>
<connect gate="A" pin="CTRL_IN1" pad="C6"/>
<connect gate="A" pin="CTRL_IN2" pad="D6"/>
<connect gate="A" pin="CTRL_IN3" pad="D5"/>
<connect gate="A" pin="CTRL_OUT0" pad="D4"/>
<connect gate="A" pin="CTRL_OUT1" pad="E4"/>
<connect gate="A" pin="CTRL_OUT2" pad="E5"/>
<connect gate="A" pin="CTRL_OUT3" pad="E6"/>
<connect gate="A" pin="CTRL_OUT4" pad="F6"/>
<connect gate="A" pin="CTRL_OUT5" pad="F5"/>
<connect gate="A" pin="CTRL_OUT6" pad="F4"/>
<connect gate="A" pin="DNC" pad="A3"/>
<connect gate="A" pin="FB_CLK_P" pad="F10"/>
<connect gate="A" pin="GPO_0" pad="B7"/>
<connect gate="A" pin="GPO_1" pad="B6"/>
<connect gate="A" pin="GPO_2" pad="B5"/>
<connect gate="A" pin="GPO_3" pad="B4"/>
<connect gate="A" pin="P0_D0/TX_D0_N" pad="E12"/>
<connect gate="A" pin="P0_D1/TX_D0_P" pad="D11"/>
<connect gate="A" pin="P0_D10/TX_D5_N" pad="F8"/>
<connect gate="A" pin="P0_D11/TX_D5_P" pad="E7"/>
<connect gate="A" pin="P0_D2/TX_D1_N" pad="E11"/>
<connect gate="A" pin="P0_D3/TX_D1_P" pad="D10"/>
<connect gate="A" pin="P0_D4/TX_D2_N" pad="E10"/>
<connect gate="A" pin="P0_D5/TX_D2_P" pad="D9"/>
<connect gate="A" pin="P0_D6/TX_D3_N" pad="E9"/>
<connect gate="A" pin="P0_D7/TX_D3_P" pad="D8"/>
<connect gate="A" pin="P0_D8/TX_D4_N" pad="E8"/>
<connect gate="A" pin="P0_D9/TX_D4_P" pad="D7"/>
<connect gate="A" pin="RX2A_N" pad="A1"/>
<connect gate="A" pin="RX2A_P" pad="A2"/>
<connect gate="A" pin="RX2B_N" pad="F1"/>
<connect gate="A" pin="RX2B_P" pad="E1"/>
<connect gate="A" pin="RX2C_N" pad="D1"/>
<connect gate="A" pin="RX2C_P" pad="C1"/>
<connect gate="A" pin="TEST/ENABLE" pad="C4"/>
<connect gate="A" pin="TX2A_N" pad="A7"/>
<connect gate="A" pin="TX2A_P" pad="A8"/>
<connect gate="A" pin="TX2B_N" pad="A9"/>
<connect gate="A" pin="TX2B_P" pad="A10"/>
<connect gate="A" pin="TX_EXT_LO_IN" pad="A12"/>
<connect gate="A" pin="TX_MON2" pad="A5"/>
<connect gate="A" pin="TX_VCO_LDO_OUT" pad="B11"/>
<connect gate="A" pin="VDDA1P1_TX_VCO" pad="A11"/>
<connect gate="A" pin="VDDA1P3_RX_LO" pad="E2"/>
<connect gate="A" pin="VDDA1P3_RX_RF" pad="D2"/>
<connect gate="A" pin="VDDA1P3_RX_TX" pad="D3"/>
<connect gate="A" pin="VDDA1P3_RX_VCO_LDO" pad="F2"/>
<connect gate="A" pin="VDDA1P3_TX_LO_BUFFER" pad="E3"/>
<connect gate="A" pin="VDDA1P3_TX_VCO_LDO" pad="B10"/>
<connect gate="A" pin="VDDA_1P3_TX_LO" pad="B9"/>
<connect gate="A" pin="VDDD1P3_DIG" pad="F12"/>
<connect gate="A" pin="VDD_GPO" pad="B8"/>
<connect gate="A" pin="VSSA" pad="F3"/>
<connect gate="A" pin="VSSA_10" pad="C9"/>
<connect gate="A" pin="VSSA_11" pad="C10"/>
<connect gate="A" pin="VSSA_12" pad="C11"/>
<connect gate="A" pin="VSSA_13" pad="C12"/>
<connect gate="A" pin="VSSA_2" pad="A4"/>
<connect gate="A" pin="VSSA_3" pad="A6"/>
<connect gate="A" pin="VSSA_4" pad="B1"/>
<connect gate="A" pin="VSSA_5" pad="B2"/>
<connect gate="A" pin="VSSA_6" pad="B12"/>
<connect gate="A" pin="VSSA_7" pad="C2"/>
<connect gate="A" pin="VSSA_8" pad="C7"/>
<connect gate="A" pin="VSSA_9" pad="C8"/>
<connect gate="A" pin="VSSD" pad="F11"/>
<connect gate="A" pin="VSSD_2" pad="D12"/>
<connect gate="A" pin="VSSD_3" pad="F7"/>
<connect gate="A" pin="VSSD_4" pad="F9"/>
<connect gate="B" pin="AUXADC" pad="L5"/>
<connect gate="B" pin="CLK_OUT" pad="J6"/>
<connect gate="B" pin="CTRL_OUT7" pad="G4"/>
<connect gate="B" pin="DATA_CLK_N" pad="H11"/>
<connect gate="B" pin="DATA_CLK_P" pad="G11"/>
<connect gate="B" pin="DNC" pad="M3"/>
<connect gate="B" pin="ENABLE" pad="G6"/>
<connect gate="B" pin="EN_AGC" pad="G5"/>
<connect gate="B" pin="FB_CLK_N" pad="G10"/>
<connect gate="B" pin="P1_D0/RX_D0_N" pad="K11"/>
<connect gate="B" pin="P1_D1/RX_D0_P" pad="J12"/>
<connect gate="B" pin="P1_D10/RX_D5_N" pad="J7"/>
<connect gate="B" pin="P1_D11/RX_D5_P" pad="H8"/>
<connect gate="B" pin="P1_D2/RX_D1_N" pad="K10"/>
<connect gate="B" pin="P1_D3/RX_D1_P" pad="J11"/>
<connect gate="B" pin="P1_D4/RX_D2_N" pad="K9"/>
<connect gate="B" pin="P1_D5/RX_D2_P" pad="J10"/>
<connect gate="B" pin="P1_D6/RX_D3_N" pad="K8"/>
<connect gate="B" pin="P1_D7/RX_D3_P" pad="J9"/>
<connect gate="B" pin="P1_D8/RX_D4_N" pad="K7"/>
<connect gate="B" pin="P1_D9/RX_D4_P" pad="J8"/>
<connect gate="B" pin="RBIAS" pad="L4"/>
<connect gate="B" pin="RESETB" pad="K5"/>
<connect gate="B" pin="RX1A_N" pad="M2"/>
<connect gate="B" pin="RX1A_P" pad="M1"/>
<connect gate="B" pin="RX1B_N" pad="J1"/>
<connect gate="B" pin="RX1B_P" pad="H1"/>
<connect gate="B" pin="RX1C_N" pad="L1"/>
<connect gate="B" pin="RX1C_P" pad="K1"/>
<connect gate="B" pin="RX_EXT_LO_IN" pad="G1"/>
<connect gate="B" pin="RX_FRAME_N" pad="G7"/>
<connect gate="B" pin="RX_FRAME_P" pad="G8"/>
<connect gate="B" pin="RX_VCO_LDO_OUT" pad="G2"/>
<connect gate="B" pin="SPI_CLK" pad="J5"/>
<connect gate="B" pin="SPI_DI" pad="J4"/>
<connect gate="B" pin="SPI_DO" pad="L6"/>
<connect gate="B" pin="SPI_ENB" pad="K6"/>
<connect gate="B" pin="SYNC_IN" pad="H5"/>
<connect gate="B" pin="TX1A_N" pad="M8"/>
<connect gate="B" pin="TX1A_P" pad="M7"/>
<connect gate="B" pin="TX1B_N" pad="M10"/>
<connect gate="B" pin="TX1B_P" pad="M9"/>
<connect gate="B" pin="TXNRX" pad="H4"/>
<connect gate="B" pin="TX_FRAME_N" pad="H9"/>
<connect gate="B" pin="TX_FRAME_P" pad="G9"/>
<connect gate="B" pin="TX_MON1" pad="M5"/>
<connect gate="B" pin="VDDA1P1_RX_VCO" pad="G3"/>
<connect gate="B" pin="VDDA1P3_BB" pad="K4"/>
<connect gate="B" pin="VDDA1P3_RX_SYNTH" pad="J3"/>
<connect gate="B" pin="VDDA1P3_TX_SYNTH" pad="K3"/>
<connect gate="B" pin="VDD_INTERFACE" pad="H12"/>
<connect gate="B" pin="VSSA" pad="M6"/>
<connect gate="B" pin="VSSA_10" pad="L8"/>
<connect gate="B" pin="VSSA_11" pad="L9"/>
<connect gate="B" pin="VSSA_12" pad="L10"/>
<connect gate="B" pin="VSSA_13" pad="L11"/>
<connect gate="B" pin="VSSA_14" pad="L12"/>
<connect gate="B" pin="VSSA_15" pad="M4"/>
<connect gate="B" pin="VSSA_2" pad="H2"/>
<connect gate="B" pin="VSSA_3" pad="H3"/>
<connect gate="B" pin="VSSA_4" pad="H6"/>
<connect gate="B" pin="VSSA_5" pad="J2"/>
<connect gate="B" pin="VSSA_6" pad="K2"/>
<connect gate="B" pin="VSSA_7" pad="L2"/>
<connect gate="B" pin="VSSA_8" pad="L3"/>
<connect gate="B" pin="VSSA_9" pad="L7"/>
<connect gate="B" pin="VSSD" pad="K12"/>
<connect gate="B" pin="VSSD_2" pad="G12"/>
<connect gate="B" pin="VSSD_3" pad="H7"/>
<connect gate="B" pin="VSSD_4" pad="H10"/>
<connect gate="B" pin="XTALN" pad="M12"/>
<connect gate="B" pin="XTALP" pad="M11"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="AD9361BBC-CSH"/>
<attribute name="MFR_NAME" value="Analog Devices Inc"/>
<attribute name="TYPE" value="RF"/>
</technology>
</technologies>
</device>
<device name="BC-144-7_ADI-M" package="BC-144-7_ADI-M">
<connects>
<connect gate="A" pin="AUXDAC1" pad="B3"/>
<connect gate="A" pin="AUXDAC2" pad="C3"/>
<connect gate="A" pin="CTRL_IN0" pad="C5"/>
<connect gate="A" pin="CTRL_IN1" pad="C6"/>
<connect gate="A" pin="CTRL_IN2" pad="D6"/>
<connect gate="A" pin="CTRL_IN3" pad="D5"/>
<connect gate="A" pin="CTRL_OUT0" pad="D4"/>
<connect gate="A" pin="CTRL_OUT1" pad="E4"/>
<connect gate="A" pin="CTRL_OUT2" pad="E5"/>
<connect gate="A" pin="CTRL_OUT3" pad="E6"/>
<connect gate="A" pin="CTRL_OUT4" pad="F6"/>
<connect gate="A" pin="CTRL_OUT5" pad="F5"/>
<connect gate="A" pin="CTRL_OUT6" pad="F4"/>
<connect gate="A" pin="DNC" pad="A3"/>
<connect gate="A" pin="FB_CLK_P" pad="F10"/>
<connect gate="A" pin="GPO_0" pad="B7"/>
<connect gate="A" pin="GPO_1" pad="B6"/>
<connect gate="A" pin="GPO_2" pad="B5"/>
<connect gate="A" pin="GPO_3" pad="B4"/>
<connect gate="A" pin="P0_D0/TX_D0_N" pad="E12"/>
<connect gate="A" pin="P0_D1/TX_D0_P" pad="D11"/>
<connect gate="A" pin="P0_D10/TX_D5_N" pad="F8"/>
<connect gate="A" pin="P0_D11/TX_D5_P" pad="E7"/>
<connect gate="A" pin="P0_D2/TX_D1_N" pad="E11"/>
<connect gate="A" pin="P0_D3/TX_D1_P" pad="D10"/>
<connect gate="A" pin="P0_D4/TX_D2_N" pad="E10"/>
<connect gate="A" pin="P0_D5/TX_D2_P" pad="D9"/>
<connect gate="A" pin="P0_D6/TX_D3_N" pad="E9"/>
<connect gate="A" pin="P0_D7/TX_D3_P" pad="D8"/>
<connect gate="A" pin="P0_D8/TX_D4_N" pad="E8"/>
<connect gate="A" pin="P0_D9/TX_D4_P" pad="D7"/>
<connect gate="A" pin="RX2A_N" pad="A1"/>
<connect gate="A" pin="RX2A_P" pad="A2"/>
<connect gate="A" pin="RX2B_N" pad="F1"/>
<connect gate="A" pin="RX2B_P" pad="E1"/>
<connect gate="A" pin="RX2C_N" pad="D1"/>
<connect gate="A" pin="RX2C_P" pad="C1"/>
<connect gate="A" pin="TEST/ENABLE" pad="C4"/>
<connect gate="A" pin="TX2A_N" pad="A7"/>
<connect gate="A" pin="TX2A_P" pad="A8"/>
<connect gate="A" pin="TX2B_N" pad="A9"/>
<connect gate="A" pin="TX2B_P" pad="A10"/>
<connect gate="A" pin="TX_EXT_LO_IN" pad="A12"/>
<connect gate="A" pin="TX_MON2" pad="A5"/>
<connect gate="A" pin="TX_VCO_LDO_OUT" pad="B11"/>
<connect gate="A" pin="VDDA1P1_TX_VCO" pad="A11"/>
<connect gate="A" pin="VDDA1P3_RX_LO" pad="E2"/>
<connect gate="A" pin="VDDA1P3_RX_RF" pad="D2"/>
<connect gate="A" pin="VDDA1P3_RX_TX" pad="D3"/>
<connect gate="A" pin="VDDA1P3_RX_VCO_LDO" pad="F2"/>
<connect gate="A" pin="VDDA1P3_TX_LO_BUFFER" pad="E3"/>
<connect gate="A" pin="VDDA1P3_TX_VCO_LDO" pad="B10"/>
<connect gate="A" pin="VDDA_1P3_TX_LO" pad="B9"/>
<connect gate="A" pin="VDDD1P3_DIG" pad="F12"/>
<connect gate="A" pin="VDD_GPO" pad="B8"/>
<connect gate="A" pin="VSSA" pad="F3"/>
<connect gate="A" pin="VSSA_10" pad="C9"/>
<connect gate="A" pin="VSSA_11" pad="C10"/>
<connect gate="A" pin="VSSA_12" pad="C11"/>
<connect gate="A" pin="VSSA_13" pad="C12"/>
<connect gate="A" pin="VSSA_2" pad="A4"/>
<connect gate="A" pin="VSSA_3" pad="A6"/>
<connect gate="A" pin="VSSA_4" pad="B1"/>
<connect gate="A" pin="VSSA_5" pad="B2"/>
<connect gate="A" pin="VSSA_6" pad="B12"/>
<connect gate="A" pin="VSSA_7" pad="C2"/>
<connect gate="A" pin="VSSA_8" pad="C7"/>
<connect gate="A" pin="VSSA_9" pad="C8"/>
<connect gate="A" pin="VSSD" pad="F11"/>
<connect gate="A" pin="VSSD_2" pad="D12"/>
<connect gate="A" pin="VSSD_3" pad="F7"/>
<connect gate="A" pin="VSSD_4" pad="F9"/>
<connect gate="B" pin="AUXADC" pad="L5"/>
<connect gate="B" pin="CLK_OUT" pad="J6"/>
<connect gate="B" pin="CTRL_OUT7" pad="G4"/>
<connect gate="B" pin="DATA_CLK_N" pad="H11"/>
<connect gate="B" pin="DATA_CLK_P" pad="G11"/>
<connect gate="B" pin="DNC" pad="M3"/>
<connect gate="B" pin="ENABLE" pad="G6"/>
<connect gate="B" pin="EN_AGC" pad="G5"/>
<connect gate="B" pin="FB_CLK_N" pad="G10"/>
<connect gate="B" pin="P1_D0/RX_D0_N" pad="K11"/>
<connect gate="B" pin="P1_D1/RX_D0_P" pad="J12"/>
<connect gate="B" pin="P1_D10/RX_D5_N" pad="J7"/>
<connect gate="B" pin="P1_D11/RX_D5_P" pad="H8"/>
<connect gate="B" pin="P1_D2/RX_D1_N" pad="K10"/>
<connect gate="B" pin="P1_D3/RX_D1_P" pad="J11"/>
<connect gate="B" pin="P1_D4/RX_D2_N" pad="K9"/>
<connect gate="B" pin="P1_D5/RX_D2_P" pad="J10"/>
<connect gate="B" pin="P1_D6/RX_D3_N" pad="K8"/>
<connect gate="B" pin="P1_D7/RX_D3_P" pad="J9"/>
<connect gate="B" pin="P1_D8/RX_D4_N" pad="K7"/>
<connect gate="B" pin="P1_D9/RX_D4_P" pad="J8"/>
<connect gate="B" pin="RBIAS" pad="L4"/>
<connect gate="B" pin="RESETB" pad="K5"/>
<connect gate="B" pin="RX1A_N" pad="M2"/>
<connect gate="B" pin="RX1A_P" pad="M1"/>
<connect gate="B" pin="RX1B_N" pad="J1"/>
<connect gate="B" pin="RX1B_P" pad="H1"/>
<connect gate="B" pin="RX1C_N" pad="L1"/>
<connect gate="B" pin="RX1C_P" pad="K1"/>
<connect gate="B" pin="RX_EXT_LO_IN" pad="G1"/>
<connect gate="B" pin="RX_FRAME_N" pad="G7"/>
<connect gate="B" pin="RX_FRAME_P" pad="G8"/>
<connect gate="B" pin="RX_VCO_LDO_OUT" pad="G2"/>
<connect gate="B" pin="SPI_CLK" pad="J5"/>
<connect gate="B" pin="SPI_DI" pad="J4"/>
<connect gate="B" pin="SPI_DO" pad="L6"/>
<connect gate="B" pin="SPI_ENB" pad="K6"/>
<connect gate="B" pin="SYNC_IN" pad="H5"/>
<connect gate="B" pin="TX1A_N" pad="M8"/>
<connect gate="B" pin="TX1A_P" pad="M7"/>
<connect gate="B" pin="TX1B_N" pad="M10"/>
<connect gate="B" pin="TX1B_P" pad="M9"/>
<connect gate="B" pin="TXNRX" pad="H4"/>
<connect gate="B" pin="TX_FRAME_N" pad="H9"/>
<connect gate="B" pin="TX_FRAME_P" pad="G9"/>
<connect gate="B" pin="TX_MON1" pad="M5"/>
<connect gate="B" pin="VDDA1P1_RX_VCO" pad="G3"/>
<connect gate="B" pin="VDDA1P3_BB" pad="K4"/>
<connect gate="B" pin="VDDA1P3_RX_SYNTH" pad="J3"/>
<connect gate="B" pin="VDDA1P3_TX_SYNTH" pad="K3"/>
<connect gate="B" pin="VDD_INTERFACE" pad="H12"/>
<connect gate="B" pin="VSSA" pad="M6"/>
<connect gate="B" pin="VSSA_10" pad="L8"/>
<connect gate="B" pin="VSSA_11" pad="L9"/>
<connect gate="B" pin="VSSA_12" pad="L10"/>
<connect gate="B" pin="VSSA_13" pad="L11"/>
<connect gate="B" pin="VSSA_14" pad="L12"/>
<connect gate="B" pin="VSSA_15" pad="M4"/>
<connect gate="B" pin="VSSA_2" pad="H2"/>
<connect gate="B" pin="VSSA_3" pad="H3"/>
<connect gate="B" pin="VSSA_4" pad="H6"/>
<connect gate="B" pin="VSSA_5" pad="J2"/>
<connect gate="B" pin="VSSA_6" pad="K2"/>
<connect gate="B" pin="VSSA_7" pad="L2"/>
<connect gate="B" pin="VSSA_8" pad="L3"/>
<connect gate="B" pin="VSSA_9" pad="L7"/>
<connect gate="B" pin="VSSD" pad="K12"/>
<connect gate="B" pin="VSSD_2" pad="G12"/>
<connect gate="B" pin="VSSD_3" pad="H7"/>
<connect gate="B" pin="VSSD_4" pad="H10"/>
<connect gate="B" pin="XTALN" pad="M12"/>
<connect gate="B" pin="XTALP" pad="M11"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="AD9361BBC-CSH"/>
<attribute name="MFR_NAME" value="Analog Devices Inc"/>
<attribute name="TYPE" value="RF"/>
</technology>
</technologies>
</device>
<device name="BC-144-7_ADI-L" package="BC-144-7_ADI-L">
<connects>
<connect gate="A" pin="AUXDAC1" pad="B3"/>
<connect gate="A" pin="AUXDAC2" pad="C3"/>
<connect gate="A" pin="CTRL_IN0" pad="C5"/>
<connect gate="A" pin="CTRL_IN1" pad="C6"/>
<connect gate="A" pin="CTRL_IN2" pad="D6"/>
<connect gate="A" pin="CTRL_IN3" pad="D5"/>
<connect gate="A" pin="CTRL_OUT0" pad="D4"/>
<connect gate="A" pin="CTRL_OUT1" pad="E4"/>
<connect gate="A" pin="CTRL_OUT2" pad="E5"/>
<connect gate="A" pin="CTRL_OUT3" pad="E6"/>
<connect gate="A" pin="CTRL_OUT4" pad="F6"/>
<connect gate="A" pin="CTRL_OUT5" pad="F5"/>
<connect gate="A" pin="CTRL_OUT6" pad="F4"/>
<connect gate="A" pin="DNC" pad="A3"/>
<connect gate="A" pin="FB_CLK_P" pad="F10"/>
<connect gate="A" pin="GPO_0" pad="B7"/>
<connect gate="A" pin="GPO_1" pad="B6"/>
<connect gate="A" pin="GPO_2" pad="B5"/>
<connect gate="A" pin="GPO_3" pad="B4"/>
<connect gate="A" pin="P0_D0/TX_D0_N" pad="E12"/>
<connect gate="A" pin="P0_D1/TX_D0_P" pad="D11"/>
<connect gate="A" pin="P0_D10/TX_D5_N" pad="F8"/>
<connect gate="A" pin="P0_D11/TX_D5_P" pad="E7"/>
<connect gate="A" pin="P0_D2/TX_D1_N" pad="E11"/>
<connect gate="A" pin="P0_D3/TX_D1_P" pad="D10"/>
<connect gate="A" pin="P0_D4/TX_D2_N" pad="E10"/>
<connect gate="A" pin="P0_D5/TX_D2_P" pad="D9"/>
<connect gate="A" pin="P0_D6/TX_D3_N" pad="E9"/>
<connect gate="A" pin="P0_D7/TX_D3_P" pad="D8"/>
<connect gate="A" pin="P0_D8/TX_D4_N" pad="E8"/>
<connect gate="A" pin="P0_D9/TX_D4_P" pad="D7"/>
<connect gate="A" pin="RX2A_N" pad="A1"/>
<connect gate="A" pin="RX2A_P" pad="A2"/>
<connect gate="A" pin="RX2B_N" pad="F1"/>
<connect gate="A" pin="RX2B_P" pad="E1"/>
<connect gate="A" pin="RX2C_N" pad="D1"/>
<connect gate="A" pin="RX2C_P" pad="C1"/>
<connect gate="A" pin="TEST/ENABLE" pad="C4"/>
<connect gate="A" pin="TX2A_N" pad="A7"/>
<connect gate="A" pin="TX2A_P" pad="A8"/>
<connect gate="A" pin="TX2B_N" pad="A9"/>
<connect gate="A" pin="TX2B_P" pad="A10"/>
<connect gate="A" pin="TX_EXT_LO_IN" pad="A12"/>
<connect gate="A" pin="TX_MON2" pad="A5"/>
<connect gate="A" pin="TX_VCO_LDO_OUT" pad="B11"/>
<connect gate="A" pin="VDDA1P1_TX_VCO" pad="A11"/>
<connect gate="A" pin="VDDA1P3_RX_LO" pad="E2"/>
<connect gate="A" pin="VDDA1P3_RX_RF" pad="D2"/>
<connect gate="A" pin="VDDA1P3_RX_TX" pad="D3"/>
<connect gate="A" pin="VDDA1P3_RX_VCO_LDO" pad="F2"/>
<connect gate="A" pin="VDDA1P3_TX_LO_BUFFER" pad="E3"/>
<connect gate="A" pin="VDDA1P3_TX_VCO_LDO" pad="B10"/>
<connect gate="A" pin="VDDA_1P3_TX_LO" pad="B9"/>
<connect gate="A" pin="VDDD1P3_DIG" pad="F12"/>
<connect gate="A" pin="VDD_GPO" pad="B8"/>
<connect gate="A" pin="VSSA" pad="F3"/>
<connect gate="A" pin="VSSA_10" pad="C9"/>
<connect gate="A" pin="VSSA_11" pad="C10"/>
<connect gate="A" pin="VSSA_12" pad="C11"/>
<connect gate="A" pin="VSSA_13" pad="C12"/>
<connect gate="A" pin="VSSA_2" pad="A4"/>
<connect gate="A" pin="VSSA_3" pad="A6"/>
<connect gate="A" pin="VSSA_4" pad="B1"/>
<connect gate="A" pin="VSSA_5" pad="B2"/>
<connect gate="A" pin="VSSA_6" pad="B12"/>
<connect gate="A" pin="VSSA_7" pad="C2"/>
<connect gate="A" pin="VSSA_8" pad="C7"/>
<connect gate="A" pin="VSSA_9" pad="C8"/>
<connect gate="A" pin="VSSD" pad="F11"/>
<connect gate="A" pin="VSSD_2" pad="D12"/>
<connect gate="A" pin="VSSD_3" pad="F7"/>
<connect gate="A" pin="VSSD_4" pad="F9"/>
<connect gate="B" pin="AUXADC" pad="L5"/>
<connect gate="B" pin="CLK_OUT" pad="J6"/>
<connect gate="B" pin="CTRL_OUT7" pad="G4"/>
<connect gate="B" pin="DATA_CLK_N" pad="H11"/>
<connect gate="B" pin="DATA_CLK_P" pad="G11"/>
<connect gate="B" pin="DNC" pad="M3"/>
<connect gate="B" pin="ENABLE" pad="G6"/>
<connect gate="B" pin="EN_AGC" pad="G5"/>
<connect gate="B" pin="FB_CLK_N" pad="G10"/>
<connect gate="B" pin="P1_D0/RX_D0_N" pad="K11"/>
<connect gate="B" pin="P1_D1/RX_D0_P" pad="J12"/>
<connect gate="B" pin="P1_D10/RX_D5_N" pad="J7"/>
<connect gate="B" pin="P1_D11/RX_D5_P" pad="H8"/>
<connect gate="B" pin="P1_D2/RX_D1_N" pad="K10"/>
<connect gate="B" pin="P1_D3/RX_D1_P" pad="J11"/>
<connect gate="B" pin="P1_D4/RX_D2_N" pad="K9"/>
<connect gate="B" pin="P1_D5/RX_D2_P" pad="J10"/>
<connect gate="B" pin="P1_D6/RX_D3_N" pad="K8"/>
<connect gate="B" pin="P1_D7/RX_D3_P" pad="J9"/>
<connect gate="B" pin="P1_D8/RX_D4_N" pad="K7"/>
<connect gate="B" pin="P1_D9/RX_D4_P" pad="J8"/>
<connect gate="B" pin="RBIAS" pad="L4"/>
<connect gate="B" pin="RESETB" pad="K5"/>
<connect gate="B" pin="RX1A_N" pad="M2"/>
<connect gate="B" pin="RX1A_P" pad="M1"/>
<connect gate="B" pin="RX1B_N" pad="J1"/>
<connect gate="B" pin="RX1B_P" pad="H1"/>
<connect gate="B" pin="RX1C_N" pad="L1"/>
<connect gate="B" pin="RX1C_P" pad="K1"/>
<connect gate="B" pin="RX_EXT_LO_IN" pad="G1"/>
<connect gate="B" pin="RX_FRAME_N" pad="G7"/>
<connect gate="B" pin="RX_FRAME_P" pad="G8"/>
<connect gate="B" pin="RX_VCO_LDO_OUT" pad="G2"/>
<connect gate="B" pin="SPI_CLK" pad="J5"/>
<connect gate="B" pin="SPI_DI" pad="J4"/>
<connect gate="B" pin="SPI_DO" pad="L6"/>
<connect gate="B" pin="SPI_ENB" pad="K6"/>
<connect gate="B" pin="SYNC_IN" pad="H5"/>
<connect gate="B" pin="TX1A_N" pad="M8"/>
<connect gate="B" pin="TX1A_P" pad="M7"/>
<connect gate="B" pin="TX1B_N" pad="M10"/>
<connect gate="B" pin="TX1B_P" pad="M9"/>
<connect gate="B" pin="TXNRX" pad="H4"/>
<connect gate="B" pin="TX_FRAME_N" pad="H9"/>
<connect gate="B" pin="TX_FRAME_P" pad="G9"/>
<connect gate="B" pin="TX_MON1" pad="M5"/>
<connect gate="B" pin="VDDA1P1_RX_VCO" pad="G3"/>
<connect gate="B" pin="VDDA1P3_BB" pad="K4"/>
<connect gate="B" pin="VDDA1P3_RX_SYNTH" pad="J3"/>
<connect gate="B" pin="VDDA1P3_TX_SYNTH" pad="K3"/>
<connect gate="B" pin="VDD_INTERFACE" pad="H12"/>
<connect gate="B" pin="VSSA" pad="M6"/>
<connect gate="B" pin="VSSA_10" pad="L8"/>
<connect gate="B" pin="VSSA_11" pad="L9"/>
<connect gate="B" pin="VSSA_12" pad="L10"/>
<connect gate="B" pin="VSSA_13" pad="L11"/>
<connect gate="B" pin="VSSA_14" pad="L12"/>
<connect gate="B" pin="VSSA_15" pad="M4"/>
<connect gate="B" pin="VSSA_2" pad="H2"/>
<connect gate="B" pin="VSSA_3" pad="H3"/>
<connect gate="B" pin="VSSA_4" pad="H6"/>
<connect gate="B" pin="VSSA_5" pad="J2"/>
<connect gate="B" pin="VSSA_6" pad="K2"/>
<connect gate="B" pin="VSSA_7" pad="L2"/>
<connect gate="B" pin="VSSA_8" pad="L3"/>
<connect gate="B" pin="VSSA_9" pad="L7"/>
<connect gate="B" pin="VSSD" pad="K12"/>
<connect gate="B" pin="VSSD_2" pad="G12"/>
<connect gate="B" pin="VSSD_3" pad="H7"/>
<connect gate="B" pin="VSSD_4" pad="H10"/>
<connect gate="B" pin="XTALN" pad="M12"/>
<connect gate="B" pin="XTALP" pad="M11"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="AD9361BBC-CSH"/>
<attribute name="MFR_NAME" value="Analog Devices Inc"/>
<attribute name="TYPE" value="RF"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="SI5351A-B-GM" prefix="U">
<gates>
<gate name="A" symbol="SI5351A-B-GM"/>
</gates>
<devices>
<device name="" package="QFN20_SIL">
<connects>
<connect gate="A" pin="A0" pad="3"/>
<connect gate="A" pin="CLK0" pad="13"/>
<connect gate="A" pin="CLK1" pad="12"/>
<connect gate="A" pin="CLK2" pad="9"/>
<connect gate="A" pin="CLK3" pad="8"/>
<connect gate="A" pin="CLK4" pad="19"/>
<connect gate="A" pin="CLK5" pad="17"/>
<connect gate="A" pin="CLK6" pad="16"/>
<connect gate="A" pin="CLK7" pad="15"/>
<connect gate="A" pin="EPAD" pad="21"/>
<connect gate="A" pin="OEB" pad="7"/>
<connect gate="A" pin="SCL" pad="4"/>
<connect gate="A" pin="SDA" pad="5"/>
<connect gate="A" pin="SSEN" pad="6"/>
<connect gate="A" pin="VDD" pad="20"/>
<connect gate="A" pin="VDDOA" pad="11"/>
<connect gate="A" pin="VDDOB" pad="10"/>
<connect gate="A" pin="VDDOC" pad="18"/>
<connect gate="A" pin="VDDOD" pad="14"/>
<connect gate="A" pin="XA" pad="1"/>
<connect gate="A" pin="XB" pad="2"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="SI5351A-B-GM"/>
<attribute name="MFR_NAME" value="Silicon Labs"/>
</technology>
</technologies>
</device>
<device name="QFN20_SIL-M" package="QFN20_SIL-M">
<connects>
<connect gate="A" pin="A0" pad="3"/>
<connect gate="A" pin="CLK0" pad="13"/>
<connect gate="A" pin="CLK1" pad="12"/>
<connect gate="A" pin="CLK2" pad="9"/>
<connect gate="A" pin="CLK3" pad="8"/>
<connect gate="A" pin="CLK4" pad="19"/>
<connect gate="A" pin="CLK5" pad="17"/>
<connect gate="A" pin="CLK6" pad="16"/>
<connect gate="A" pin="CLK7" pad="15"/>
<connect gate="A" pin="EPAD" pad="21"/>
<connect gate="A" pin="OEB" pad="7"/>
<connect gate="A" pin="SCL" pad="4"/>
<connect gate="A" pin="SDA" pad="5"/>
<connect gate="A" pin="SSEN" pad="6"/>
<connect gate="A" pin="VDD" pad="20"/>
<connect gate="A" pin="VDDOA" pad="11"/>
<connect gate="A" pin="VDDOB" pad="10"/>
<connect gate="A" pin="VDDOC" pad="18"/>
<connect gate="A" pin="VDDOD" pad="14"/>
<connect gate="A" pin="XA" pad="1"/>
<connect gate="A" pin="XB" pad="2"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="SI5351A-B-GM"/>
<attribute name="MFR_NAME" value="Silicon Labs"/>
</technology>
</technologies>
</device>
<device name="QFN20_SIL-L" package="QFN20_SIL-L">
<connects>
<connect gate="A" pin="A0" pad="3"/>
<connect gate="A" pin="CLK0" pad="13"/>
<connect gate="A" pin="CLK1" pad="12"/>
<connect gate="A" pin="CLK2" pad="9"/>
<connect gate="A" pin="CLK3" pad="8"/>
<connect gate="A" pin="CLK4" pad="19"/>
<connect gate="A" pin="CLK5" pad="17"/>
<connect gate="A" pin="CLK6" pad="16"/>
<connect gate="A" pin="CLK7" pad="15"/>
<connect gate="A" pin="EPAD" pad="21"/>
<connect gate="A" pin="OEB" pad="7"/>
<connect gate="A" pin="SCL" pad="4"/>
<connect gate="A" pin="SDA" pad="5"/>
<connect gate="A" pin="SSEN" pad="6"/>
<connect gate="A" pin="VDD" pad="20"/>
<connect gate="A" pin="VDDOA" pad="11"/>
<connect gate="A" pin="VDDOB" pad="10"/>
<connect gate="A" pin="VDDOC" pad="18"/>
<connect gate="A" pin="VDDOD" pad="14"/>
<connect gate="A" pin="XA" pad="1"/>
<connect gate="A" pin="XB" pad="2"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="SI5351A-B-GM"/>
<attribute name="MFR_NAME" value="Silicon Labs"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="XC7A100T-2FGG484I" prefix="U">
<gates>
<gate name="A" symbol="XC7A100T-FGG484_A"/>
<gate name="B" symbol="XC7A100T-FGG484_B"/>
<gate name="C" symbol="XC7A100T-FGG484_C"/>
<gate name="D" symbol="XC7A100T-FGG484_D"/>
<gate name="E" symbol="XC7A100T-FGG484_E"/>
</gates>
<devices>
<device name="" package="FGG484(ARTIX-7)_XIL">
<connects>
<connect gate="A" pin="GND" pad="L2"/>
<connect gate="A" pin="GNDADC_0" pad="K9"/>
<connect gate="A" pin="GND_10" pad="D3"/>
<connect gate="A" pin="GND_11" pad="D4"/>
<connect gate="A" pin="GND_12" pad="D8"/>
<connect gate="A" pin="GND_13" pad="E4"/>
<connect gate="A" pin="GND_14" pad="E5"/>
<connect gate="A" pin="GND_15" pad="E7"/>
<connect gate="A" pin="GND_16" pad="E9"/>
<connect gate="A" pin="GND_17" pad="F5"/>
<connect gate="A" pin="GND_18" pad="G5"/>
<connect gate="A" pin="GND_19" pad="G6"/>
<connect gate="A" pin="GND_2" pad="A2"/>
<connect gate="A" pin="GND_20" pad="G7"/>
<connect gate="A" pin="GND_21" pad="G8"/>
<connect gate="A" pin="GND_22" pad="G9"/>
<connect gate="A" pin="GND_23" pad="H1"/>
<connect gate="A" pin="GND_24" pad="H7"/>
<connect gate="A" pin="GND_25" pad="H9"/>
<connect gate="A" pin="GND_26" pad="J8"/>
<connect gate="A" pin="GND_27" pad="K5"/>
<connect gate="A" pin="GND_28" pad="K7"/>
<connect gate="A" pin="GND_3" pad="A3"/>
<connect gate="A" pin="GND_4" pad="A5"/>
<connect gate="A" pin="GND_5" pad="A7"/>
<connect gate="A" pin="GND_6" pad="A9"/>
<connect gate="A" pin="GND_7" pad="B3"/>
<connect gate="A" pin="GND_8" pad="C3"/>
<connect gate="A" pin="GND_9" pad="C6"/>
<connect gate="A" pin="IO_0_35" pad="F4"/>
<connect gate="A" pin="IO_25_35" pad="L6"/>
<connect gate="A" pin="IO_L10N_T1_AD15N_35" pad="H5"/>
<connect gate="A" pin="IO_L10P_T1_AD15P_35" pad="J5"/>
<connect gate="A" pin="IO_L11N_T1_SRCC_35" pad="G3"/>
<connect gate="A" pin="IO_L11P_T1_SRCC_35" pad="H3"/>
<connect gate="A" pin="IO_L12N_T1_MRCC_35" pad="G4"/>
<connect gate="A" pin="IO_L12P_T1_MRCC_35" pad="H4"/>
<connect gate="A" pin="IO_L13N_T2_MRCC_35" pad="J4"/>
<connect gate="A" pin="IO_L13P_T2_MRCC_35" pad="K4"/>
<connect gate="A" pin="IO_L14N_T2_SRCC_35" pad="K3"/>
<connect gate="A" pin="IO_L14P_T2_SRCC_35" pad="L3"/>
<connect gate="A" pin="IO_L15N_T2_DQS_35" pad="L1"/>
<connect gate="A" pin="IO_L17N_T2_35" pad="J6"/>
<connect gate="A" pin="IO_L17P_T2_35" pad="K6"/>
<connect gate="A" pin="IO_L18N_T2_35" pad="L4"/>
<connect gate="A" pin="IO_L18P_T2_35" pad="L5"/>
<connect gate="A" pin="IO_L1N_T0_AD4N_35" pad="A1"/>
<connect gate="A" pin="IO_L1P_T0_AD4P_35" pad="B1"/>
<connect gate="A" pin="IO_L2N_T0_AD12N_35" pad="B2"/>
<connect gate="A" pin="IO_L2P_T0_AD12P_35" pad="C2"/>
<connect gate="A" pin="IO_L3N_T0_DQS_AD5N_35" pad="D1"/>
<connect gate="A" pin="IO_L3P_T0_DQS_AD5P_35" pad="E1"/>
<connect gate="A" pin="IO_L4N_T0_35" pad="D2"/>
<connect gate="A" pin="IO_L4P_T0_35" pad="E2"/>
<connect gate="A" pin="IO_L5N_T0_AD13N_35" pad="F1"/>
<connect gate="A" pin="IO_L5P_T0_AD13P_35" pad="G1"/>
<connect gate="A" pin="IO_L6N_T0_VREF_35" pad="E3"/>
<connect gate="A" pin="IO_L6P_T0_35" pad="F3"/>
<connect gate="A" pin="IO_L7N_T1_AD6N_35" pad="J1"/>
<connect gate="A" pin="IO_L7P_T1_AD6P_35" pad="K1"/>
<connect gate="A" pin="IO_L8N_T1_AD14N_35" pad="G2"/>
<connect gate="A" pin="IO_L8P_T1_AD14P_35" pad="H2"/>
<connect gate="A" pin="IO_L9N_T1_DQS_AD7N_35" pad="J2"/>
<connect gate="A" pin="IO_L9P_T1_DQS_AD7P_35" pad="K2"/>
<connect gate="A" pin="MGTAVCC" pad="F9"/>
<connect gate="A" pin="MGTAVCC_2" pad="D6"/>
<connect gate="A" pin="MGTAVCC_3" pad="E8"/>
<connect gate="A" pin="MGTAVCC_4" pad="F7"/>
<connect gate="A" pin="MGTAVTT" pad="C8"/>
<connect gate="A" pin="MGTAVTT_2" pad="B5"/>
<connect gate="A" pin="MGTAVTT_3" pad="B7"/>
<connect gate="A" pin="MGTAVTT_4" pad="B9"/>
<connect gate="A" pin="MGTAVTT_5" pad="C4"/>
<connect gate="A" pin="MGTPRXN0_216" pad="A8"/>
<connect gate="A" pin="MGTPRXN3_216" pad="C9"/>
<connect gate="A" pin="MGTPRXP0_216" pad="B8"/>
<connect gate="A" pin="MGTPRXP3_216" pad="D9"/>
<connect gate="A" pin="MGTPTXN0_216" pad="A4"/>
<connect gate="A" pin="MGTPTXN1_216" pad="C5"/>
<connect gate="A" pin="MGTPTXN2_216" pad="A6"/>
<connect gate="A" pin="MGTPTXN3_216" pad="C7"/>
<connect gate="A" pin="MGTPTXP0_216" pad="B4"/>
<connect gate="A" pin="MGTPTXP1_216" pad="D5"/>
<connect gate="A" pin="MGTPTXP2_216" pad="B6"/>
<connect gate="A" pin="MGTPTXP3_216" pad="D7"/>
<connect gate="A" pin="MGTREFCLK0N_216" pad="E6"/>
<connect gate="A" pin="MGTREFCLK0P_216" pad="F6"/>
<connect gate="A" pin="MGTRREF_216" pad="F8"/>
<connect gate="A" pin="VCCINT" pad="L7"/>
<connect gate="A" pin="VCCINT_2" pad="H8"/>
<connect gate="A" pin="VCCINT_3" pad="J7"/>
<connect gate="A" pin="VCCINT_4" pad="J9"/>
<connect gate="A" pin="VCCINT_5" pad="K8"/>
<connect gate="A" pin="VCCO_35" pad="J3"/>
<connect gate="A" pin="VCCO_35_2" pad="C1"/>
<connect gate="A" pin="VCCO_35_3" pad="F2"/>
<connect gate="A" pin="VCCO_35_4" pad="H6"/>
<connect gate="B" pin="CFGBVS_0" pad="U8"/>
<connect gate="B" pin="DXN_0" pad="N9"/>
<connect gate="B" pin="GND" pad="A22"/>
<connect gate="B" pin="GND_10" pad="T7"/>
<connect gate="B" pin="GND_11" pad="T9"/>
<connect gate="B" pin="GND_12" pad="U4"/>
<connect gate="B" pin="GND_13" pad="V1"/>
<connect gate="B" pin="GND_14" pad="W8"/>
<connect gate="B" pin="GND_15" pad="Y5"/>
<connect gate="B" pin="GND_16" pad="A11"/>
<connect gate="B" pin="GND_17" pad="A12"/>
<connect gate="B" pin="GND_2" pad="L8"/>
<connect gate="B" pin="GND_3" pad="M7"/>
<connect gate="B" pin="GND_4" pad="N6"/>
<connect gate="B" pin="GND_5" pad="N8"/>
<connect gate="B" pin="GND_6" pad="P3"/>
<connect gate="B" pin="GND_7" pad="P7"/>
<connect gate="B" pin="GND_8" pad="P9"/>
<connect gate="B" pin="GND_9" pad="R8"/>
<connect gate="B" pin="IO_0_34" pad="T3"/>
<connect gate="B" pin="IO_25_34" pad="U7"/>
<connect gate="B" pin="IO_L10N_T1_16" pad="A14"/>
<connect gate="B" pin="IO_L10P_T1_16" pad="A13"/>
<connect gate="B" pin="IO_L11P_T1_SRCC_34" pad="Y4"/>
<connect gate="B" pin="IO_L12N_T1_MRCC_34" pad="W4"/>
<connect gate="B" pin="IO_L12P_T1_MRCC_34" pad="V4"/>
<connect gate="B" pin="IO_L13N_T2_MRCC_34" pad="T4"/>
<connect gate="B" pin="IO_L13P_T2_MRCC_34" pad="R4"/>
<connect gate="B" pin="IO_L14N_T2_SRCC_34" pad="U5"/>
<connect gate="B" pin="IO_L14P_T2_SRCC_34" pad="T5"/>
<connect gate="B" pin="IO_L15N_T2_DQS_34" pad="W5"/>
<connect gate="B" pin="IO_L15P_T2_DQS_34" pad="W6"/>
<connect gate="B" pin="IO_L15P_T2_DQS_35" pad="M1"/>
<connect gate="B" pin="IO_L16N_T2_16" pad="A20"/>
<connect gate="B" pin="IO_L16N_T2_34" pad="V5"/>
<connect gate="B" pin="IO_L16N_T2_35" pad="M2"/>
<connect gate="B" pin="IO_L16P_T2_34" pad="U6"/>
<connect gate="B" pin="IO_L16P_T2_35" pad="M3"/>
<connect gate="B" pin="IO_L17N_T2_16" pad="A19"/>
<connect gate="B" pin="IO_L17N_T2_34" pad="T6"/>
<connect gate="B" pin="IO_L17P_T2_16" pad="A18"/>
<connect gate="B" pin="IO_L17P_T2_34" pad="R6"/>
<connect gate="B" pin="IO_L18P_T2_34" pad="Y6"/>
<connect gate="B" pin="IO_L19N_T3_VREF_34" pad="W7"/>
<connect gate="B" pin="IO_L19N_T3_VREF_35" pad="N3"/>
<connect gate="B" pin="IO_L19P_T3_34" pad="V7"/>
<connect gate="B" pin="IO_L19P_T3_35" pad="N4"/>
<connect gate="B" pin="IO_L1N_T0_34" pad="U1"/>
<connect gate="B" pin="IO_L1P_T0_34" pad="T1"/>
<connect gate="B" pin="IO_L20N_T3_35" pad="P1"/>
<connect gate="B" pin="IO_L20P_T3_35" pad="R1"/>
<connect gate="B" pin="IO_L21N_T3_DQS_16" pad="A21"/>
<connect gate="B" pin="IO_L21N_T3_DQS_34" pad="V8"/>
<connect gate="B" pin="IO_L21N_T3_DQS_35" pad="P4"/>
<connect gate="B" pin="IO_L21P_T3_DQS_34" pad="V9"/>
<connect gate="B" pin="IO_L21P_T3_DQS_35" pad="P5"/>
<connect gate="B" pin="IO_L22N_T3_35" pad="N2"/>
<connect gate="B" pin="IO_L22P_T3_35" pad="P2"/>
<connect gate="B" pin="IO_L23N_T3_34" pad="Y7"/>
<connect gate="B" pin="IO_L23N_T3_35" pad="M5"/>
<connect gate="B" pin="IO_L23P_T3_34" pad="Y8"/>
<connect gate="B" pin="IO_L23P_T3_35" pad="M6"/>
<connect gate="B" pin="IO_L24N_T3_34" pad="Y9"/>
<connect gate="B" pin="IO_L24N_T3_35" pad="N5"/>
<connect gate="B" pin="IO_L24P_T3_34" pad="W9"/>
<connect gate="B" pin="IO_L24P_T3_35" pad="P6"/>
<connect gate="B" pin="IO_L2N_T0_34" pad="V2"/>
<connect gate="B" pin="IO_L2P_T0_34" pad="U2"/>
<connect gate="B" pin="IO_L3N_T0_DQS_34" pad="R2"/>
<connect gate="B" pin="IO_L3P_T0_DQS_34" pad="R3"/>
<connect gate="B" pin="IO_L4N_T0_34" pad="Y2"/>
<connect gate="B" pin="IO_L4P_T0_34" pad="W2"/>
<connect gate="B" pin="IO_L5N_T0_34" pad="Y1"/>
<connect gate="B" pin="IO_L5P_T0_34" pad="W1"/>
<connect gate="B" pin="IO_L6N_T0_VREF_34" pad="V3"/>
<connect gate="B" pin="IO_L6P_T0_34" pad="U3"/>
<connect gate="B" pin="IO_L7P_T1_34" pad="AA1"/>
<connect gate="B" pin="IO_L9N_T1_DQS_16" pad="A16"/>
<connect gate="B" pin="IO_L9P_T1_DQS_16" pad="A15"/>
<connect gate="B" pin="IO_L9P_T1_DQS_34" pad="Y3"/>
<connect gate="B" pin="M2_0" pad="U9"/>
<connect gate="B" pin="MGTPRXN2_216" pad="A10"/>
<connect gate="B" pin="VCCINT" pad="T8"/>
<connect gate="B" pin="VCCINT_2" pad="M8"/>
<connect gate="B" pin="VCCINT_3" pad="N7"/>
<connect gate="B" pin="VCCINT_4" pad="P8"/>
<connect gate="B" pin="VCCINT_5" pad="R7"/>
<connect gate="B" pin="VCCINT_6" pad="R9"/>
<connect gate="B" pin="VCCO_16" pad="A17"/>
<connect gate="B" pin="VCCO_34" pad="W3"/>
<connect gate="B" pin="VCCO_34_2" pad="R5"/>
<connect gate="B" pin="VCCO_34_3" pad="T2"/>
<connect gate="B" pin="VCCO_34_4" pad="V6"/>
<connect gate="B" pin="VCCO_35" pad="N1"/>
<connect gate="B" pin="VCCO_35_2" pad="M4"/>
<connect gate="B" pin="VN_0" pad="M9"/>
<connect gate="B" pin="VREFN_0" pad="L9"/>
<connect gate="C" pin="DONE_0" pad="G11"/>
<connect gate="C" pin="GND" pad="H11"/>
<connect gate="C" pin="GND_10" pad="D13"/>
<connect gate="C" pin="GND_11" pad="E11"/>
<connect gate="C" pin="GND_12" pad="E20"/>
<connect gate="C" pin="GND_13" pad="F11"/>
<connect gate="C" pin="GND_14" pad="F17"/>
<connect gate="C" pin="GND_15" pad="G10"/>
<connect gate="C" pin="GND_16" pad="G12"/>
<connect gate="C" pin="GND_17" pad="G14"/>
<connect gate="C" pin="GND_2" pad="AA2"/>
<connect gate="C" pin="GND_3" pad="AB9"/>
<connect gate="C" pin="GND_4" pad="B12"/>
<connect gate="C" pin="GND_5" pad="B19"/>
<connect gate="C" pin="GND_6" pad="C10"/>
<connect gate="C" pin="GND_7" pad="C12"/>
<connect gate="C" pin="GND_8" pad="C16"/>
<connect gate="C" pin="GND_9" pad="D12"/>
<connect gate="C" pin="IO_0_16" pad="F15"/>
<connect gate="C" pin="IO_25_16" pad="F21"/>
<connect gate="C" pin="IO_L10N_T1_34" pad="AB5"/>
<connect gate="C" pin="IO_L10P_T1_34" pad="AA5"/>
<connect gate="C" pin="IO_L11N_T1_SRCC_16" pad="B18"/>
<connect gate="C" pin="IO_L11N_T1_SRCC_34" pad="AA4"/>
<connect gate="C" pin="IO_L11P_T1_SRCC_16" pad="B17"/>
<connect gate="C" pin="IO_L12N_T1_MRCC_16" pad="C17"/>
<connect gate="C" pin="IO_L12P_T1_MRCC_16" pad="D17"/>
<connect gate="C" pin="IO_L13N_T2_MRCC_16" pad="C19"/>
<connect gate="C" pin="IO_L13P_T2_MRCC_16" pad="C18"/>
<connect gate="C" pin="IO_L14N_T2_SRCC_16" pad="D19"/>
<connect gate="C" pin="IO_L14P_T2_SRCC_16" pad="E19"/>
<connect gate="C" pin="IO_L15N_T2_DQS_16" pad="E18"/>
<connect gate="C" pin="IO_L15P_T2_DQS_16" pad="F18"/>
<connect gate="C" pin="IO_L16P_T2_16" pad="B20"/>
<connect gate="C" pin="IO_L18N_T2_16" pad="F20"/>
<connect gate="C" pin="IO_L18N_T2_34" pad="AA6"/>
<connect gate="C" pin="IO_L18P_T2_16" pad="F19"/>
<connect gate="C" pin="IO_L19N_T3_VREF_16" pad="C20"/>
<connect gate="C" pin="IO_L19P_T3_16" pad="D20"/>
<connect gate="C" pin="IO_L1N_T0_16" pad="F14"/>
<connect gate="C" pin="IO_L1N_T0_AD0N_15" pad="G13"/>
<connect gate="C" pin="IO_L1P_T0_16" pad="F13"/>
<connect gate="C" pin="IO_L20N_T3_16" pad="B22"/>
<connect gate="C" pin="IO_L20N_T3_34" pad="AB6"/>
<connect gate="C" pin="IO_L20P_T3_16" pad="C22"/>
<connect gate="C" pin="IO_L20P_T3_34" pad="AB7"/>
<connect gate="C" pin="IO_L21P_T3_DQS_16" pad="B21"/>
<connect gate="C" pin="IO_L22N_T3_16" pad="D22"/>
<connect gate="C" pin="IO_L22N_T3_34" pad="AB8"/>
<connect gate="C" pin="IO_L22P_T3_16" pad="E22"/>
<connect gate="C" pin="IO_L22P_T3_34" pad="AA8"/>
<connect gate="C" pin="IO_L23N_T3_16" pad="D21"/>
<connect gate="C" pin="IO_L23P_T3_16" pad="E21"/>
<connect gate="C" pin="IO_L24N_T3_16" pad="G22"/>
<connect gate="C" pin="IO_L24P_T3_16" pad="G21"/>
<connect gate="C" pin="IO_L2N_T0_16" pad="E17"/>
<connect gate="C" pin="IO_L2N_T0_AD8N_15" pad="G16"/>
<connect gate="C" pin="IO_L2P_T0_16" pad="F16"/>
<connect gate="C" pin="IO_L2P_T0_AD8P_15" pad="G15"/>
<connect gate="C" pin="IO_L3N_T0_DQS_16" pad="C15"/>
<connect gate="C" pin="IO_L3P_T0_DQS_16" pad="C14"/>
<connect gate="C" pin="IO_L4N_T0_15" pad="G18"/>
<connect gate="C" pin="IO_L4N_T0_16" pad="E14"/>
<connect gate="C" pin="IO_L4P_T0_15" pad="G17"/>
<connect gate="C" pin="IO_L4P_T0_16" pad="E13"/>
<connect gate="C" pin="IO_L5N_T0_16" pad="D16"/>
<connect gate="C" pin="IO_L5P_T0_16" pad="E16"/>
<connect gate="C" pin="IO_L6N_T0_VREF_16" pad="D15"/>
<connect gate="C" pin="IO_L6P_T0_16" pad="D14"/>
<connect gate="C" pin="IO_L7N_T1_16" pad="B16"/>
<connect gate="C" pin="IO_L7N_T1_34" pad="AB1"/>
<connect gate="C" pin="IO_L7P_T1_16" pad="B15"/>
<connect gate="C" pin="IO_L8N_T1_16" pad="B13"/>
<connect gate="C" pin="IO_L8N_T1_34" pad="AB2"/>
<connect gate="C" pin="IO_L8N_T1_AD10N_15" pad="G20"/>
<connect gate="C" pin="IO_L8P_T1_13" pad="AA9"/>
<connect gate="C" pin="IO_L8P_T1_16" pad="C13"/>
<connect gate="C" pin="IO_L8P_T1_34" pad="AB3"/>
<connect gate="C" pin="IO_L9N_T1_DQS_34" pad="AA3"/>
<connect gate="C" pin="MGTAVCC" pad="D10"/>
<connect gate="C" pin="MGTAVTT" pad="B11"/>
<connect gate="C" pin="MGTPRXN1_216" pad="C11"/>
<connect gate="C" pin="MGTPRXP1_216" pad="D11"/>
<connect gate="C" pin="MGTPRXP2_216" pad="B10"/>
<connect gate="C" pin="MGTREFCLK1N_216" pad="E10"/>
<connect gate="C" pin="MGTREFCLK1P_216" pad="F10"/>
<connect gate="C" pin="VCCBATT_0" pad="E12"/>
<connect gate="C" pin="VCCINT" pad="H10"/>
<connect gate="C" pin="VCCO_0" pad="F12"/>
<connect gate="C" pin="VCCO_15" pad="G19"/>
<connect gate="C" pin="VCCO_16" pad="F22"/>
<connect gate="C" pin="VCCO_16_2" pad="B14"/>
<connect gate="C" pin="VCCO_16_3" pad="C21"/>
<connect gate="C" pin="VCCO_16_4" pad="D18"/>
<connect gate="C" pin="VCCO_16_5" pad="E15"/>
<connect gate="C" pin="VCCO_34" pad="AB4"/>
<connect gate="C" pin="VCCO_34_2" pad="AA7"/>
<connect gate="D" pin="CCLK_0" pad="L12"/>
<connect gate="D" pin="DXP_0" pad="N10"/>
<connect gate="D" pin="GND" pad="R12"/>
<connect gate="D" pin="GND_10" pad="M19"/>
<connect gate="D" pin="GND_11" pad="N16"/>
<connect gate="D" pin="GND_12" pad="P11"/>
<connect gate="D" pin="GND_13" pad="P13"/>
<connect gate="D" pin="GND_14" pad="R10"/>
<connect gate="D" pin="GND_2" pad="H21"/>
<connect gate="D" pin="GND_3" pad="J10"/>
<connect gate="D" pin="GND_4" pad="J12"/>
<connect gate="D" pin="GND_5" pad="J18"/>
<connect gate="D" pin="GND_6" pad="K11"/>
<connect gate="D" pin="GND_7" pad="K15"/>
<connect gate="D" pin="GND_8" pad="L22"/>
<connect gate="D" pin="GND_9" pad="M11"/>
<connect gate="D" pin="IO_0_14" pad="P20"/>
<connect gate="D" pin="IO_0_15" pad="J16"/>
<connect gate="D" pin="IO_25_14" pad="N15"/>
<connect gate="D" pin="IO_25_15" pad="M17"/>
<connect gate="D" pin="IO_L10N_T1_AD11N_15" pad="L21"/>
<connect gate="D" pin="IO_L10P_T1_AD11P_15" pad="M21"/>
<connect gate="D" pin="IO_L11N_T1_SRCC_15" pad="J21"/>
<connect gate="D" pin="IO_L11P_T1_SRCC_15" pad="J20"/>
<connect gate="D" pin="IO_L12N_T1_MRCC_15" pad="H19"/>
<connect gate="D" pin="IO_L12P_T1_MRCC_15" pad="J19"/>
<connect gate="D" pin="IO_L13N_T2_MRCC_15" pad="K19"/>
<connect gate="D" pin="IO_L13P_T2_MRCC_15" pad="K18"/>
<connect gate="D" pin="IO_L14N_T2_SRCC_15" pad="L20"/>
<connect gate="D" pin="IO_L14P_T2_SRCC_15" pad="L19"/>
<connect gate="D" pin="IO_L15N_T2_DQS_ADV_B_15" pad="M22"/>
<connect gate="D" pin="IO_L15P_T2_DQS_15" pad="N22"/>
<connect gate="D" pin="IO_L16N_T2_A27_15" pad="L18"/>
<connect gate="D" pin="IO_L16P_T2_A28_15" pad="M18"/>
<connect gate="D" pin="IO_L17N_T2_A25_15" pad="N19"/>
<connect gate="D" pin="IO_L17P_T2_A26_15" pad="N18"/>
<connect gate="D" pin="IO_L18N_T2_A23_15" pad="M20"/>
<connect gate="D" pin="IO_L18P_T2_A24_15" pad="N20"/>
<connect gate="D" pin="IO_L19N_T3_A09_D25_VREF_14" pad="R14"/>
<connect gate="D" pin="IO_L19N_T3_A21_VREF_15" pad="K14"/>
<connect gate="D" pin="IO_L19P_T3_A10_D26_14" pad="P14"/>
<connect gate="D" pin="IO_L19P_T3_A22_15" pad="K13"/>
<connect gate="D" pin="IO_L1P_T0_AD0P_15" pad="H13"/>
<connect gate="D" pin="IO_L1P_T0_D00_MOSI_14" pad="P22"/>
<connect gate="D" pin="IO_L20N_T3_A19_15" pad="L13"/>
<connect gate="D" pin="IO_L20P_T3_A20_15" pad="M13"/>
<connect gate="D" pin="IO_L21N_T3_DQS_A06_D22_14" pad="P17"/>
<connect gate="D" pin="IO_L21N_T3_DQS_A18_15" pad="J17"/>
<connect gate="D" pin="IO_L21P_T3_DQS_14" pad="N17"/>
<connect gate="D" pin="IO_L21P_T3_DQS_15" pad="K17"/>
<connect gate="D" pin="IO_L22N_T3_A04_D20_14" pad="R16"/>
<connect gate="D" pin="IO_L22N_T3_A16_15" pad="L15"/>
<connect gate="D" pin="IO_L22P_T3_A05_D21_14" pad="P15"/>
<connect gate="D" pin="IO_L22P_T3_A17_15" pad="L14"/>
<connect gate="D" pin="IO_L23N_T3_A02_D18_14" pad="N14"/>
<connect gate="D" pin="IO_L23N_T3_FWE_B_15" pad="K16"/>
<connect gate="D" pin="IO_L23P_T3_A03_D19_14" pad="N13"/>
<connect gate="D" pin="IO_L23P_T3_FOE_B_15" pad="L16"/>
<connect gate="D" pin="IO_L24N_T3_A00_D16_14" pad="R17"/>
<connect gate="D" pin="IO_L24N_T3_RS0_15" pad="M16"/>
<connect gate="D" pin="IO_L24P_T3_A01_D17_14" pad="P16"/>
<connect gate="D" pin="IO_L24P_T3_RS1_15" pad="M15"/>
<connect gate="D" pin="IO_L2P_T0_D02_14" pad="P21"/>
<connect gate="D" pin="IO_L3N_T0_DQS_AD1N_15" pad="H14"/>
<connect gate="D" pin="IO_L3P_T0_DQS_AD1P_15" pad="J14"/>
<connect gate="D" pin="IO_L5N_T0_AD9N_15" pad="H15"/>
<connect gate="D" pin="IO_L5P_T0_AD9P_15" pad="J15"/>
<connect gate="D" pin="IO_L5P_T0_D06_14" pad="P19"/>
<connect gate="D" pin="IO_L6N_T0_VREF_15" pad="H18"/>
<connect gate="D" pin="IO_L6P_T0_15" pad="H17"/>
<connect gate="D" pin="IO_L7N_T1_AD2N_15" pad="H22"/>
<connect gate="D" pin="IO_L7P_T1_AD2P_15" pad="J22"/>
<connect gate="D" pin="IO_L8P_T1_AD10P_15" pad="H20"/>
<connect gate="D" pin="IO_L9N_T1_DQS_AD3N_15" pad="K22"/>
<connect gate="D" pin="IO_L9P_T1_DQS_AD3P_15" pad="K21"/>
<connect gate="D" pin="PROGRAM_B_0" pad="N12"/>
<connect gate="D" pin="TDI_0" pad="R13"/>
<connect gate="D" pin="VCCADC_0" pad="K10"/>
<connect gate="D" pin="VCCAUX" pad="R11"/>
<connect gate="D" pin="VCCAUX_2" pad="H12"/>
<connect gate="D" pin="VCCAUX_3" pad="K12"/>
<connect gate="D" pin="VCCAUX_4" pad="M12"/>
<connect gate="D" pin="VCCAUX_5" pad="P12"/>
<connect gate="D" pin="VCCBRAM" pad="N11"/>
<connect gate="D" pin="VCCBRAM_2" pad="J11"/>
<connect gate="D" pin="VCCBRAM_3" pad="L11"/>
<connect gate="D" pin="VCCINT" pad="P10"/>
<connect gate="D" pin="VCCO_14" pad="R15"/>
<connect gate="D" pin="VCCO_14_2" pad="M14"/>
<connect gate="D" pin="VCCO_14_3" pad="P18"/>
<connect gate="D" pin="VCCO_15" pad="N21"/>
<connect gate="D" pin="VCCO_15_2" pad="H16"/>
<connect gate="D" pin="VCCO_15_3" pad="J13"/>
<connect gate="D" pin="VCCO_15_4" pad="K20"/>
<connect gate="D" pin="VCCO_15_5" pad="L17"/>
<connect gate="D" pin="VP_0" pad="L10"/>
<connect gate="D" pin="VREFP_0" pad="M10"/>
<connect gate="E" pin="GND" pad="AB19"/>
<connect gate="E" pin="GND_10" pad="AA12"/>
<connect gate="E" pin="GND_11" pad="AA22"/>
<connect gate="E" pin="GND_2" pad="R20"/>
<connect gate="E" pin="GND_3" pad="T11"/>
<connect gate="E" pin="GND_4" pad="T17"/>
<connect gate="E" pin="GND_5" pad="U14"/>
<connect gate="E" pin="GND_6" pad="V11"/>
<connect gate="E" pin="GND_7" pad="V21"/>
<connect gate="E" pin="GND_8" pad="W18"/>
<connect gate="E" pin="GND_9" pad="Y15"/>
<connect gate="E" pin="INIT_B_0" pad="U12"/>
<connect gate="E" pin="IO_0_13" pad="Y17"/>
<connect gate="E" pin="IO_L10N_T1_13" pad="W10"/>
<connect gate="E" pin="IO_L10N_T1_D15_14" pad="AB22"/>
<connect gate="E" pin="IO_L10P_T1_13" pad="V10"/>
<connect gate="E" pin="IO_L10P_T1_D14_14" pad="AB21"/>
<connect gate="E" pin="IO_L11N_T1_SRCC_13" pad="Y12"/>
<connect gate="E" pin="IO_L11N_T1_SRCC_14" pad="V20"/>
<connect gate="E" pin="IO_L11P_T1_SRCC_13" pad="Y11"/>
<connect gate="E" pin="IO_L11P_T1_SRCC_14" pad="U20"/>
<connect gate="E" pin="IO_L12N_T1_MRCC_13" pad="W12"/>
<connect gate="E" pin="IO_L12N_T1_MRCC_14" pad="W20"/>
<connect gate="E" pin="IO_L12P_T1_MRCC_13" pad="W11"/>
<connect gate="E" pin="IO_L12P_T1_MRCC_14" pad="W19"/>
<connect gate="E" pin="IO_L13N_T2_MRCC_13" pad="V14"/>
<connect gate="E" pin="IO_L13N_T2_MRCC_14" pad="Y19"/>
<connect gate="E" pin="IO_L13P_T2_MRCC_13" pad="V13"/>
<connect gate="E" pin="IO_L13P_T2_MRCC_14" pad="Y18"/>
<connect gate="E" pin="IO_L14N_T2_SRCC_13" pad="V15"/>
<connect gate="E" pin="IO_L14N_T2_SRCC_14" pad="V19"/>
<connect gate="E" pin="IO_L14P_T2_SRCC_13" pad="U15"/>
<connect gate="E" pin="IO_L14P_T2_SRCC_14" pad="V18"/>
<connect gate="E" pin="IO_L15N_T2_DQS_13" pad="T15"/>
<connect gate="E" pin="IO_L15N_T2_DQS_DOUT_CSO_B_14" pad="AB20"/>
<connect gate="E" pin="IO_L15P_T2_DQS_13" pad="T14"/>
<connect gate="E" pin="IO_L15P_T2_DQS_RDWR_B_14" pad="AA19"/>
<connect gate="E" pin="IO_L16N_T2_13" pad="W16"/>
<connect gate="E" pin="IO_L16N_T2_A15_D31_14" pad="W17"/>
<connect gate="E" pin="IO_L16P_T2_13" pad="W15"/>
<connect gate="E" pin="IO_L16P_T2_CSI_B_14" pad="V17"/>
<connect gate="E" pin="IO_L17N_T2_13" pad="U16"/>
<connect gate="E" pin="IO_L17N_T2_A13_D29_14" pad="AB18"/>
<connect gate="E" pin="IO_L17P_T2_13" pad="T16"/>
<connect gate="E" pin="IO_L17P_T2_A14_D30_14" pad="AA18"/>
<connect gate="E" pin="IO_L18N_T2_A11_D27_14" pad="U18"/>
<connect gate="E" pin="IO_L18P_T2_A12_D28_14" pad="U17"/>
<connect gate="E" pin="IO_L1N_T0_13" pad="AA16"/>
<connect gate="E" pin="IO_L1N_T0_D01_DIN_14" pad="R22"/>
<connect gate="E" pin="IO_L1P_T0_13" pad="Y16"/>
<connect gate="E" pin="IO_L20N_T3_A07_D23_14" pad="T18"/>
<connect gate="E" pin="IO_L20P_T3_A08_D24_14" pad="R18"/>
<connect gate="E" pin="IO_L2N_T0_13" pad="AB17"/>
<connect gate="E" pin="IO_L2N_T0_D03_14" pad="R21"/>
<connect gate="E" pin="IO_L2P_T0_13" pad="AB16"/>
<connect gate="E" pin="IO_L3N_T0_DQS_13" pad="AB13"/>
<connect gate="E" pin="IO_L3N_T0_DQS_EMCCLK_14" pad="V22"/>
<connect gate="E" pin="IO_L3P_T0_DQS_13" pad="AA13"/>
<connect gate="E" pin="IO_L3P_T0_DQS_PUDC_B_14" pad="U22"/>
<connect gate="E" pin="IO_L4N_T0_13" pad="AB15"/>
<connect gate="E" pin="IO_L4N_T0_D05_14" pad="U21"/>
<connect gate="E" pin="IO_L4P_T0_13" pad="AA15"/>
<connect gate="E" pin="IO_L4P_T0_D04_14" pad="T21"/>
<connect gate="E" pin="IO_L5N_T0_13" pad="AA14"/>
<connect gate="E" pin="IO_L5N_T0_D07_14" pad="R19"/>
<connect gate="E" pin="IO_L5P_T0_13" pad="Y13"/>
<connect gate="E" pin="IO_L6N_T0_D08_VREF_14" pad="T20"/>
<connect gate="E" pin="IO_L6N_T0_VREF_13" pad="Y14"/>
<connect gate="E" pin="IO_L6P_T0_13" pad="W14"/>
<connect gate="E" pin="IO_L6P_T0_FCS_B_14" pad="T19"/>
<connect gate="E" pin="IO_L7N_T1_13" pad="AB12"/>
<connect gate="E" pin="IO_L7N_T1_D10_14" pad="W22"/>
<connect gate="E" pin="IO_L7P_T1_13" pad="AB11"/>
<connect gate="E" pin="IO_L7P_T1_D09_14" pad="W21"/>
<connect gate="E" pin="IO_L8N_T1_13" pad="AB10"/>
<connect gate="E" pin="IO_L8N_T1_D12_14" pad="AA21"/>
<connect gate="E" pin="IO_L8P_T1_D11_14" pad="AA20"/>
<connect gate="E" pin="IO_L9N_T1_DQS_13" pad="AA11"/>
<connect gate="E" pin="IO_L9N_T1_DQS_D13_14" pad="Y22"/>
<connect gate="E" pin="IO_L9P_T1_DQS_13" pad="AA10"/>
<connect gate="E" pin="IO_L9P_T1_DQS_14" pad="Y21"/>
<connect gate="E" pin="M0_0" pad="U11"/>
<connect gate="E" pin="M1_0" pad="U10"/>
<connect gate="E" pin="TCK_0" pad="V12"/>
<connect gate="E" pin="TDO_0" pad="U13"/>
<connect gate="E" pin="TMS_0" pad="T13"/>
<connect gate="E" pin="VCCINT" pad="T10"/>
<connect gate="E" pin="VCCO_0" pad="T12"/>
<connect gate="E" pin="VCCO_13" pad="AB14"/>
<connect gate="E" pin="VCCO_13_2" pad="V16"/>
<connect gate="E" pin="VCCO_13_3" pad="W13"/>
<connect gate="E" pin="VCCO_13_4" pad="Y10"/>
<connect gate="E" pin="VCCO_13_5" pad="AA17"/>
<connect gate="E" pin="VCCO_14" pad="Y20"/>
<connect gate="E" pin="VCCO_14_2" pad="T22"/>
<connect gate="E" pin="VCCO_14_3" pad="U19"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="XC7A100T-2FGG484I"/>
<attribute name="MFR_NAME" value="Xilinx Inc"/>
</technology>
</technologies>
</device>
<device name="FGG484(ARTIX-7)_XIL-M" package="FGG484(ARTIX-7)_XIL-M">
<connects>
<connect gate="A" pin="GND" pad="L2"/>
<connect gate="A" pin="GNDADC_0" pad="K9"/>
<connect gate="A" pin="GND_10" pad="D3"/>
<connect gate="A" pin="GND_11" pad="D4"/>
<connect gate="A" pin="GND_12" pad="D8"/>
<connect gate="A" pin="GND_13" pad="E4"/>
<connect gate="A" pin="GND_14" pad="E5"/>
<connect gate="A" pin="GND_15" pad="E7"/>
<connect gate="A" pin="GND_16" pad="E9"/>
<connect gate="A" pin="GND_17" pad="F5"/>
<connect gate="A" pin="GND_18" pad="G5"/>
<connect gate="A" pin="GND_19" pad="G6"/>
<connect gate="A" pin="GND_2" pad="A2"/>
<connect gate="A" pin="GND_20" pad="G7"/>
<connect gate="A" pin="GND_21" pad="G8"/>
<connect gate="A" pin="GND_22" pad="G9"/>
<connect gate="A" pin="GND_23" pad="H1"/>
<connect gate="A" pin="GND_24" pad="H7"/>
<connect gate="A" pin="GND_25" pad="H9"/>
<connect gate="A" pin="GND_26" pad="J8"/>
<connect gate="A" pin="GND_27" pad="K5"/>
<connect gate="A" pin="GND_28" pad="K7"/>
<connect gate="A" pin="GND_3" pad="A3"/>
<connect gate="A" pin="GND_4" pad="A5"/>
<connect gate="A" pin="GND_5" pad="A7"/>
<connect gate="A" pin="GND_6" pad="A9"/>
<connect gate="A" pin="GND_7" pad="B3"/>
<connect gate="A" pin="GND_8" pad="C3"/>
<connect gate="A" pin="GND_9" pad="C6"/>
<connect gate="A" pin="IO_0_35" pad="F4"/>
<connect gate="A" pin="IO_25_35" pad="L6"/>
<connect gate="A" pin="IO_L10N_T1_AD15N_35" pad="H5"/>
<connect gate="A" pin="IO_L10P_T1_AD15P_35" pad="J5"/>
<connect gate="A" pin="IO_L11N_T1_SRCC_35" pad="G3"/>
<connect gate="A" pin="IO_L11P_T1_SRCC_35" pad="H3"/>
<connect gate="A" pin="IO_L12N_T1_MRCC_35" pad="G4"/>
<connect gate="A" pin="IO_L12P_T1_MRCC_35" pad="H4"/>
<connect gate="A" pin="IO_L13N_T2_MRCC_35" pad="J4"/>
<connect gate="A" pin="IO_L13P_T2_MRCC_35" pad="K4"/>
<connect gate="A" pin="IO_L14N_T2_SRCC_35" pad="K3"/>
<connect gate="A" pin="IO_L14P_T2_SRCC_35" pad="L3"/>
<connect gate="A" pin="IO_L15N_T2_DQS_35" pad="L1"/>
<connect gate="A" pin="IO_L17N_T2_35" pad="J6"/>
<connect gate="A" pin="IO_L17P_T2_35" pad="K6"/>
<connect gate="A" pin="IO_L18N_T2_35" pad="L4"/>
<connect gate="A" pin="IO_L18P_T2_35" pad="L5"/>
<connect gate="A" pin="IO_L1N_T0_AD4N_35" pad="A1"/>
<connect gate="A" pin="IO_L1P_T0_AD4P_35" pad="B1"/>
<connect gate="A" pin="IO_L2N_T0_AD12N_35" pad="B2"/>
<connect gate="A" pin="IO_L2P_T0_AD12P_35" pad="C2"/>
<connect gate="A" pin="IO_L3N_T0_DQS_AD5N_35" pad="D1"/>
<connect gate="A" pin="IO_L3P_T0_DQS_AD5P_35" pad="E1"/>
<connect gate="A" pin="IO_L4N_T0_35" pad="D2"/>
<connect gate="A" pin="IO_L4P_T0_35" pad="E2"/>
<connect gate="A" pin="IO_L5N_T0_AD13N_35" pad="F1"/>
<connect gate="A" pin="IO_L5P_T0_AD13P_35" pad="G1"/>
<connect gate="A" pin="IO_L6N_T0_VREF_35" pad="E3"/>
<connect gate="A" pin="IO_L6P_T0_35" pad="F3"/>
<connect gate="A" pin="IO_L7N_T1_AD6N_35" pad="J1"/>
<connect gate="A" pin="IO_L7P_T1_AD6P_35" pad="K1"/>
<connect gate="A" pin="IO_L8N_T1_AD14N_35" pad="G2"/>
<connect gate="A" pin="IO_L8P_T1_AD14P_35" pad="H2"/>
<connect gate="A" pin="IO_L9N_T1_DQS_AD7N_35" pad="J2"/>
<connect gate="A" pin="IO_L9P_T1_DQS_AD7P_35" pad="K2"/>
<connect gate="A" pin="MGTAVCC" pad="F9"/>
<connect gate="A" pin="MGTAVCC_2" pad="D6"/>
<connect gate="A" pin="MGTAVCC_3" pad="E8"/>
<connect gate="A" pin="MGTAVCC_4" pad="F7"/>
<connect gate="A" pin="MGTAVTT" pad="C8"/>
<connect gate="A" pin="MGTAVTT_2" pad="B5"/>
<connect gate="A" pin="MGTAVTT_3" pad="B7"/>
<connect gate="A" pin="MGTAVTT_4" pad="B9"/>
<connect gate="A" pin="MGTAVTT_5" pad="C4"/>
<connect gate="A" pin="MGTPRXN0_216" pad="A8"/>
<connect gate="A" pin="MGTPRXN3_216" pad="C9"/>
<connect gate="A" pin="MGTPRXP0_216" pad="B8"/>
<connect gate="A" pin="MGTPRXP3_216" pad="D9"/>
<connect gate="A" pin="MGTPTXN0_216" pad="A4"/>
<connect gate="A" pin="MGTPTXN1_216" pad="C5"/>
<connect gate="A" pin="MGTPTXN2_216" pad="A6"/>
<connect gate="A" pin="MGTPTXN3_216" pad="C7"/>
<connect gate="A" pin="MGTPTXP0_216" pad="B4"/>
<connect gate="A" pin="MGTPTXP1_216" pad="D5"/>
<connect gate="A" pin="MGTPTXP2_216" pad="B6"/>
<connect gate="A" pin="MGTPTXP3_216" pad="D7"/>
<connect gate="A" pin="MGTREFCLK0N_216" pad="E6"/>
<connect gate="A" pin="MGTREFCLK0P_216" pad="F6"/>
<connect gate="A" pin="MGTRREF_216" pad="F8"/>
<connect gate="A" pin="VCCINT" pad="L7"/>
<connect gate="A" pin="VCCINT_2" pad="H8"/>
<connect gate="A" pin="VCCINT_3" pad="J7"/>
<connect gate="A" pin="VCCINT_4" pad="J9"/>
<connect gate="A" pin="VCCINT_5" pad="K8"/>
<connect gate="A" pin="VCCO_35" pad="J3"/>
<connect gate="A" pin="VCCO_35_2" pad="C1"/>
<connect gate="A" pin="VCCO_35_3" pad="F2"/>
<connect gate="A" pin="VCCO_35_4" pad="H6"/>
<connect gate="B" pin="CFGBVS_0" pad="U8"/>
<connect gate="B" pin="DXN_0" pad="N9"/>
<connect gate="B" pin="GND" pad="A22"/>
<connect gate="B" pin="GND_10" pad="T7"/>
<connect gate="B" pin="GND_11" pad="T9"/>
<connect gate="B" pin="GND_12" pad="U4"/>
<connect gate="B" pin="GND_13" pad="V1"/>
<connect gate="B" pin="GND_14" pad="W8"/>
<connect gate="B" pin="GND_15" pad="Y5"/>
<connect gate="B" pin="GND_16" pad="A11"/>
<connect gate="B" pin="GND_17" pad="A12"/>
<connect gate="B" pin="GND_2" pad="L8"/>
<connect gate="B" pin="GND_3" pad="M7"/>
<connect gate="B" pin="GND_4" pad="N6"/>
<connect gate="B" pin="GND_5" pad="N8"/>
<connect gate="B" pin="GND_6" pad="P3"/>
<connect gate="B" pin="GND_7" pad="P7"/>
<connect gate="B" pin="GND_8" pad="P9"/>
<connect gate="B" pin="GND_9" pad="R8"/>
<connect gate="B" pin="IO_0_34" pad="T3"/>
<connect gate="B" pin="IO_25_34" pad="U7"/>
<connect gate="B" pin="IO_L10N_T1_16" pad="A14"/>
<connect gate="B" pin="IO_L10P_T1_16" pad="A13"/>
<connect gate="B" pin="IO_L11P_T1_SRCC_34" pad="Y4"/>
<connect gate="B" pin="IO_L12N_T1_MRCC_34" pad="W4"/>
<connect gate="B" pin="IO_L12P_T1_MRCC_34" pad="V4"/>
<connect gate="B" pin="IO_L13N_T2_MRCC_34" pad="T4"/>
<connect gate="B" pin="IO_L13P_T2_MRCC_34" pad="R4"/>
<connect gate="B" pin="IO_L14N_T2_SRCC_34" pad="U5"/>
<connect gate="B" pin="IO_L14P_T2_SRCC_34" pad="T5"/>
<connect gate="B" pin="IO_L15N_T2_DQS_34" pad="W5"/>
<connect gate="B" pin="IO_L15P_T2_DQS_34" pad="W6"/>
<connect gate="B" pin="IO_L15P_T2_DQS_35" pad="M1"/>
<connect gate="B" pin="IO_L16N_T2_16" pad="A20"/>
<connect gate="B" pin="IO_L16N_T2_34" pad="V5"/>
<connect gate="B" pin="IO_L16N_T2_35" pad="M2"/>
<connect gate="B" pin="IO_L16P_T2_34" pad="U6"/>
<connect gate="B" pin="IO_L16P_T2_35" pad="M3"/>
<connect gate="B" pin="IO_L17N_T2_16" pad="A19"/>
<connect gate="B" pin="IO_L17N_T2_34" pad="T6"/>
<connect gate="B" pin="IO_L17P_T2_16" pad="A18"/>
<connect gate="B" pin="IO_L17P_T2_34" pad="R6"/>
<connect gate="B" pin="IO_L18P_T2_34" pad="Y6"/>
<connect gate="B" pin="IO_L19N_T3_VREF_34" pad="W7"/>
<connect gate="B" pin="IO_L19N_T3_VREF_35" pad="N3"/>
<connect gate="B" pin="IO_L19P_T3_34" pad="V7"/>
<connect gate="B" pin="IO_L19P_T3_35" pad="N4"/>
<connect gate="B" pin="IO_L1N_T0_34" pad="U1"/>
<connect gate="B" pin="IO_L1P_T0_34" pad="T1"/>
<connect gate="B" pin="IO_L20N_T3_35" pad="P1"/>
<connect gate="B" pin="IO_L20P_T3_35" pad="R1"/>
<connect gate="B" pin="IO_L21N_T3_DQS_16" pad="A21"/>
<connect gate="B" pin="IO_L21N_T3_DQS_34" pad="V8"/>
<connect gate="B" pin="IO_L21N_T3_DQS_35" pad="P4"/>
<connect gate="B" pin="IO_L21P_T3_DQS_34" pad="V9"/>
<connect gate="B" pin="IO_L21P_T3_DQS_35" pad="P5"/>
<connect gate="B" pin="IO_L22N_T3_35" pad="N2"/>
<connect gate="B" pin="IO_L22P_T3_35" pad="P2"/>
<connect gate="B" pin="IO_L23N_T3_34" pad="Y7"/>
<connect gate="B" pin="IO_L23N_T3_35" pad="M5"/>
<connect gate="B" pin="IO_L23P_T3_34" pad="Y8"/>
<connect gate="B" pin="IO_L23P_T3_35" pad="M6"/>
<connect gate="B" pin="IO_L24N_T3_34" pad="Y9"/>
<connect gate="B" pin="IO_L24N_T3_35" pad="N5"/>
<connect gate="B" pin="IO_L24P_T3_34" pad="W9"/>
<connect gate="B" pin="IO_L24P_T3_35" pad="P6"/>
<connect gate="B" pin="IO_L2N_T0_34" pad="V2"/>
<connect gate="B" pin="IO_L2P_T0_34" pad="U2"/>
<connect gate="B" pin="IO_L3N_T0_DQS_34" pad="R2"/>
<connect gate="B" pin="IO_L3P_T0_DQS_34" pad="R3"/>
<connect gate="B" pin="IO_L4N_T0_34" pad="Y2"/>
<connect gate="B" pin="IO_L4P_T0_34" pad="W2"/>
<connect gate="B" pin="IO_L5N_T0_34" pad="Y1"/>
<connect gate="B" pin="IO_L5P_T0_34" pad="W1"/>
<connect gate="B" pin="IO_L6N_T0_VREF_34" pad="V3"/>
<connect gate="B" pin="IO_L6P_T0_34" pad="U3"/>
<connect gate="B" pin="IO_L7P_T1_34" pad="AA1"/>
<connect gate="B" pin="IO_L9N_T1_DQS_16" pad="A16"/>
<connect gate="B" pin="IO_L9P_T1_DQS_16" pad="A15"/>
<connect gate="B" pin="IO_L9P_T1_DQS_34" pad="Y3"/>
<connect gate="B" pin="M2_0" pad="U9"/>
<connect gate="B" pin="MGTPRXN2_216" pad="A10"/>
<connect gate="B" pin="VCCINT" pad="T8"/>
<connect gate="B" pin="VCCINT_2" pad="M8"/>
<connect gate="B" pin="VCCINT_3" pad="N7"/>
<connect gate="B" pin="VCCINT_4" pad="P8"/>
<connect gate="B" pin="VCCINT_5" pad="R7"/>
<connect gate="B" pin="VCCINT_6" pad="R9"/>
<connect gate="B" pin="VCCO_16" pad="A17"/>
<connect gate="B" pin="VCCO_34" pad="W3"/>
<connect gate="B" pin="VCCO_34_2" pad="R5"/>
<connect gate="B" pin="VCCO_34_3" pad="T2"/>
<connect gate="B" pin="VCCO_34_4" pad="V6"/>
<connect gate="B" pin="VCCO_35" pad="N1"/>
<connect gate="B" pin="VCCO_35_2" pad="M4"/>
<connect gate="B" pin="VN_0" pad="M9"/>
<connect gate="B" pin="VREFN_0" pad="L9"/>
<connect gate="C" pin="DONE_0" pad="G11"/>
<connect gate="C" pin="GND" pad="H11"/>
<connect gate="C" pin="GND_10" pad="D13"/>
<connect gate="C" pin="GND_11" pad="E11"/>
<connect gate="C" pin="GND_12" pad="E20"/>
<connect gate="C" pin="GND_13" pad="F11"/>
<connect gate="C" pin="GND_14" pad="F17"/>
<connect gate="C" pin="GND_15" pad="G10"/>
<connect gate="C" pin="GND_16" pad="G12"/>
<connect gate="C" pin="GND_17" pad="G14"/>
<connect gate="C" pin="GND_2" pad="AA2"/>
<connect gate="C" pin="GND_3" pad="AB9"/>
<connect gate="C" pin="GND_4" pad="B12"/>
<connect gate="C" pin="GND_5" pad="B19"/>
<connect gate="C" pin="GND_6" pad="C10"/>
<connect gate="C" pin="GND_7" pad="C12"/>
<connect gate="C" pin="GND_8" pad="C16"/>
<connect gate="C" pin="GND_9" pad="D12"/>
<connect gate="C" pin="IO_0_16" pad="F15"/>
<connect gate="C" pin="IO_25_16" pad="F21"/>
<connect gate="C" pin="IO_L10N_T1_34" pad="AB5"/>
<connect gate="C" pin="IO_L10P_T1_34" pad="AA5"/>
<connect gate="C" pin="IO_L11N_T1_SRCC_16" pad="B18"/>
<connect gate="C" pin="IO_L11N_T1_SRCC_34" pad="AA4"/>
<connect gate="C" pin="IO_L11P_T1_SRCC_16" pad="B17"/>
<connect gate="C" pin="IO_L12N_T1_MRCC_16" pad="C17"/>
<connect gate="C" pin="IO_L12P_T1_MRCC_16" pad="D17"/>
<connect gate="C" pin="IO_L13N_T2_MRCC_16" pad="C19"/>
<connect gate="C" pin="IO_L13P_T2_MRCC_16" pad="C18"/>
<connect gate="C" pin="IO_L14N_T2_SRCC_16" pad="D19"/>
<connect gate="C" pin="IO_L14P_T2_SRCC_16" pad="E19"/>
<connect gate="C" pin="IO_L15N_T2_DQS_16" pad="E18"/>
<connect gate="C" pin="IO_L15P_T2_DQS_16" pad="F18"/>
<connect gate="C" pin="IO_L16P_T2_16" pad="B20"/>
<connect gate="C" pin="IO_L18N_T2_16" pad="F20"/>
<connect gate="C" pin="IO_L18N_T2_34" pad="AA6"/>
<connect gate="C" pin="IO_L18P_T2_16" pad="F19"/>
<connect gate="C" pin="IO_L19N_T3_VREF_16" pad="C20"/>
<connect gate="C" pin="IO_L19P_T3_16" pad="D20"/>
<connect gate="C" pin="IO_L1N_T0_16" pad="F14"/>
<connect gate="C" pin="IO_L1N_T0_AD0N_15" pad="G13"/>
<connect gate="C" pin="IO_L1P_T0_16" pad="F13"/>
<connect gate="C" pin="IO_L20N_T3_16" pad="B22"/>
<connect gate="C" pin="IO_L20N_T3_34" pad="AB6"/>
<connect gate="C" pin="IO_L20P_T3_16" pad="C22"/>
<connect gate="C" pin="IO_L20P_T3_34" pad="AB7"/>
<connect gate="C" pin="IO_L21P_T3_DQS_16" pad="B21"/>
<connect gate="C" pin="IO_L22N_T3_16" pad="D22"/>
<connect gate="C" pin="IO_L22N_T3_34" pad="AB8"/>
<connect gate="C" pin="IO_L22P_T3_16" pad="E22"/>
<connect gate="C" pin="IO_L22P_T3_34" pad="AA8"/>
<connect gate="C" pin="IO_L23N_T3_16" pad="D21"/>
<connect gate="C" pin="IO_L23P_T3_16" pad="E21"/>
<connect gate="C" pin="IO_L24N_T3_16" pad="G22"/>
<connect gate="C" pin="IO_L24P_T3_16" pad="G21"/>
<connect gate="C" pin="IO_L2N_T0_16" pad="E17"/>
<connect gate="C" pin="IO_L2N_T0_AD8N_15" pad="G16"/>
<connect gate="C" pin="IO_L2P_T0_16" pad="F16"/>
<connect gate="C" pin="IO_L2P_T0_AD8P_15" pad="G15"/>
<connect gate="C" pin="IO_L3N_T0_DQS_16" pad="C15"/>
<connect gate="C" pin="IO_L3P_T0_DQS_16" pad="C14"/>
<connect gate="C" pin="IO_L4N_T0_15" pad="G18"/>
<connect gate="C" pin="IO_L4N_T0_16" pad="E14"/>
<connect gate="C" pin="IO_L4P_T0_15" pad="G17"/>
<connect gate="C" pin="IO_L4P_T0_16" pad="E13"/>
<connect gate="C" pin="IO_L5N_T0_16" pad="D16"/>
<connect gate="C" pin="IO_L5P_T0_16" pad="E16"/>
<connect gate="C" pin="IO_L6N_T0_VREF_16" pad="D15"/>
<connect gate="C" pin="IO_L6P_T0_16" pad="D14"/>
<connect gate="C" pin="IO_L7N_T1_16" pad="B16"/>
<connect gate="C" pin="IO_L7N_T1_34" pad="AB1"/>
<connect gate="C" pin="IO_L7P_T1_16" pad="B15"/>
<connect gate="C" pin="IO_L8N_T1_16" pad="B13"/>
<connect gate="C" pin="IO_L8N_T1_34" pad="AB2"/>
<connect gate="C" pin="IO_L8N_T1_AD10N_15" pad="G20"/>
<connect gate="C" pin="IO_L8P_T1_13" pad="AA9"/>
<connect gate="C" pin="IO_L8P_T1_16" pad="C13"/>
<connect gate="C" pin="IO_L8P_T1_34" pad="AB3"/>
<connect gate="C" pin="IO_L9N_T1_DQS_34" pad="AA3"/>
<connect gate="C" pin="MGTAVCC" pad="D10"/>
<connect gate="C" pin="MGTAVTT" pad="B11"/>
<connect gate="C" pin="MGTPRXN1_216" pad="C11"/>
<connect gate="C" pin="MGTPRXP1_216" pad="D11"/>
<connect gate="C" pin="MGTPRXP2_216" pad="B10"/>
<connect gate="C" pin="MGTREFCLK1N_216" pad="E10"/>
<connect gate="C" pin="MGTREFCLK1P_216" pad="F10"/>
<connect gate="C" pin="VCCBATT_0" pad="E12"/>
<connect gate="C" pin="VCCINT" pad="H10"/>
<connect gate="C" pin="VCCO_0" pad="F12"/>
<connect gate="C" pin="VCCO_15" pad="G19"/>
<connect gate="C" pin="VCCO_16" pad="F22"/>
<connect gate="C" pin="VCCO_16_2" pad="B14"/>
<connect gate="C" pin="VCCO_16_3" pad="C21"/>
<connect gate="C" pin="VCCO_16_4" pad="D18"/>
<connect gate="C" pin="VCCO_16_5" pad="E15"/>
<connect gate="C" pin="VCCO_34" pad="AB4"/>
<connect gate="C" pin="VCCO_34_2" pad="AA7"/>
<connect gate="D" pin="CCLK_0" pad="L12"/>
<connect gate="D" pin="DXP_0" pad="N10"/>
<connect gate="D" pin="GND" pad="R12"/>
<connect gate="D" pin="GND_10" pad="M19"/>
<connect gate="D" pin="GND_11" pad="N16"/>
<connect gate="D" pin="GND_12" pad="P11"/>
<connect gate="D" pin="GND_13" pad="P13"/>
<connect gate="D" pin="GND_14" pad="R10"/>
<connect gate="D" pin="GND_2" pad="H21"/>
<connect gate="D" pin="GND_3" pad="J10"/>
<connect gate="D" pin="GND_4" pad="J12"/>
<connect gate="D" pin="GND_5" pad="J18"/>
<connect gate="D" pin="GND_6" pad="K11"/>
<connect gate="D" pin="GND_7" pad="K15"/>
<connect gate="D" pin="GND_8" pad="L22"/>
<connect gate="D" pin="GND_9" pad="M11"/>
<connect gate="D" pin="IO_0_14" pad="P20"/>
<connect gate="D" pin="IO_0_15" pad="J16"/>
<connect gate="D" pin="IO_25_14" pad="N15"/>
<connect gate="D" pin="IO_25_15" pad="M17"/>
<connect gate="D" pin="IO_L10N_T1_AD11N_15" pad="L21"/>
<connect gate="D" pin="IO_L10P_T1_AD11P_15" pad="M21"/>
<connect gate="D" pin="IO_L11N_T1_SRCC_15" pad="J21"/>
<connect gate="D" pin="IO_L11P_T1_SRCC_15" pad="J20"/>
<connect gate="D" pin="IO_L12N_T1_MRCC_15" pad="H19"/>
<connect gate="D" pin="IO_L12P_T1_MRCC_15" pad="J19"/>
<connect gate="D" pin="IO_L13N_T2_MRCC_15" pad="K19"/>
<connect gate="D" pin="IO_L13P_T2_MRCC_15" pad="K18"/>
<connect gate="D" pin="IO_L14N_T2_SRCC_15" pad="L20"/>
<connect gate="D" pin="IO_L14P_T2_SRCC_15" pad="L19"/>
<connect gate="D" pin="IO_L15N_T2_DQS_ADV_B_15" pad="M22"/>
<connect gate="D" pin="IO_L15P_T2_DQS_15" pad="N22"/>
<connect gate="D" pin="IO_L16N_T2_A27_15" pad="L18"/>
<connect gate="D" pin="IO_L16P_T2_A28_15" pad="M18"/>
<connect gate="D" pin="IO_L17N_T2_A25_15" pad="N19"/>
<connect gate="D" pin="IO_L17P_T2_A26_15" pad="N18"/>
<connect gate="D" pin="IO_L18N_T2_A23_15" pad="M20"/>
<connect gate="D" pin="IO_L18P_T2_A24_15" pad="N20"/>
<connect gate="D" pin="IO_L19N_T3_A09_D25_VREF_14" pad="R14"/>
<connect gate="D" pin="IO_L19N_T3_A21_VREF_15" pad="K14"/>
<connect gate="D" pin="IO_L19P_T3_A10_D26_14" pad="P14"/>
<connect gate="D" pin="IO_L19P_T3_A22_15" pad="K13"/>
<connect gate="D" pin="IO_L1P_T0_AD0P_15" pad="H13"/>
<connect gate="D" pin="IO_L1P_T0_D00_MOSI_14" pad="P22"/>
<connect gate="D" pin="IO_L20N_T3_A19_15" pad="L13"/>
<connect gate="D" pin="IO_L20P_T3_A20_15" pad="M13"/>
<connect gate="D" pin="IO_L21N_T3_DQS_A06_D22_14" pad="P17"/>
<connect gate="D" pin="IO_L21N_T3_DQS_A18_15" pad="J17"/>
<connect gate="D" pin="IO_L21P_T3_DQS_14" pad="N17"/>
<connect gate="D" pin="IO_L21P_T3_DQS_15" pad="K17"/>
<connect gate="D" pin="IO_L22N_T3_A04_D20_14" pad="R16"/>
<connect gate="D" pin="IO_L22N_T3_A16_15" pad="L15"/>
<connect gate="D" pin="IO_L22P_T3_A05_D21_14" pad="P15"/>
<connect gate="D" pin="IO_L22P_T3_A17_15" pad="L14"/>
<connect gate="D" pin="IO_L23N_T3_A02_D18_14" pad="N14"/>
<connect gate="D" pin="IO_L23N_T3_FWE_B_15" pad="K16"/>
<connect gate="D" pin="IO_L23P_T3_A03_D19_14" pad="N13"/>
<connect gate="D" pin="IO_L23P_T3_FOE_B_15" pad="L16"/>
<connect gate="D" pin="IO_L24N_T3_A00_D16_14" pad="R17"/>
<connect gate="D" pin="IO_L24N_T3_RS0_15" pad="M16"/>
<connect gate="D" pin="IO_L24P_T3_A01_D17_14" pad="P16"/>
<connect gate="D" pin="IO_L24P_T3_RS1_15" pad="M15"/>
<connect gate="D" pin="IO_L2P_T0_D02_14" pad="P21"/>
<connect gate="D" pin="IO_L3N_T0_DQS_AD1N_15" pad="H14"/>
<connect gate="D" pin="IO_L3P_T0_DQS_AD1P_15" pad="J14"/>
<connect gate="D" pin="IO_L5N_T0_AD9N_15" pad="H15"/>
<connect gate="D" pin="IO_L5P_T0_AD9P_15" pad="J15"/>
<connect gate="D" pin="IO_L5P_T0_D06_14" pad="P19"/>
<connect gate="D" pin="IO_L6N_T0_VREF_15" pad="H18"/>
<connect gate="D" pin="IO_L6P_T0_15" pad="H17"/>
<connect gate="D" pin="IO_L7N_T1_AD2N_15" pad="H22"/>
<connect gate="D" pin="IO_L7P_T1_AD2P_15" pad="J22"/>
<connect gate="D" pin="IO_L8P_T1_AD10P_15" pad="H20"/>
<connect gate="D" pin="IO_L9N_T1_DQS_AD3N_15" pad="K22"/>
<connect gate="D" pin="IO_L9P_T1_DQS_AD3P_15" pad="K21"/>
<connect gate="D" pin="PROGRAM_B_0" pad="N12"/>
<connect gate="D" pin="TDI_0" pad="R13"/>
<connect gate="D" pin="VCCADC_0" pad="K10"/>
<connect gate="D" pin="VCCAUX" pad="R11"/>
<connect gate="D" pin="VCCAUX_2" pad="H12"/>
<connect gate="D" pin="VCCAUX_3" pad="K12"/>
<connect gate="D" pin="VCCAUX_4" pad="M12"/>
<connect gate="D" pin="VCCAUX_5" pad="P12"/>
<connect gate="D" pin="VCCBRAM" pad="N11"/>
<connect gate="D" pin="VCCBRAM_2" pad="J11"/>
<connect gate="D" pin="VCCBRAM_3" pad="L11"/>
<connect gate="D" pin="VCCINT" pad="P10"/>
<connect gate="D" pin="VCCO_14" pad="R15"/>
<connect gate="D" pin="VCCO_14_2" pad="M14"/>
<connect gate="D" pin="VCCO_14_3" pad="P18"/>
<connect gate="D" pin="VCCO_15" pad="N21"/>
<connect gate="D" pin="VCCO_15_2" pad="H16"/>
<connect gate="D" pin="VCCO_15_3" pad="J13"/>
<connect gate="D" pin="VCCO_15_4" pad="K20"/>
<connect gate="D" pin="VCCO_15_5" pad="L17"/>
<connect gate="D" pin="VP_0" pad="L10"/>
<connect gate="D" pin="VREFP_0" pad="M10"/>
<connect gate="E" pin="GND" pad="AB19"/>
<connect gate="E" pin="GND_10" pad="AA12"/>
<connect gate="E" pin="GND_11" pad="AA22"/>
<connect gate="E" pin="GND_2" pad="R20"/>
<connect gate="E" pin="GND_3" pad="T11"/>
<connect gate="E" pin="GND_4" pad="T17"/>
<connect gate="E" pin="GND_5" pad="U14"/>
<connect gate="E" pin="GND_6" pad="V11"/>
<connect gate="E" pin="GND_7" pad="V21"/>
<connect gate="E" pin="GND_8" pad="W18"/>
<connect gate="E" pin="GND_9" pad="Y15"/>
<connect gate="E" pin="INIT_B_0" pad="U12"/>
<connect gate="E" pin="IO_0_13" pad="Y17"/>
<connect gate="E" pin="IO_L10N_T1_13" pad="W10"/>
<connect gate="E" pin="IO_L10N_T1_D15_14" pad="AB22"/>
<connect gate="E" pin="IO_L10P_T1_13" pad="V10"/>
<connect gate="E" pin="IO_L10P_T1_D14_14" pad="AB21"/>
<connect gate="E" pin="IO_L11N_T1_SRCC_13" pad="Y12"/>
<connect gate="E" pin="IO_L11N_T1_SRCC_14" pad="V20"/>
<connect gate="E" pin="IO_L11P_T1_SRCC_13" pad="Y11"/>
<connect gate="E" pin="IO_L11P_T1_SRCC_14" pad="U20"/>
<connect gate="E" pin="IO_L12N_T1_MRCC_13" pad="W12"/>
<connect gate="E" pin="IO_L12N_T1_MRCC_14" pad="W20"/>
<connect gate="E" pin="IO_L12P_T1_MRCC_13" pad="W11"/>
<connect gate="E" pin="IO_L12P_T1_MRCC_14" pad="W19"/>
<connect gate="E" pin="IO_L13N_T2_MRCC_13" pad="V14"/>
<connect gate="E" pin="IO_L13N_T2_MRCC_14" pad="Y19"/>
<connect gate="E" pin="IO_L13P_T2_MRCC_13" pad="V13"/>
<connect gate="E" pin="IO_L13P_T2_MRCC_14" pad="Y18"/>
<connect gate="E" pin="IO_L14N_T2_SRCC_13" pad="V15"/>
<connect gate="E" pin="IO_L14N_T2_SRCC_14" pad="V19"/>
<connect gate="E" pin="IO_L14P_T2_SRCC_13" pad="U15"/>
<connect gate="E" pin="IO_L14P_T2_SRCC_14" pad="V18"/>
<connect gate="E" pin="IO_L15N_T2_DQS_13" pad="T15"/>
<connect gate="E" pin="IO_L15N_T2_DQS_DOUT_CSO_B_14" pad="AB20"/>
<connect gate="E" pin="IO_L15P_T2_DQS_13" pad="T14"/>
<connect gate="E" pin="IO_L15P_T2_DQS_RDWR_B_14" pad="AA19"/>
<connect gate="E" pin="IO_L16N_T2_13" pad="W16"/>
<connect gate="E" pin="IO_L16N_T2_A15_D31_14" pad="W17"/>
<connect gate="E" pin="IO_L16P_T2_13" pad="W15"/>
<connect gate="E" pin="IO_L16P_T2_CSI_B_14" pad="V17"/>
<connect gate="E" pin="IO_L17N_T2_13" pad="U16"/>
<connect gate="E" pin="IO_L17N_T2_A13_D29_14" pad="AB18"/>
<connect gate="E" pin="IO_L17P_T2_13" pad="T16"/>
<connect gate="E" pin="IO_L17P_T2_A14_D30_14" pad="AA18"/>
<connect gate="E" pin="IO_L18N_T2_A11_D27_14" pad="U18"/>
<connect gate="E" pin="IO_L18P_T2_A12_D28_14" pad="U17"/>
<connect gate="E" pin="IO_L1N_T0_13" pad="AA16"/>
<connect gate="E" pin="IO_L1N_T0_D01_DIN_14" pad="R22"/>
<connect gate="E" pin="IO_L1P_T0_13" pad="Y16"/>
<connect gate="E" pin="IO_L20N_T3_A07_D23_14" pad="T18"/>
<connect gate="E" pin="IO_L20P_T3_A08_D24_14" pad="R18"/>
<connect gate="E" pin="IO_L2N_T0_13" pad="AB17"/>
<connect gate="E" pin="IO_L2N_T0_D03_14" pad="R21"/>
<connect gate="E" pin="IO_L2P_T0_13" pad="AB16"/>
<connect gate="E" pin="IO_L3N_T0_DQS_13" pad="AB13"/>
<connect gate="E" pin="IO_L3N_T0_DQS_EMCCLK_14" pad="V22"/>
<connect gate="E" pin="IO_L3P_T0_DQS_13" pad="AA13"/>
<connect gate="E" pin="IO_L3P_T0_DQS_PUDC_B_14" pad="U22"/>
<connect gate="E" pin="IO_L4N_T0_13" pad="AB15"/>
<connect gate="E" pin="IO_L4N_T0_D05_14" pad="U21"/>
<connect gate="E" pin="IO_L4P_T0_13" pad="AA15"/>
<connect gate="E" pin="IO_L4P_T0_D04_14" pad="T21"/>
<connect gate="E" pin="IO_L5N_T0_13" pad="AA14"/>
<connect gate="E" pin="IO_L5N_T0_D07_14" pad="R19"/>
<connect gate="E" pin="IO_L5P_T0_13" pad="Y13"/>
<connect gate="E" pin="IO_L6N_T0_D08_VREF_14" pad="T20"/>
<connect gate="E" pin="IO_L6N_T0_VREF_13" pad="Y14"/>
<connect gate="E" pin="IO_L6P_T0_13" pad="W14"/>
<connect gate="E" pin="IO_L6P_T0_FCS_B_14" pad="T19"/>
<connect gate="E" pin="IO_L7N_T1_13" pad="AB12"/>
<connect gate="E" pin="IO_L7N_T1_D10_14" pad="W22"/>
<connect gate="E" pin="IO_L7P_T1_13" pad="AB11"/>
<connect gate="E" pin="IO_L7P_T1_D09_14" pad="W21"/>
<connect gate="E" pin="IO_L8N_T1_13" pad="AB10"/>
<connect gate="E" pin="IO_L8N_T1_D12_14" pad="AA21"/>
<connect gate="E" pin="IO_L8P_T1_D11_14" pad="AA20"/>
<connect gate="E" pin="IO_L9N_T1_DQS_13" pad="AA11"/>
<connect gate="E" pin="IO_L9N_T1_DQS_D13_14" pad="Y22"/>
<connect gate="E" pin="IO_L9P_T1_DQS_13" pad="AA10"/>
<connect gate="E" pin="IO_L9P_T1_DQS_14" pad="Y21"/>
<connect gate="E" pin="M0_0" pad="U11"/>
<connect gate="E" pin="M1_0" pad="U10"/>
<connect gate="E" pin="TCK_0" pad="V12"/>
<connect gate="E" pin="TDO_0" pad="U13"/>
<connect gate="E" pin="TMS_0" pad="T13"/>
<connect gate="E" pin="VCCINT" pad="T10"/>
<connect gate="E" pin="VCCO_0" pad="T12"/>
<connect gate="E" pin="VCCO_13" pad="AB14"/>
<connect gate="E" pin="VCCO_13_2" pad="V16"/>
<connect gate="E" pin="VCCO_13_3" pad="W13"/>
<connect gate="E" pin="VCCO_13_4" pad="Y10"/>
<connect gate="E" pin="VCCO_13_5" pad="AA17"/>
<connect gate="E" pin="VCCO_14" pad="Y20"/>
<connect gate="E" pin="VCCO_14_2" pad="T22"/>
<connect gate="E" pin="VCCO_14_3" pad="U19"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="XC7A100T-2FGG484I"/>
<attribute name="MFR_NAME" value="Xilinx Inc"/>
</technology>
</technologies>
</device>
<device name="FGG484(ARTIX-7)_XIL-L" package="FGG484(ARTIX-7)_XIL-L">
<connects>
<connect gate="A" pin="GND" pad="L2"/>
<connect gate="A" pin="GNDADC_0" pad="K9"/>
<connect gate="A" pin="GND_10" pad="D3"/>
<connect gate="A" pin="GND_11" pad="D4"/>
<connect gate="A" pin="GND_12" pad="D8"/>
<connect gate="A" pin="GND_13" pad="E4"/>
<connect gate="A" pin="GND_14" pad="E5"/>
<connect gate="A" pin="GND_15" pad="E7"/>
<connect gate="A" pin="GND_16" pad="E9"/>
<connect gate="A" pin="GND_17" pad="F5"/>
<connect gate="A" pin="GND_18" pad="G5"/>
<connect gate="A" pin="GND_19" pad="G6"/>
<connect gate="A" pin="GND_2" pad="A2"/>
<connect gate="A" pin="GND_20" pad="G7"/>
<connect gate="A" pin="GND_21" pad="G8"/>
<connect gate="A" pin="GND_22" pad="G9"/>
<connect gate="A" pin="GND_23" pad="H1"/>
<connect gate="A" pin="GND_24" pad="H7"/>
<connect gate="A" pin="GND_25" pad="H9"/>
<connect gate="A" pin="GND_26" pad="J8"/>
<connect gate="A" pin="GND_27" pad="K5"/>
<connect gate="A" pin="GND_28" pad="K7"/>
<connect gate="A" pin="GND_3" pad="A3"/>
<connect gate="A" pin="GND_4" pad="A5"/>
<connect gate="A" pin="GND_5" pad="A7"/>
<connect gate="A" pin="GND_6" pad="A9"/>
<connect gate="A" pin="GND_7" pad="B3"/>
<connect gate="A" pin="GND_8" pad="C3"/>
<connect gate="A" pin="GND_9" pad="C6"/>
<connect gate="A" pin="IO_0_35" pad="F4"/>
<connect gate="A" pin="IO_25_35" pad="L6"/>
<connect gate="A" pin="IO_L10N_T1_AD15N_35" pad="H5"/>
<connect gate="A" pin="IO_L10P_T1_AD15P_35" pad="J5"/>
<connect gate="A" pin="IO_L11N_T1_SRCC_35" pad="G3"/>
<connect gate="A" pin="IO_L11P_T1_SRCC_35" pad="H3"/>
<connect gate="A" pin="IO_L12N_T1_MRCC_35" pad="G4"/>
<connect gate="A" pin="IO_L12P_T1_MRCC_35" pad="H4"/>
<connect gate="A" pin="IO_L13N_T2_MRCC_35" pad="J4"/>
<connect gate="A" pin="IO_L13P_T2_MRCC_35" pad="K4"/>
<connect gate="A" pin="IO_L14N_T2_SRCC_35" pad="K3"/>
<connect gate="A" pin="IO_L14P_T2_SRCC_35" pad="L3"/>
<connect gate="A" pin="IO_L15N_T2_DQS_35" pad="L1"/>
<connect gate="A" pin="IO_L17N_T2_35" pad="J6"/>
<connect gate="A" pin="IO_L17P_T2_35" pad="K6"/>
<connect gate="A" pin="IO_L18N_T2_35" pad="L4"/>
<connect gate="A" pin="IO_L18P_T2_35" pad="L5"/>
<connect gate="A" pin="IO_L1N_T0_AD4N_35" pad="A1"/>
<connect gate="A" pin="IO_L1P_T0_AD4P_35" pad="B1"/>
<connect gate="A" pin="IO_L2N_T0_AD12N_35" pad="B2"/>
<connect gate="A" pin="IO_L2P_T0_AD12P_35" pad="C2"/>
<connect gate="A" pin="IO_L3N_T0_DQS_AD5N_35" pad="D1"/>
<connect gate="A" pin="IO_L3P_T0_DQS_AD5P_35" pad="E1"/>
<connect gate="A" pin="IO_L4N_T0_35" pad="D2"/>
<connect gate="A" pin="IO_L4P_T0_35" pad="E2"/>
<connect gate="A" pin="IO_L5N_T0_AD13N_35" pad="F1"/>
<connect gate="A" pin="IO_L5P_T0_AD13P_35" pad="G1"/>
<connect gate="A" pin="IO_L6N_T0_VREF_35" pad="E3"/>
<connect gate="A" pin="IO_L6P_T0_35" pad="F3"/>
<connect gate="A" pin="IO_L7N_T1_AD6N_35" pad="J1"/>
<connect gate="A" pin="IO_L7P_T1_AD6P_35" pad="K1"/>
<connect gate="A" pin="IO_L8N_T1_AD14N_35" pad="G2"/>
<connect gate="A" pin="IO_L8P_T1_AD14P_35" pad="H2"/>
<connect gate="A" pin="IO_L9N_T1_DQS_AD7N_35" pad="J2"/>
<connect gate="A" pin="IO_L9P_T1_DQS_AD7P_35" pad="K2"/>
<connect gate="A" pin="MGTAVCC" pad="F9"/>
<connect gate="A" pin="MGTAVCC_2" pad="D6"/>
<connect gate="A" pin="MGTAVCC_3" pad="E8"/>
<connect gate="A" pin="MGTAVCC_4" pad="F7"/>
<connect gate="A" pin="MGTAVTT" pad="C8"/>
<connect gate="A" pin="MGTAVTT_2" pad="B5"/>
<connect gate="A" pin="MGTAVTT_3" pad="B7"/>
<connect gate="A" pin="MGTAVTT_4" pad="B9"/>
<connect gate="A" pin="MGTAVTT_5" pad="C4"/>
<connect gate="A" pin="MGTPRXN0_216" pad="A8"/>
<connect gate="A" pin="MGTPRXN3_216" pad="C9"/>
<connect gate="A" pin="MGTPRXP0_216" pad="B8"/>
<connect gate="A" pin="MGTPRXP3_216" pad="D9"/>
<connect gate="A" pin="MGTPTXN0_216" pad="A4"/>
<connect gate="A" pin="MGTPTXN1_216" pad="C5"/>
<connect gate="A" pin="MGTPTXN2_216" pad="A6"/>
<connect gate="A" pin="MGTPTXN3_216" pad="C7"/>
<connect gate="A" pin="MGTPTXP0_216" pad="B4"/>
<connect gate="A" pin="MGTPTXP1_216" pad="D5"/>
<connect gate="A" pin="MGTPTXP2_216" pad="B6"/>
<connect gate="A" pin="MGTPTXP3_216" pad="D7"/>
<connect gate="A" pin="MGTREFCLK0N_216" pad="E6"/>
<connect gate="A" pin="MGTREFCLK0P_216" pad="F6"/>
<connect gate="A" pin="MGTRREF_216" pad="F8"/>
<connect gate="A" pin="VCCINT" pad="L7"/>
<connect gate="A" pin="VCCINT_2" pad="H8"/>
<connect gate="A" pin="VCCINT_3" pad="J7"/>
<connect gate="A" pin="VCCINT_4" pad="J9"/>
<connect gate="A" pin="VCCINT_5" pad="K8"/>
<connect gate="A" pin="VCCO_35" pad="J3"/>
<connect gate="A" pin="VCCO_35_2" pad="C1"/>
<connect gate="A" pin="VCCO_35_3" pad="F2"/>
<connect gate="A" pin="VCCO_35_4" pad="H6"/>
<connect gate="B" pin="CFGBVS_0" pad="U8"/>
<connect gate="B" pin="DXN_0" pad="N9"/>
<connect gate="B" pin="GND" pad="A22"/>
<connect gate="B" pin="GND_10" pad="T7"/>
<connect gate="B" pin="GND_11" pad="T9"/>
<connect gate="B" pin="GND_12" pad="U4"/>
<connect gate="B" pin="GND_13" pad="V1"/>
<connect gate="B" pin="GND_14" pad="W8"/>
<connect gate="B" pin="GND_15" pad="Y5"/>
<connect gate="B" pin="GND_16" pad="A11"/>
<connect gate="B" pin="GND_17" pad="A12"/>
<connect gate="B" pin="GND_2" pad="L8"/>
<connect gate="B" pin="GND_3" pad="M7"/>
<connect gate="B" pin="GND_4" pad="N6"/>
<connect gate="B" pin="GND_5" pad="N8"/>
<connect gate="B" pin="GND_6" pad="P3"/>
<connect gate="B" pin="GND_7" pad="P7"/>
<connect gate="B" pin="GND_8" pad="P9"/>
<connect gate="B" pin="GND_9" pad="R8"/>
<connect gate="B" pin="IO_0_34" pad="T3"/>
<connect gate="B" pin="IO_25_34" pad="U7"/>
<connect gate="B" pin="IO_L10N_T1_16" pad="A14"/>
<connect gate="B" pin="IO_L10P_T1_16" pad="A13"/>
<connect gate="B" pin="IO_L11P_T1_SRCC_34" pad="Y4"/>
<connect gate="B" pin="IO_L12N_T1_MRCC_34" pad="W4"/>
<connect gate="B" pin="IO_L12P_T1_MRCC_34" pad="V4"/>
<connect gate="B" pin="IO_L13N_T2_MRCC_34" pad="T4"/>
<connect gate="B" pin="IO_L13P_T2_MRCC_34" pad="R4"/>
<connect gate="B" pin="IO_L14N_T2_SRCC_34" pad="U5"/>
<connect gate="B" pin="IO_L14P_T2_SRCC_34" pad="T5"/>
<connect gate="B" pin="IO_L15N_T2_DQS_34" pad="W5"/>
<connect gate="B" pin="IO_L15P_T2_DQS_34" pad="W6"/>
<connect gate="B" pin="IO_L15P_T2_DQS_35" pad="M1"/>
<connect gate="B" pin="IO_L16N_T2_16" pad="A20"/>
<connect gate="B" pin="IO_L16N_T2_34" pad="V5"/>
<connect gate="B" pin="IO_L16N_T2_35" pad="M2"/>
<connect gate="B" pin="IO_L16P_T2_34" pad="U6"/>
<connect gate="B" pin="IO_L16P_T2_35" pad="M3"/>
<connect gate="B" pin="IO_L17N_T2_16" pad="A19"/>
<connect gate="B" pin="IO_L17N_T2_34" pad="T6"/>
<connect gate="B" pin="IO_L17P_T2_16" pad="A18"/>
<connect gate="B" pin="IO_L17P_T2_34" pad="R6"/>
<connect gate="B" pin="IO_L18P_T2_34" pad="Y6"/>
<connect gate="B" pin="IO_L19N_T3_VREF_34" pad="W7"/>
<connect gate="B" pin="IO_L19N_T3_VREF_35" pad="N3"/>
<connect gate="B" pin="IO_L19P_T3_34" pad="V7"/>
<connect gate="B" pin="IO_L19P_T3_35" pad="N4"/>
<connect gate="B" pin="IO_L1N_T0_34" pad="U1"/>
<connect gate="B" pin="IO_L1P_T0_34" pad="T1"/>
<connect gate="B" pin="IO_L20N_T3_35" pad="P1"/>
<connect gate="B" pin="IO_L20P_T3_35" pad="R1"/>
<connect gate="B" pin="IO_L21N_T3_DQS_16" pad="A21"/>
<connect gate="B" pin="IO_L21N_T3_DQS_34" pad="V8"/>
<connect gate="B" pin="IO_L21N_T3_DQS_35" pad="P4"/>
<connect gate="B" pin="IO_L21P_T3_DQS_34" pad="V9"/>
<connect gate="B" pin="IO_L21P_T3_DQS_35" pad="P5"/>
<connect gate="B" pin="IO_L22N_T3_35" pad="N2"/>
<connect gate="B" pin="IO_L22P_T3_35" pad="P2"/>
<connect gate="B" pin="IO_L23N_T3_34" pad="Y7"/>
<connect gate="B" pin="IO_L23N_T3_35" pad="M5"/>
<connect gate="B" pin="IO_L23P_T3_34" pad="Y8"/>
<connect gate="B" pin="IO_L23P_T3_35" pad="M6"/>
<connect gate="B" pin="IO_L24N_T3_34" pad="Y9"/>
<connect gate="B" pin="IO_L24N_T3_35" pad="N5"/>
<connect gate="B" pin="IO_L24P_T3_34" pad="W9"/>
<connect gate="B" pin="IO_L24P_T3_35" pad="P6"/>
<connect gate="B" pin="IO_L2N_T0_34" pad="V2"/>
<connect gate="B" pin="IO_L2P_T0_34" pad="U2"/>
<connect gate="B" pin="IO_L3N_T0_DQS_34" pad="R2"/>
<connect gate="B" pin="IO_L3P_T0_DQS_34" pad="R3"/>
<connect gate="B" pin="IO_L4N_T0_34" pad="Y2"/>
<connect gate="B" pin="IO_L4P_T0_34" pad="W2"/>
<connect gate="B" pin="IO_L5N_T0_34" pad="Y1"/>
<connect gate="B" pin="IO_L5P_T0_34" pad="W1"/>
<connect gate="B" pin="IO_L6N_T0_VREF_34" pad="V3"/>
<connect gate="B" pin="IO_L6P_T0_34" pad="U3"/>
<connect gate="B" pin="IO_L7P_T1_34" pad="AA1"/>
<connect gate="B" pin="IO_L9N_T1_DQS_16" pad="A16"/>
<connect gate="B" pin="IO_L9P_T1_DQS_16" pad="A15"/>
<connect gate="B" pin="IO_L9P_T1_DQS_34" pad="Y3"/>
<connect gate="B" pin="M2_0" pad="U9"/>
<connect gate="B" pin="MGTPRXN2_216" pad="A10"/>
<connect gate="B" pin="VCCINT" pad="T8"/>
<connect gate="B" pin="VCCINT_2" pad="M8"/>
<connect gate="B" pin="VCCINT_3" pad="N7"/>
<connect gate="B" pin="VCCINT_4" pad="P8"/>
<connect gate="B" pin="VCCINT_5" pad="R7"/>
<connect gate="B" pin="VCCINT_6" pad="R9"/>
<connect gate="B" pin="VCCO_16" pad="A17"/>
<connect gate="B" pin="VCCO_34" pad="W3"/>
<connect gate="B" pin="VCCO_34_2" pad="R5"/>
<connect gate="B" pin="VCCO_34_3" pad="T2"/>
<connect gate="B" pin="VCCO_34_4" pad="V6"/>
<connect gate="B" pin="VCCO_35" pad="N1"/>
<connect gate="B" pin="VCCO_35_2" pad="M4"/>
<connect gate="B" pin="VN_0" pad="M9"/>
<connect gate="B" pin="VREFN_0" pad="L9"/>
<connect gate="C" pin="DONE_0" pad="G11"/>
<connect gate="C" pin="GND" pad="H11"/>
<connect gate="C" pin="GND_10" pad="D13"/>
<connect gate="C" pin="GND_11" pad="E11"/>
<connect gate="C" pin="GND_12" pad="E20"/>
<connect gate="C" pin="GND_13" pad="F11"/>
<connect gate="C" pin="GND_14" pad="F17"/>
<connect gate="C" pin="GND_15" pad="G10"/>
<connect gate="C" pin="GND_16" pad="G12"/>
<connect gate="C" pin="GND_17" pad="G14"/>
<connect gate="C" pin="GND_2" pad="AA2"/>
<connect gate="C" pin="GND_3" pad="AB9"/>
<connect gate="C" pin="GND_4" pad="B12"/>
<connect gate="C" pin="GND_5" pad="B19"/>
<connect gate="C" pin="GND_6" pad="C10"/>
<connect gate="C" pin="GND_7" pad="C12"/>
<connect gate="C" pin="GND_8" pad="C16"/>
<connect gate="C" pin="GND_9" pad="D12"/>
<connect gate="C" pin="IO_0_16" pad="F15"/>
<connect gate="C" pin="IO_25_16" pad="F21"/>
<connect gate="C" pin="IO_L10N_T1_34" pad="AB5"/>
<connect gate="C" pin="IO_L10P_T1_34" pad="AA5"/>
<connect gate="C" pin="IO_L11N_T1_SRCC_16" pad="B18"/>
<connect gate="C" pin="IO_L11N_T1_SRCC_34" pad="AA4"/>
<connect gate="C" pin="IO_L11P_T1_SRCC_16" pad="B17"/>
<connect gate="C" pin="IO_L12N_T1_MRCC_16" pad="C17"/>
<connect gate="C" pin="IO_L12P_T1_MRCC_16" pad="D17"/>
<connect gate="C" pin="IO_L13N_T2_MRCC_16" pad="C19"/>
<connect gate="C" pin="IO_L13P_T2_MRCC_16" pad="C18"/>
<connect gate="C" pin="IO_L14N_T2_SRCC_16" pad="D19"/>
<connect gate="C" pin="IO_L14P_T2_SRCC_16" pad="E19"/>
<connect gate="C" pin="IO_L15N_T2_DQS_16" pad="E18"/>
<connect gate="C" pin="IO_L15P_T2_DQS_16" pad="F18"/>
<connect gate="C" pin="IO_L16P_T2_16" pad="B20"/>
<connect gate="C" pin="IO_L18N_T2_16" pad="F20"/>
<connect gate="C" pin="IO_L18N_T2_34" pad="AA6"/>
<connect gate="C" pin="IO_L18P_T2_16" pad="F19"/>
<connect gate="C" pin="IO_L19N_T3_VREF_16" pad="C20"/>
<connect gate="C" pin="IO_L19P_T3_16" pad="D20"/>
<connect gate="C" pin="IO_L1N_T0_16" pad="F14"/>
<connect gate="C" pin="IO_L1N_T0_AD0N_15" pad="G13"/>
<connect gate="C" pin="IO_L1P_T0_16" pad="F13"/>
<connect gate="C" pin="IO_L20N_T3_16" pad="B22"/>
<connect gate="C" pin="IO_L20N_T3_34" pad="AB6"/>
<connect gate="C" pin="IO_L20P_T3_16" pad="C22"/>
<connect gate="C" pin="IO_L20P_T3_34" pad="AB7"/>
<connect gate="C" pin="IO_L21P_T3_DQS_16" pad="B21"/>
<connect gate="C" pin="IO_L22N_T3_16" pad="D22"/>
<connect gate="C" pin="IO_L22N_T3_34" pad="AB8"/>
<connect gate="C" pin="IO_L22P_T3_16" pad="E22"/>
<connect gate="C" pin="IO_L22P_T3_34" pad="AA8"/>
<connect gate="C" pin="IO_L23N_T3_16" pad="D21"/>
<connect gate="C" pin="IO_L23P_T3_16" pad="E21"/>
<connect gate="C" pin="IO_L24N_T3_16" pad="G22"/>
<connect gate="C" pin="IO_L24P_T3_16" pad="G21"/>
<connect gate="C" pin="IO_L2N_T0_16" pad="E17"/>
<connect gate="C" pin="IO_L2N_T0_AD8N_15" pad="G16"/>
<connect gate="C" pin="IO_L2P_T0_16" pad="F16"/>
<connect gate="C" pin="IO_L2P_T0_AD8P_15" pad="G15"/>
<connect gate="C" pin="IO_L3N_T0_DQS_16" pad="C15"/>
<connect gate="C" pin="IO_L3P_T0_DQS_16" pad="C14"/>
<connect gate="C" pin="IO_L4N_T0_15" pad="G18"/>
<connect gate="C" pin="IO_L4N_T0_16" pad="E14"/>
<connect gate="C" pin="IO_L4P_T0_15" pad="G17"/>
<connect gate="C" pin="IO_L4P_T0_16" pad="E13"/>
<connect gate="C" pin="IO_L5N_T0_16" pad="D16"/>
<connect gate="C" pin="IO_L5P_T0_16" pad="E16"/>
<connect gate="C" pin="IO_L6N_T0_VREF_16" pad="D15"/>
<connect gate="C" pin="IO_L6P_T0_16" pad="D14"/>
<connect gate="C" pin="IO_L7N_T1_16" pad="B16"/>
<connect gate="C" pin="IO_L7N_T1_34" pad="AB1"/>
<connect gate="C" pin="IO_L7P_T1_16" pad="B15"/>
<connect gate="C" pin="IO_L8N_T1_16" pad="B13"/>
<connect gate="C" pin="IO_L8N_T1_34" pad="AB2"/>
<connect gate="C" pin="IO_L8N_T1_AD10N_15" pad="G20"/>
<connect gate="C" pin="IO_L8P_T1_13" pad="AA9"/>
<connect gate="C" pin="IO_L8P_T1_16" pad="C13"/>
<connect gate="C" pin="IO_L8P_T1_34" pad="AB3"/>
<connect gate="C" pin="IO_L9N_T1_DQS_34" pad="AA3"/>
<connect gate="C" pin="MGTAVCC" pad="D10"/>
<connect gate="C" pin="MGTAVTT" pad="B11"/>
<connect gate="C" pin="MGTPRXN1_216" pad="C11"/>
<connect gate="C" pin="MGTPRXP1_216" pad="D11"/>
<connect gate="C" pin="MGTPRXP2_216" pad="B10"/>
<connect gate="C" pin="MGTREFCLK1N_216" pad="E10"/>
<connect gate="C" pin="MGTREFCLK1P_216" pad="F10"/>
<connect gate="C" pin="VCCBATT_0" pad="E12"/>
<connect gate="C" pin="VCCINT" pad="H10"/>
<connect gate="C" pin="VCCO_0" pad="F12"/>
<connect gate="C" pin="VCCO_15" pad="G19"/>
<connect gate="C" pin="VCCO_16" pad="F22"/>
<connect gate="C" pin="VCCO_16_2" pad="B14"/>
<connect gate="C" pin="VCCO_16_3" pad="C21"/>
<connect gate="C" pin="VCCO_16_4" pad="D18"/>
<connect gate="C" pin="VCCO_16_5" pad="E15"/>
<connect gate="C" pin="VCCO_34" pad="AB4"/>
<connect gate="C" pin="VCCO_34_2" pad="AA7"/>
<connect gate="D" pin="CCLK_0" pad="L12"/>
<connect gate="D" pin="DXP_0" pad="N10"/>
<connect gate="D" pin="GND" pad="R12"/>
<connect gate="D" pin="GND_10" pad="M19"/>
<connect gate="D" pin="GND_11" pad="N16"/>
<connect gate="D" pin="GND_12" pad="P11"/>
<connect gate="D" pin="GND_13" pad="P13"/>
<connect gate="D" pin="GND_14" pad="R10"/>
<connect gate="D" pin="GND_2" pad="H21"/>
<connect gate="D" pin="GND_3" pad="J10"/>
<connect gate="D" pin="GND_4" pad="J12"/>
<connect gate="D" pin="GND_5" pad="J18"/>
<connect gate="D" pin="GND_6" pad="K11"/>
<connect gate="D" pin="GND_7" pad="K15"/>
<connect gate="D" pin="GND_8" pad="L22"/>
<connect gate="D" pin="GND_9" pad="M11"/>
<connect gate="D" pin="IO_0_14" pad="P20"/>
<connect gate="D" pin="IO_0_15" pad="J16"/>
<connect gate="D" pin="IO_25_14" pad="N15"/>
<connect gate="D" pin="IO_25_15" pad="M17"/>
<connect gate="D" pin="IO_L10N_T1_AD11N_15" pad="L21"/>
<connect gate="D" pin="IO_L10P_T1_AD11P_15" pad="M21"/>
<connect gate="D" pin="IO_L11N_T1_SRCC_15" pad="J21"/>
<connect gate="D" pin="IO_L11P_T1_SRCC_15" pad="J20"/>
<connect gate="D" pin="IO_L12N_T1_MRCC_15" pad="H19"/>
<connect gate="D" pin="IO_L12P_T1_MRCC_15" pad="J19"/>
<connect gate="D" pin="IO_L13N_T2_MRCC_15" pad="K19"/>
<connect gate="D" pin="IO_L13P_T2_MRCC_15" pad="K18"/>
<connect gate="D" pin="IO_L14N_T2_SRCC_15" pad="L20"/>
<connect gate="D" pin="IO_L14P_T2_SRCC_15" pad="L19"/>
<connect gate="D" pin="IO_L15N_T2_DQS_ADV_B_15" pad="M22"/>
<connect gate="D" pin="IO_L15P_T2_DQS_15" pad="N22"/>
<connect gate="D" pin="IO_L16N_T2_A27_15" pad="L18"/>
<connect gate="D" pin="IO_L16P_T2_A28_15" pad="M18"/>
<connect gate="D" pin="IO_L17N_T2_A25_15" pad="N19"/>
<connect gate="D" pin="IO_L17P_T2_A26_15" pad="N18"/>
<connect gate="D" pin="IO_L18N_T2_A23_15" pad="M20"/>
<connect gate="D" pin="IO_L18P_T2_A24_15" pad="N20"/>
<connect gate="D" pin="IO_L19N_T3_A09_D25_VREF_14" pad="R14"/>
<connect gate="D" pin="IO_L19N_T3_A21_VREF_15" pad="K14"/>
<connect gate="D" pin="IO_L19P_T3_A10_D26_14" pad="P14"/>
<connect gate="D" pin="IO_L19P_T3_A22_15" pad="K13"/>
<connect gate="D" pin="IO_L1P_T0_AD0P_15" pad="H13"/>
<connect gate="D" pin="IO_L1P_T0_D00_MOSI_14" pad="P22"/>
<connect gate="D" pin="IO_L20N_T3_A19_15" pad="L13"/>
<connect gate="D" pin="IO_L20P_T3_A20_15" pad="M13"/>
<connect gate="D" pin="IO_L21N_T3_DQS_A06_D22_14" pad="P17"/>
<connect gate="D" pin="IO_L21N_T3_DQS_A18_15" pad="J17"/>
<connect gate="D" pin="IO_L21P_T3_DQS_14" pad="N17"/>
<connect gate="D" pin="IO_L21P_T3_DQS_15" pad="K17"/>
<connect gate="D" pin="IO_L22N_T3_A04_D20_14" pad="R16"/>
<connect gate="D" pin="IO_L22N_T3_A16_15" pad="L15"/>
<connect gate="D" pin="IO_L22P_T3_A05_D21_14" pad="P15"/>
<connect gate="D" pin="IO_L22P_T3_A17_15" pad="L14"/>
<connect gate="D" pin="IO_L23N_T3_A02_D18_14" pad="N14"/>
<connect gate="D" pin="IO_L23N_T3_FWE_B_15" pad="K16"/>
<connect gate="D" pin="IO_L23P_T3_A03_D19_14" pad="N13"/>
<connect gate="D" pin="IO_L23P_T3_FOE_B_15" pad="L16"/>
<connect gate="D" pin="IO_L24N_T3_A00_D16_14" pad="R17"/>
<connect gate="D" pin="IO_L24N_T3_RS0_15" pad="M16"/>
<connect gate="D" pin="IO_L24P_T3_A01_D17_14" pad="P16"/>
<connect gate="D" pin="IO_L24P_T3_RS1_15" pad="M15"/>
<connect gate="D" pin="IO_L2P_T0_D02_14" pad="P21"/>
<connect gate="D" pin="IO_L3N_T0_DQS_AD1N_15" pad="H14"/>
<connect gate="D" pin="IO_L3P_T0_DQS_AD1P_15" pad="J14"/>
<connect gate="D" pin="IO_L5N_T0_AD9N_15" pad="H15"/>
<connect gate="D" pin="IO_L5P_T0_AD9P_15" pad="J15"/>
<connect gate="D" pin="IO_L5P_T0_D06_14" pad="P19"/>
<connect gate="D" pin="IO_L6N_T0_VREF_15" pad="H18"/>
<connect gate="D" pin="IO_L6P_T0_15" pad="H17"/>
<connect gate="D" pin="IO_L7N_T1_AD2N_15" pad="H22"/>
<connect gate="D" pin="IO_L7P_T1_AD2P_15" pad="J22"/>
<connect gate="D" pin="IO_L8P_T1_AD10P_15" pad="H20"/>
<connect gate="D" pin="IO_L9N_T1_DQS_AD3N_15" pad="K22"/>
<connect gate="D" pin="IO_L9P_T1_DQS_AD3P_15" pad="K21"/>
<connect gate="D" pin="PROGRAM_B_0" pad="N12"/>
<connect gate="D" pin="TDI_0" pad="R13"/>
<connect gate="D" pin="VCCADC_0" pad="K10"/>
<connect gate="D" pin="VCCAUX" pad="R11"/>
<connect gate="D" pin="VCCAUX_2" pad="H12"/>
<connect gate="D" pin="VCCAUX_3" pad="K12"/>
<connect gate="D" pin="VCCAUX_4" pad="M12"/>
<connect gate="D" pin="VCCAUX_5" pad="P12"/>
<connect gate="D" pin="VCCBRAM" pad="N11"/>
<connect gate="D" pin="VCCBRAM_2" pad="J11"/>
<connect gate="D" pin="VCCBRAM_3" pad="L11"/>
<connect gate="D" pin="VCCINT" pad="P10"/>
<connect gate="D" pin="VCCO_14" pad="R15"/>
<connect gate="D" pin="VCCO_14_2" pad="M14"/>
<connect gate="D" pin="VCCO_14_3" pad="P18"/>
<connect gate="D" pin="VCCO_15" pad="N21"/>
<connect gate="D" pin="VCCO_15_2" pad="H16"/>
<connect gate="D" pin="VCCO_15_3" pad="J13"/>
<connect gate="D" pin="VCCO_15_4" pad="K20"/>
<connect gate="D" pin="VCCO_15_5" pad="L17"/>
<connect gate="D" pin="VP_0" pad="L10"/>
<connect gate="D" pin="VREFP_0" pad="M10"/>
<connect gate="E" pin="GND" pad="AB19"/>
<connect gate="E" pin="GND_10" pad="AA12"/>
<connect gate="E" pin="GND_11" pad="AA22"/>
<connect gate="E" pin="GND_2" pad="R20"/>
<connect gate="E" pin="GND_3" pad="T11"/>
<connect gate="E" pin="GND_4" pad="T17"/>
<connect gate="E" pin="GND_5" pad="U14"/>
<connect gate="E" pin="GND_6" pad="V11"/>
<connect gate="E" pin="GND_7" pad="V21"/>
<connect gate="E" pin="GND_8" pad="W18"/>
<connect gate="E" pin="GND_9" pad="Y15"/>
<connect gate="E" pin="INIT_B_0" pad="U12"/>
<connect gate="E" pin="IO_0_13" pad="Y17"/>
<connect gate="E" pin="IO_L10N_T1_13" pad="W10"/>
<connect gate="E" pin="IO_L10N_T1_D15_14" pad="AB22"/>
<connect gate="E" pin="IO_L10P_T1_13" pad="V10"/>
<connect gate="E" pin="IO_L10P_T1_D14_14" pad="AB21"/>
<connect gate="E" pin="IO_L11N_T1_SRCC_13" pad="Y12"/>
<connect gate="E" pin="IO_L11N_T1_SRCC_14" pad="V20"/>
<connect gate="E" pin="IO_L11P_T1_SRCC_13" pad="Y11"/>
<connect gate="E" pin="IO_L11P_T1_SRCC_14" pad="U20"/>
<connect gate="E" pin="IO_L12N_T1_MRCC_13" pad="W12"/>
<connect gate="E" pin="IO_L12N_T1_MRCC_14" pad="W20"/>
<connect gate="E" pin="IO_L12P_T1_MRCC_13" pad="W11"/>
<connect gate="E" pin="IO_L12P_T1_MRCC_14" pad="W19"/>
<connect gate="E" pin="IO_L13N_T2_MRCC_13" pad="V14"/>
<connect gate="E" pin="IO_L13N_T2_MRCC_14" pad="Y19"/>
<connect gate="E" pin="IO_L13P_T2_MRCC_13" pad="V13"/>
<connect gate="E" pin="IO_L13P_T2_MRCC_14" pad="Y18"/>
<connect gate="E" pin="IO_L14N_T2_SRCC_13" pad="V15"/>
<connect gate="E" pin="IO_L14N_T2_SRCC_14" pad="V19"/>
<connect gate="E" pin="IO_L14P_T2_SRCC_13" pad="U15"/>
<connect gate="E" pin="IO_L14P_T2_SRCC_14" pad="V18"/>
<connect gate="E" pin="IO_L15N_T2_DQS_13" pad="T15"/>
<connect gate="E" pin="IO_L15N_T2_DQS_DOUT_CSO_B_14" pad="AB20"/>
<connect gate="E" pin="IO_L15P_T2_DQS_13" pad="T14"/>
<connect gate="E" pin="IO_L15P_T2_DQS_RDWR_B_14" pad="AA19"/>
<connect gate="E" pin="IO_L16N_T2_13" pad="W16"/>
<connect gate="E" pin="IO_L16N_T2_A15_D31_14" pad="W17"/>
<connect gate="E" pin="IO_L16P_T2_13" pad="W15"/>
<connect gate="E" pin="IO_L16P_T2_CSI_B_14" pad="V17"/>
<connect gate="E" pin="IO_L17N_T2_13" pad="U16"/>
<connect gate="E" pin="IO_L17N_T2_A13_D29_14" pad="AB18"/>
<connect gate="E" pin="IO_L17P_T2_13" pad="T16"/>
<connect gate="E" pin="IO_L17P_T2_A14_D30_14" pad="AA18"/>
<connect gate="E" pin="IO_L18N_T2_A11_D27_14" pad="U18"/>
<connect gate="E" pin="IO_L18P_T2_A12_D28_14" pad="U17"/>
<connect gate="E" pin="IO_L1N_T0_13" pad="AA16"/>
<connect gate="E" pin="IO_L1N_T0_D01_DIN_14" pad="R22"/>
<connect gate="E" pin="IO_L1P_T0_13" pad="Y16"/>
<connect gate="E" pin="IO_L20N_T3_A07_D23_14" pad="T18"/>
<connect gate="E" pin="IO_L20P_T3_A08_D24_14" pad="R18"/>
<connect gate="E" pin="IO_L2N_T0_13" pad="AB17"/>
<connect gate="E" pin="IO_L2N_T0_D03_14" pad="R21"/>
<connect gate="E" pin="IO_L2P_T0_13" pad="AB16"/>
<connect gate="E" pin="IO_L3N_T0_DQS_13" pad="AB13"/>
<connect gate="E" pin="IO_L3N_T0_DQS_EMCCLK_14" pad="V22"/>
<connect gate="E" pin="IO_L3P_T0_DQS_13" pad="AA13"/>
<connect gate="E" pin="IO_L3P_T0_DQS_PUDC_B_14" pad="U22"/>
<connect gate="E" pin="IO_L4N_T0_13" pad="AB15"/>
<connect gate="E" pin="IO_L4N_T0_D05_14" pad="U21"/>
<connect gate="E" pin="IO_L4P_T0_13" pad="AA15"/>
<connect gate="E" pin="IO_L4P_T0_D04_14" pad="T21"/>
<connect gate="E" pin="IO_L5N_T0_13" pad="AA14"/>
<connect gate="E" pin="IO_L5N_T0_D07_14" pad="R19"/>
<connect gate="E" pin="IO_L5P_T0_13" pad="Y13"/>
<connect gate="E" pin="IO_L6N_T0_D08_VREF_14" pad="T20"/>
<connect gate="E" pin="IO_L6N_T0_VREF_13" pad="Y14"/>
<connect gate="E" pin="IO_L6P_T0_13" pad="W14"/>
<connect gate="E" pin="IO_L6P_T0_FCS_B_14" pad="T19"/>
<connect gate="E" pin="IO_L7N_T1_13" pad="AB12"/>
<connect gate="E" pin="IO_L7N_T1_D10_14" pad="W22"/>
<connect gate="E" pin="IO_L7P_T1_13" pad="AB11"/>
<connect gate="E" pin="IO_L7P_T1_D09_14" pad="W21"/>
<connect gate="E" pin="IO_L8N_T1_13" pad="AB10"/>
<connect gate="E" pin="IO_L8N_T1_D12_14" pad="AA21"/>
<connect gate="E" pin="IO_L8P_T1_D11_14" pad="AA20"/>
<connect gate="E" pin="IO_L9N_T1_DQS_13" pad="AA11"/>
<connect gate="E" pin="IO_L9N_T1_DQS_D13_14" pad="Y22"/>
<connect gate="E" pin="IO_L9P_T1_DQS_13" pad="AA10"/>
<connect gate="E" pin="IO_L9P_T1_DQS_14" pad="Y21"/>
<connect gate="E" pin="M0_0" pad="U11"/>
<connect gate="E" pin="M1_0" pad="U10"/>
<connect gate="E" pin="TCK_0" pad="V12"/>
<connect gate="E" pin="TDO_0" pad="U13"/>
<connect gate="E" pin="TMS_0" pad="T13"/>
<connect gate="E" pin="VCCINT" pad="T10"/>
<connect gate="E" pin="VCCO_0" pad="T12"/>
<connect gate="E" pin="VCCO_13" pad="AB14"/>
<connect gate="E" pin="VCCO_13_2" pad="V16"/>
<connect gate="E" pin="VCCO_13_3" pad="W13"/>
<connect gate="E" pin="VCCO_13_4" pad="Y10"/>
<connect gate="E" pin="VCCO_13_5" pad="AA17"/>
<connect gate="E" pin="VCCO_14" pad="Y20"/>
<connect gate="E" pin="VCCO_14_2" pad="T22"/>
<connect gate="E" pin="VCCO_14_3" pad="U19"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="XC7A100T-2FGG484I"/>
<attribute name="MFR_NAME" value="Xilinx Inc"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="FT232RNQ-REEL" prefix="U">
<gates>
<gate name="A" symbol="FT232RNQ-REEL"/>
</gates>
<devices>
<device name="" package="QFN32_FT232_FTD">
<connects>
<connect gate="A" pin="3V3OUT" pad="16"/>
<connect gate="A" pin="AGND" pad="24"/>
<connect gate="A" pin="CBUS0" pad="22"/>
<connect gate="A" pin="CBUS1" pad="21"/>
<connect gate="A" pin="CBUS2" pad="10"/>
<connect gate="A" pin="CBUS3" pad="11"/>
<connect gate="A" pin="CBUS4" pad="9"/>
<connect gate="A" pin="CTS" pad="8"/>
<connect gate="A" pin="DCD" pad="7"/>
<connect gate="A" pin="DSR" pad="6"/>
<connect gate="A" pin="DTR" pad="31"/>
<connect gate="A" pin="EPAD" pad="33"/>
<connect gate="A" pin="GND" pad="20"/>
<connect gate="A" pin="GND_2" pad="4"/>
<connect gate="A" pin="GND_3" pad="17"/>
<connect gate="A" pin="NC" pad="29"/>
<connect gate="A" pin="NC_2" pad="5"/>
<connect gate="A" pin="NC_3" pad="12"/>
<connect gate="A" pin="NC_4" pad="13"/>
<connect gate="A" pin="NC_5" pad="23"/>
<connect gate="A" pin="NC_6" pad="25"/>
<connect gate="A" pin="OSCI" pad="27"/>
<connect gate="A" pin="OSCO" pad="28"/>
<connect gate="A" pin="RESET" pad="18"/>
<connect gate="A" pin="RI" pad="3"/>
<connect gate="A" pin="RTS" pad="32"/>
<connect gate="A" pin="RXD" pad="2"/>
<connect gate="A" pin="TEST" pad="26"/>
<connect gate="A" pin="TXD" pad="30"/>
<connect gate="A" pin="USBDM" pad="15"/>
<connect gate="A" pin="USBDP" pad="14"/>
<connect gate="A" pin="VCC" pad="19"/>
<connect gate="A" pin="VCCIO" pad="1"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="FT232RNQ-REEL"/>
<attribute name="MFR_NAME" value="FTDI, Future Technology Devices International Ltd"/>
<attribute name="TYPE" value="Interface"/>
</technology>
</technologies>
</device>
<device name="QFN32_FT232_FTD-M" package="QFN32_FT232_FTD-M">
<connects>
<connect gate="A" pin="3V3OUT" pad="16"/>
<connect gate="A" pin="AGND" pad="24"/>
<connect gate="A" pin="CBUS0" pad="22"/>
<connect gate="A" pin="CBUS1" pad="21"/>
<connect gate="A" pin="CBUS2" pad="10"/>
<connect gate="A" pin="CBUS3" pad="11"/>
<connect gate="A" pin="CBUS4" pad="9"/>
<connect gate="A" pin="CTS" pad="8"/>
<connect gate="A" pin="DCD" pad="7"/>
<connect gate="A" pin="DSR" pad="6"/>
<connect gate="A" pin="DTR" pad="31"/>
<connect gate="A" pin="EPAD" pad="33"/>
<connect gate="A" pin="GND" pad="20"/>
<connect gate="A" pin="GND_2" pad="4"/>
<connect gate="A" pin="GND_3" pad="17"/>
<connect gate="A" pin="NC" pad="29"/>
<connect gate="A" pin="NC_2" pad="5"/>
<connect gate="A" pin="NC_3" pad="12"/>
<connect gate="A" pin="NC_4" pad="13"/>
<connect gate="A" pin="NC_5" pad="23"/>
<connect gate="A" pin="NC_6" pad="25"/>
<connect gate="A" pin="OSCI" pad="27"/>
<connect gate="A" pin="OSCO" pad="28"/>
<connect gate="A" pin="RESET" pad="18"/>
<connect gate="A" pin="RI" pad="3"/>
<connect gate="A" pin="RTS" pad="32"/>
<connect gate="A" pin="RXD" pad="2"/>
<connect gate="A" pin="TEST" pad="26"/>
<connect gate="A" pin="TXD" pad="30"/>
<connect gate="A" pin="USBDM" pad="15"/>
<connect gate="A" pin="USBDP" pad="14"/>
<connect gate="A" pin="VCC" pad="19"/>
<connect gate="A" pin="VCCIO" pad="1"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="FT232RNQ-REEL"/>
<attribute name="MFR_NAME" value="FTDI, Future Technology Devices International Ltd"/>
<attribute name="TYPE" value="Interface"/>
</technology>
</technologies>
</device>
<device name="QFN32_FT232_FTD-L" package="QFN32_FT232_FTD-L">
<connects>
<connect gate="A" pin="3V3OUT" pad="16"/>
<connect gate="A" pin="AGND" pad="24"/>
<connect gate="A" pin="CBUS0" pad="22"/>
<connect gate="A" pin="CBUS1" pad="21"/>
<connect gate="A" pin="CBUS2" pad="10"/>
<connect gate="A" pin="CBUS3" pad="11"/>
<connect gate="A" pin="CBUS4" pad="9"/>
<connect gate="A" pin="CTS" pad="8"/>
<connect gate="A" pin="DCD" pad="7"/>
<connect gate="A" pin="DSR" pad="6"/>
<connect gate="A" pin="DTR" pad="31"/>
<connect gate="A" pin="EPAD" pad="33"/>
<connect gate="A" pin="GND" pad="20"/>
<connect gate="A" pin="GND_2" pad="4"/>
<connect gate="A" pin="GND_3" pad="17"/>
<connect gate="A" pin="NC" pad="29"/>
<connect gate="A" pin="NC_2" pad="5"/>
<connect gate="A" pin="NC_3" pad="12"/>
<connect gate="A" pin="NC_4" pad="13"/>
<connect gate="A" pin="NC_5" pad="23"/>
<connect gate="A" pin="NC_6" pad="25"/>
<connect gate="A" pin="OSCI" pad="27"/>
<connect gate="A" pin="OSCO" pad="28"/>
<connect gate="A" pin="RESET" pad="18"/>
<connect gate="A" pin="RI" pad="3"/>
<connect gate="A" pin="RTS" pad="32"/>
<connect gate="A" pin="RXD" pad="2"/>
<connect gate="A" pin="TEST" pad="26"/>
<connect gate="A" pin="TXD" pad="30"/>
<connect gate="A" pin="USBDM" pad="15"/>
<connect gate="A" pin="USBDP" pad="14"/>
<connect gate="A" pin="VCC" pad="19"/>
<connect gate="A" pin="VCCIO" pad="1"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="FT232RNQ-REEL"/>
<attribute name="MFR_NAME" value="FTDI, Future Technology Devices International Ltd"/>
<attribute name="TYPE" value="Interface"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="LSM9DS1TR" prefix="U">
<gates>
<gate name="A" symbol="LSM9DS1TR"/>
</gates>
<devices>
<device name="" package="LGA-24_3X3P5X1_STM">
<connects>
<connect gate="A" pin="C1" pad="24"/>
<connect gate="A" pin="CAP" pad="21"/>
<connect gate="A" pin="CS_A/G" pad="7"/>
<connect gate="A" pin="CS_M" pad="8"/>
<connect gate="A" pin="DEN_A/G" pad="13"/>
<connect gate="A" pin="DRDY_M" pad="9"/>
<connect gate="A" pin="GND" pad="20"/>
<connect gate="A" pin="GND_2" pad="19"/>
<connect gate="A" pin="INT1_A/G" pad="11"/>
<connect gate="A" pin="INT2_A/G" pad="12"/>
<connect gate="A" pin="INT_M" pad="10"/>
<connect gate="A" pin="RES" pad="18"/>
<connect gate="A" pin="RES_2" pad="14"/>
<connect gate="A" pin="RES_3" pad="15"/>
<connect gate="A" pin="RES_4" pad="16"/>
<connect gate="A" pin="RES_5" pad="17"/>
<connect gate="A" pin="SCL/SPC" pad="2"/>
<connect gate="A" pin="SDA/SDI/SDO" pad="4"/>
<connect gate="A" pin="SDO_A/G" pad="5"/>
<connect gate="A" pin="SDO_M" pad="6"/>
<connect gate="A" pin="VDD" pad="23"/>
<connect gate="A" pin="VDDIO" pad="3"/>
<connect gate="A" pin="VDDIO_2" pad="1"/>
<connect gate="A" pin="VDD_2" pad="22"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="LSM9DS1TR"/>
<attribute name="MFR_NAME" value="STMicroelectronics"/>
</technology>
</technologies>
</device>
<device name="LGA-24_3X3P5X1_STM-M" package="LGA-24_3X3P5X1_STM-M">
<connects>
<connect gate="A" pin="C1" pad="24"/>
<connect gate="A" pin="CAP" pad="21"/>
<connect gate="A" pin="CS_A/G" pad="7"/>
<connect gate="A" pin="CS_M" pad="8"/>
<connect gate="A" pin="DEN_A/G" pad="13"/>
<connect gate="A" pin="DRDY_M" pad="9"/>
<connect gate="A" pin="GND" pad="20"/>
<connect gate="A" pin="GND_2" pad="19"/>
<connect gate="A" pin="INT1_A/G" pad="11"/>
<connect gate="A" pin="INT2_A/G" pad="12"/>
<connect gate="A" pin="INT_M" pad="10"/>
<connect gate="A" pin="RES" pad="18"/>
<connect gate="A" pin="RES_2" pad="14"/>
<connect gate="A" pin="RES_3" pad="15"/>
<connect gate="A" pin="RES_4" pad="16"/>
<connect gate="A" pin="RES_5" pad="17"/>
<connect gate="A" pin="SCL/SPC" pad="2"/>
<connect gate="A" pin="SDA/SDI/SDO" pad="4"/>
<connect gate="A" pin="SDO_A/G" pad="5"/>
<connect gate="A" pin="SDO_M" pad="6"/>
<connect gate="A" pin="VDD" pad="23"/>
<connect gate="A" pin="VDDIO" pad="3"/>
<connect gate="A" pin="VDDIO_2" pad="1"/>
<connect gate="A" pin="VDD_2" pad="22"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="LSM9DS1TR"/>
<attribute name="MFR_NAME" value="STMicroelectronics"/>
</technology>
</technologies>
</device>
<device name="LGA-24_3X3P5X1_STM-L" package="LGA-24_3X3P5X1_STM-L">
<connects>
<connect gate="A" pin="C1" pad="24"/>
<connect gate="A" pin="CAP" pad="21"/>
<connect gate="A" pin="CS_A/G" pad="7"/>
<connect gate="A" pin="CS_M" pad="8"/>
<connect gate="A" pin="DEN_A/G" pad="13"/>
<connect gate="A" pin="DRDY_M" pad="9"/>
<connect gate="A" pin="GND" pad="20"/>
<connect gate="A" pin="GND_2" pad="19"/>
<connect gate="A" pin="INT1_A/G" pad="11"/>
<connect gate="A" pin="INT2_A/G" pad="12"/>
<connect gate="A" pin="INT_M" pad="10"/>
<connect gate="A" pin="RES" pad="18"/>
<connect gate="A" pin="RES_2" pad="14"/>
<connect gate="A" pin="RES_3" pad="15"/>
<connect gate="A" pin="RES_4" pad="16"/>
<connect gate="A" pin="RES_5" pad="17"/>
<connect gate="A" pin="SCL/SPC" pad="2"/>
<connect gate="A" pin="SDA/SDI/SDO" pad="4"/>
<connect gate="A" pin="SDO_A/G" pad="5"/>
<connect gate="A" pin="SDO_M" pad="6"/>
<connect gate="A" pin="VDD" pad="23"/>
<connect gate="A" pin="VDDIO" pad="3"/>
<connect gate="A" pin="VDDIO_2" pad="1"/>
<connect gate="A" pin="VDD_2" pad="22"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="LSM9DS1TR"/>
<attribute name="MFR_NAME" value="STMicroelectronics"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="NEO-M8N-0" prefix="U">
<gates>
<gate name="A" symbol="NEO-M8"/>
</gates>
<devices>
<device name="" package="MOD24_NEO-M8X_UBL">
<connects>
<connect gate="A" pin="D_SEL" pad="2"/>
<connect gate="A" pin="EXTINT" pad="4"/>
<connect gate="A" pin="GND" pad="24"/>
<connect gate="A" pin="GND_2" pad="10"/>
<connect gate="A" pin="GND_3" pad="12"/>
<connect gate="A" pin="GND_4" pad="13"/>
<connect gate="A" pin="LNA_EN" pad="14"/>
<connect gate="A" pin="RESERVED" pad="17"/>
<connect gate="A" pin="RESERVED_2" pad="15"/>
<connect gate="A" pin="RESERVED_3" pad="16"/>
<connect gate="A" pin="RESET_N" pad="8"/>
<connect gate="A" pin="RF_IN" pad="11"/>
<connect gate="A" pin="RXD/SPI_MOSI" pad="21"/>
<connect gate="A" pin="SAFEBOOT_N" pad="1"/>
<connect gate="A" pin="SCL/SPI_CLK" pad="19"/>
<connect gate="A" pin="SDA/SPI_CS_N" pad="18"/>
<connect gate="A" pin="TIMEPULSE" pad="3"/>
<connect gate="A" pin="TXD/SPI_MISO" pad="20"/>
<connect gate="A" pin="USB_DM" pad="5"/>
<connect gate="A" pin="USB_DP" pad="6"/>
<connect gate="A" pin="VCC" pad="23"/>
<connect gate="A" pin="VCC_RF" pad="9"/>
<connect gate="A" pin="VDD_USB" pad="7"/>
<connect gate="A" pin="V_BCKP" pad="22"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="NEO-M8N-0"/>
<attribute name="MFR_NAME" value="Ublox"/>
<attribute name="TYPE" value="RF"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="BMP388" prefix="U">
<gates>
<gate name="A" symbol="BMP388"/>
</gates>
<devices>
<device name="" package="QFN_BMP388_BOS">
<connects>
<connect gate="A" pin="CSB" pad="6"/>
<connect gate="A" pin="INT" pad="7"/>
<connect gate="A" pin="SCK" pad="2"/>
<connect gate="A" pin="SDI" pad="4"/>
<connect gate="A" pin="SDO" pad="5"/>
<connect gate="A" pin="VDD" pad="10"/>
<connect gate="A" pin="VDDIO" pad="1"/>
<connect gate="A" pin="VSS" pad="9"/>
<connect gate="A" pin="VSS_2" pad="3"/>
<connect gate="A" pin="VSS_3" pad="8"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="BMP388"/>
<attribute name="MFR_NAME" value="Bosch Sensortec"/>
</technology>
</technologies>
</device>
<device name="QFN_BMP388_BOS-M" package="QFN_BMP388_BOS-M">
<connects>
<connect gate="A" pin="CSB" pad="6"/>
<connect gate="A" pin="INT" pad="7"/>
<connect gate="A" pin="SCK" pad="2"/>
<connect gate="A" pin="SDI" pad="4"/>
<connect gate="A" pin="SDO" pad="5"/>
<connect gate="A" pin="VDD" pad="10"/>
<connect gate="A" pin="VDDIO" pad="1"/>
<connect gate="A" pin="VSS" pad="9"/>
<connect gate="A" pin="VSS_2" pad="3"/>
<connect gate="A" pin="VSS_3" pad="8"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="BMP388"/>
<attribute name="MFR_NAME" value="Bosch Sensortec"/>
</technology>
</technologies>
</device>
<device name="QFN_BMP388_BOS-L" package="QFN_BMP388_BOS-L">
<connects>
<connect gate="A" pin="CSB" pad="6"/>
<connect gate="A" pin="INT" pad="7"/>
<connect gate="A" pin="SCK" pad="2"/>
<connect gate="A" pin="SDI" pad="4"/>
<connect gate="A" pin="SDO" pad="5"/>
<connect gate="A" pin="VDD" pad="10"/>
<connect gate="A" pin="VDDIO" pad="1"/>
<connect gate="A" pin="VSS" pad="9"/>
<connect gate="A" pin="VSS_2" pad="3"/>
<connect gate="A" pin="VSS_3" pad="8"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="BMP388"/>
<attribute name="MFR_NAME" value="Bosch Sensortec"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="STM32F746ZGT7" prefix="U">
<gates>
<gate name="A" symbol="STM32F746ZGT7_A"/>
<gate name="B" symbol="STM32F746ZGT7_B"/>
<gate name="C" symbol="STM32F746ZGT7_C"/>
</gates>
<devices>
<device name="" package="LQFP-144_STM">
<connects>
<connect gate="A" pin="PA0" pad="34"/>
<connect gate="A" pin="PA1" pad="35"/>
<connect gate="A" pin="PA10" pad="102"/>
<connect gate="A" pin="PA11" pad="103"/>
<connect gate="A" pin="PA12" pad="104"/>
<connect gate="A" pin="PA13" pad="105"/>
<connect gate="A" pin="PA14" pad="109"/>
<connect gate="A" pin="PA15" pad="110"/>
<connect gate="A" pin="PA2" pad="36"/>
<connect gate="A" pin="PA3" pad="37"/>
<connect gate="A" pin="PA4" pad="40"/>
<connect gate="A" pin="PA5" pad="41"/>
<connect gate="A" pin="PA6" pad="42"/>
<connect gate="A" pin="PA7" pad="43"/>
<connect gate="A" pin="PA8" pad="100"/>
<connect gate="A" pin="PA9" pad="101"/>
<connect gate="A" pin="PB0" pad="46"/>
<connect gate="A" pin="PB1" pad="47"/>
<connect gate="A" pin="PB10" pad="69"/>
<connect gate="A" pin="PB11" pad="70"/>
<connect gate="A" pin="PB12" pad="73"/>
<connect gate="A" pin="PB13" pad="74"/>
<connect gate="A" pin="PB14" pad="75"/>
<connect gate="A" pin="PB15" pad="76"/>
<connect gate="A" pin="PB2" pad="48"/>
<connect gate="A" pin="PB3" pad="133"/>
<connect gate="A" pin="PB4" pad="134"/>
<connect gate="A" pin="PB5" pad="135"/>
<connect gate="A" pin="PB6" pad="136"/>
<connect gate="A" pin="PB7" pad="137"/>
<connect gate="A" pin="PB8" pad="139"/>
<connect gate="A" pin="PB9" pad="140"/>
<connect gate="A" pin="PC0" pad="26"/>
<connect gate="A" pin="PC1" pad="27"/>
<connect gate="A" pin="PC10" pad="111"/>
<connect gate="A" pin="PC11" pad="112"/>
<connect gate="A" pin="PC12" pad="113"/>
<connect gate="A" pin="PC13" pad="7"/>
<connect gate="A" pin="PC14" pad="8"/>
<connect gate="A" pin="PC15" pad="9"/>
<connect gate="A" pin="PC2" pad="28"/>
<connect gate="A" pin="PC3" pad="29"/>
<connect gate="A" pin="PC4" pad="44"/>
<connect gate="A" pin="PC5" pad="45"/>
<connect gate="A" pin="PC6" pad="96"/>
<connect gate="A" pin="PC7" pad="97"/>
<connect gate="A" pin="PC8" pad="98"/>
<connect gate="A" pin="PC9" pad="99"/>
<connect gate="A" pin="PD0" pad="114"/>
<connect gate="A" pin="PD1" pad="115"/>
<connect gate="A" pin="PD10" pad="79"/>
<connect gate="A" pin="PD11" pad="80"/>
<connect gate="A" pin="PD12" pad="81"/>
<connect gate="A" pin="PD13" pad="82"/>
<connect gate="A" pin="PD14" pad="85"/>
<connect gate="A" pin="PD15" pad="86"/>
<connect gate="A" pin="PD2" pad="116"/>
<connect gate="A" pin="PD3" pad="117"/>
<connect gate="A" pin="PD4" pad="118"/>
<connect gate="A" pin="PD5" pad="119"/>
<connect gate="A" pin="PD6" pad="122"/>
<connect gate="A" pin="PD7" pad="123"/>
<connect gate="A" pin="PD8" pad="77"/>
<connect gate="A" pin="PD9" pad="78"/>
<connect gate="B" pin="BOOT0" pad="138"/>
<connect gate="B" pin="NRST" pad="25"/>
<connect gate="B" pin="PDR_ON" pad="143"/>
<connect gate="B" pin="PE0" pad="141"/>
<connect gate="B" pin="PE1" pad="142"/>
<connect gate="B" pin="PE10" pad="63"/>
<connect gate="B" pin="PE11" pad="64"/>
<connect gate="B" pin="PE12" pad="65"/>
<connect gate="B" pin="PE13" pad="66"/>
<connect gate="B" pin="PE14" pad="67"/>
<connect gate="B" pin="PE15" pad="68"/>
<connect gate="B" pin="PE2" pad="1"/>
<connect gate="B" pin="PE3" pad="2"/>
<connect gate="B" pin="PE4" pad="3"/>
<connect gate="B" pin="PE5" pad="4"/>
<connect gate="B" pin="PE6" pad="5"/>
<connect gate="B" pin="PE7" pad="58"/>
<connect gate="B" pin="PE8" pad="59"/>
<connect gate="B" pin="PE9" pad="60"/>
<connect gate="B" pin="PF0" pad="10"/>
<connect gate="B" pin="PF1" pad="11"/>
<connect gate="B" pin="PF10" pad="22"/>
<connect gate="B" pin="PF11" pad="49"/>
<connect gate="B" pin="PF12" pad="50"/>
<connect gate="B" pin="PF13" pad="53"/>
<connect gate="B" pin="PF14" pad="54"/>
<connect gate="B" pin="PF15" pad="55"/>
<connect gate="B" pin="PF2" pad="12"/>
<connect gate="B" pin="PF3" pad="13"/>
<connect gate="B" pin="PF4" pad="14"/>
<connect gate="B" pin="PF5" pad="15"/>
<connect gate="B" pin="PF6" pad="18"/>
<connect gate="B" pin="PF7" pad="19"/>
<connect gate="B" pin="PF8" pad="20"/>
<connect gate="B" pin="PF9" pad="21"/>
<connect gate="B" pin="PG0" pad="56"/>
<connect gate="B" pin="PG1" pad="57"/>
<connect gate="B" pin="PG10" pad="125"/>
<connect gate="B" pin="PG11" pad="126"/>
<connect gate="B" pin="PG12" pad="127"/>
<connect gate="B" pin="PG13" pad="128"/>
<connect gate="B" pin="PG14" pad="129"/>
<connect gate="B" pin="PG15" pad="132"/>
<connect gate="B" pin="PG2" pad="87"/>
<connect gate="B" pin="PG3" pad="88"/>
<connect gate="B" pin="PG4" pad="89"/>
<connect gate="B" pin="PG5" pad="90"/>
<connect gate="B" pin="PG6" pad="91"/>
<connect gate="B" pin="PG7" pad="92"/>
<connect gate="B" pin="PG8" pad="93"/>
<connect gate="B" pin="PG9" pad="124"/>
<connect gate="B" pin="PH0" pad="23"/>
<connect gate="B" pin="PH1" pad="24"/>
<connect gate="C" pin="VBAT" pad="6"/>
<connect gate="C" pin="VCAP_1" pad="71"/>
<connect gate="C" pin="VCAP_2" pad="106"/>
<connect gate="C" pin="VDD" pad="144"/>
<connect gate="C" pin="VDDA" pad="33"/>
<connect gate="C" pin="VDDUSB" pad="95"/>
<connect gate="C" pin="VDD_10" pad="121"/>
<connect gate="C" pin="VDD_11" pad="131"/>
<connect gate="C" pin="VDD_2" pad="17"/>
<connect gate="C" pin="VDD_3" pad="30"/>
<connect gate="C" pin="VDD_4" pad="39"/>
<connect gate="C" pin="VDD_5" pad="52"/>
<connect gate="C" pin="VDD_6" pad="62"/>
<connect gate="C" pin="VDD_7" pad="72"/>
<connect gate="C" pin="VDD_8" pad="84"/>
<connect gate="C" pin="VDD_9" pad="108"/>
<connect gate="C" pin="VREF+" pad="32"/>
<connect gate="C" pin="VSS" pad="130"/>
<connect gate="C" pin="VSSA" pad="31"/>
<connect gate="C" pin="VSS_2" pad="16"/>
<connect gate="C" pin="VSS_3" pad="38"/>
<connect gate="C" pin="VSS_4" pad="51"/>
<connect gate="C" pin="VSS_5" pad="61"/>
<connect gate="C" pin="VSS_6" pad="83"/>
<connect gate="C" pin="VSS_7" pad="94"/>
<connect gate="C" pin="VSS_8" pad="107"/>
<connect gate="C" pin="VSS_9" pad="120"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="STM32F746ZGT7"/>
<attribute name="MFR_NAME" value="STMicroelectronics"/>
</technology>
</technologies>
</device>
<device name="LQFP-144_STM-M" package="LQFP-144_STM-M">
<connects>
<connect gate="A" pin="PA0" pad="34"/>
<connect gate="A" pin="PA1" pad="35"/>
<connect gate="A" pin="PA10" pad="102"/>
<connect gate="A" pin="PA11" pad="103"/>
<connect gate="A" pin="PA12" pad="104"/>
<connect gate="A" pin="PA13" pad="105"/>
<connect gate="A" pin="PA14" pad="109"/>
<connect gate="A" pin="PA15" pad="110"/>
<connect gate="A" pin="PA2" pad="36"/>
<connect gate="A" pin="PA3" pad="37"/>
<connect gate="A" pin="PA4" pad="40"/>
<connect gate="A" pin="PA5" pad="41"/>
<connect gate="A" pin="PA6" pad="42"/>
<connect gate="A" pin="PA7" pad="43"/>
<connect gate="A" pin="PA8" pad="100"/>
<connect gate="A" pin="PA9" pad="101"/>
<connect gate="A" pin="PB0" pad="46"/>
<connect gate="A" pin="PB1" pad="47"/>
<connect gate="A" pin="PB10" pad="69"/>
<connect gate="A" pin="PB11" pad="70"/>
<connect gate="A" pin="PB12" pad="73"/>
<connect gate="A" pin="PB13" pad="74"/>
<connect gate="A" pin="PB14" pad="75"/>
<connect gate="A" pin="PB15" pad="76"/>
<connect gate="A" pin="PB2" pad="48"/>
<connect gate="A" pin="PB3" pad="133"/>
<connect gate="A" pin="PB4" pad="134"/>
<connect gate="A" pin="PB5" pad="135"/>
<connect gate="A" pin="PB6" pad="136"/>
<connect gate="A" pin="PB7" pad="137"/>
<connect gate="A" pin="PB8" pad="139"/>
<connect gate="A" pin="PB9" pad="140"/>
<connect gate="A" pin="PC0" pad="26"/>
<connect gate="A" pin="PC1" pad="27"/>
<connect gate="A" pin="PC10" pad="111"/>
<connect gate="A" pin="PC11" pad="112"/>
<connect gate="A" pin="PC12" pad="113"/>
<connect gate="A" pin="PC13" pad="7"/>
<connect gate="A" pin="PC14" pad="8"/>
<connect gate="A" pin="PC15" pad="9"/>
<connect gate="A" pin="PC2" pad="28"/>
<connect gate="A" pin="PC3" pad="29"/>
<connect gate="A" pin="PC4" pad="44"/>
<connect gate="A" pin="PC5" pad="45"/>
<connect gate="A" pin="PC6" pad="96"/>
<connect gate="A" pin="PC7" pad="97"/>
<connect gate="A" pin="PC8" pad="98"/>
<connect gate="A" pin="PC9" pad="99"/>
<connect gate="A" pin="PD0" pad="114"/>
<connect gate="A" pin="PD1" pad="115"/>
<connect gate="A" pin="PD10" pad="79"/>
<connect gate="A" pin="PD11" pad="80"/>
<connect gate="A" pin="PD12" pad="81"/>
<connect gate="A" pin="PD13" pad="82"/>
<connect gate="A" pin="PD14" pad="85"/>
<connect gate="A" pin="PD15" pad="86"/>
<connect gate="A" pin="PD2" pad="116"/>
<connect gate="A" pin="PD3" pad="117"/>
<connect gate="A" pin="PD4" pad="118"/>
<connect gate="A" pin="PD5" pad="119"/>
<connect gate="A" pin="PD6" pad="122"/>
<connect gate="A" pin="PD7" pad="123"/>
<connect gate="A" pin="PD8" pad="77"/>
<connect gate="A" pin="PD9" pad="78"/>
<connect gate="B" pin="BOOT0" pad="138"/>
<connect gate="B" pin="NRST" pad="25"/>
<connect gate="B" pin="PDR_ON" pad="143"/>
<connect gate="B" pin="PE0" pad="141"/>
<connect gate="B" pin="PE1" pad="142"/>
<connect gate="B" pin="PE10" pad="63"/>
<connect gate="B" pin="PE11" pad="64"/>
<connect gate="B" pin="PE12" pad="65"/>
<connect gate="B" pin="PE13" pad="66"/>
<connect gate="B" pin="PE14" pad="67"/>
<connect gate="B" pin="PE15" pad="68"/>
<connect gate="B" pin="PE2" pad="1"/>
<connect gate="B" pin="PE3" pad="2"/>
<connect gate="B" pin="PE4" pad="3"/>
<connect gate="B" pin="PE5" pad="4"/>
<connect gate="B" pin="PE6" pad="5"/>
<connect gate="B" pin="PE7" pad="58"/>
<connect gate="B" pin="PE8" pad="59"/>
<connect gate="B" pin="PE9" pad="60"/>
<connect gate="B" pin="PF0" pad="10"/>
<connect gate="B" pin="PF1" pad="11"/>
<connect gate="B" pin="PF10" pad="22"/>
<connect gate="B" pin="PF11" pad="49"/>
<connect gate="B" pin="PF12" pad="50"/>
<connect gate="B" pin="PF13" pad="53"/>
<connect gate="B" pin="PF14" pad="54"/>
<connect gate="B" pin="PF15" pad="55"/>
<connect gate="B" pin="PF2" pad="12"/>
<connect gate="B" pin="PF3" pad="13"/>
<connect gate="B" pin="PF4" pad="14"/>
<connect gate="B" pin="PF5" pad="15"/>
<connect gate="B" pin="PF6" pad="18"/>
<connect gate="B" pin="PF7" pad="19"/>
<connect gate="B" pin="PF8" pad="20"/>
<connect gate="B" pin="PF9" pad="21"/>
<connect gate="B" pin="PG0" pad="56"/>
<connect gate="B" pin="PG1" pad="57"/>
<connect gate="B" pin="PG10" pad="125"/>
<connect gate="B" pin="PG11" pad="126"/>
<connect gate="B" pin="PG12" pad="127"/>
<connect gate="B" pin="PG13" pad="128"/>
<connect gate="B" pin="PG14" pad="129"/>
<connect gate="B" pin="PG15" pad="132"/>
<connect gate="B" pin="PG2" pad="87"/>
<connect gate="B" pin="PG3" pad="88"/>
<connect gate="B" pin="PG4" pad="89"/>
<connect gate="B" pin="PG5" pad="90"/>
<connect gate="B" pin="PG6" pad="91"/>
<connect gate="B" pin="PG7" pad="92"/>
<connect gate="B" pin="PG8" pad="93"/>
<connect gate="B" pin="PG9" pad="124"/>
<connect gate="B" pin="PH0" pad="23"/>
<connect gate="B" pin="PH1" pad="24"/>
<connect gate="C" pin="VBAT" pad="6"/>
<connect gate="C" pin="VCAP_1" pad="71"/>
<connect gate="C" pin="VCAP_2" pad="106"/>
<connect gate="C" pin="VDD" pad="144"/>
<connect gate="C" pin="VDDA" pad="33"/>
<connect gate="C" pin="VDDUSB" pad="95"/>
<connect gate="C" pin="VDD_10" pad="121"/>
<connect gate="C" pin="VDD_11" pad="131"/>
<connect gate="C" pin="VDD_2" pad="17"/>
<connect gate="C" pin="VDD_3" pad="30"/>
<connect gate="C" pin="VDD_4" pad="39"/>
<connect gate="C" pin="VDD_5" pad="52"/>
<connect gate="C" pin="VDD_6" pad="62"/>
<connect gate="C" pin="VDD_7" pad="72"/>
<connect gate="C" pin="VDD_8" pad="84"/>
<connect gate="C" pin="VDD_9" pad="108"/>
<connect gate="C" pin="VREF+" pad="32"/>
<connect gate="C" pin="VSS" pad="130"/>
<connect gate="C" pin="VSSA" pad="31"/>
<connect gate="C" pin="VSS_2" pad="16"/>
<connect gate="C" pin="VSS_3" pad="38"/>
<connect gate="C" pin="VSS_4" pad="51"/>
<connect gate="C" pin="VSS_5" pad="61"/>
<connect gate="C" pin="VSS_6" pad="83"/>
<connect gate="C" pin="VSS_7" pad="94"/>
<connect gate="C" pin="VSS_8" pad="107"/>
<connect gate="C" pin="VSS_9" pad="120"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="STM32F746ZGT7"/>
<attribute name="MFR_NAME" value="STMicroelectronics"/>
</technology>
</technologies>
</device>
<device name="LQFP-144_STM-L" package="LQFP-144_STM-L">
<connects>
<connect gate="A" pin="PA0" pad="34"/>
<connect gate="A" pin="PA1" pad="35"/>
<connect gate="A" pin="PA10" pad="102"/>
<connect gate="A" pin="PA11" pad="103"/>
<connect gate="A" pin="PA12" pad="104"/>
<connect gate="A" pin="PA13" pad="105"/>
<connect gate="A" pin="PA14" pad="109"/>
<connect gate="A" pin="PA15" pad="110"/>
<connect gate="A" pin="PA2" pad="36"/>
<connect gate="A" pin="PA3" pad="37"/>
<connect gate="A" pin="PA4" pad="40"/>
<connect gate="A" pin="PA5" pad="41"/>
<connect gate="A" pin="PA6" pad="42"/>
<connect gate="A" pin="PA7" pad="43"/>
<connect gate="A" pin="PA8" pad="100"/>
<connect gate="A" pin="PA9" pad="101"/>
<connect gate="A" pin="PB0" pad="46"/>
<connect gate="A" pin="PB1" pad="47"/>
<connect gate="A" pin="PB10" pad="69"/>
<connect gate="A" pin="PB11" pad="70"/>
<connect gate="A" pin="PB12" pad="73"/>
<connect gate="A" pin="PB13" pad="74"/>
<connect gate="A" pin="PB14" pad="75"/>
<connect gate="A" pin="PB15" pad="76"/>
<connect gate="A" pin="PB2" pad="48"/>
<connect gate="A" pin="PB3" pad="133"/>
<connect gate="A" pin="PB4" pad="134"/>
<connect gate="A" pin="PB5" pad="135"/>
<connect gate="A" pin="PB6" pad="136"/>
<connect gate="A" pin="PB7" pad="137"/>
<connect gate="A" pin="PB8" pad="139"/>
<connect gate="A" pin="PB9" pad="140"/>
<connect gate="A" pin="PC0" pad="26"/>
<connect gate="A" pin="PC1" pad="27"/>
<connect gate="A" pin="PC10" pad="111"/>
<connect gate="A" pin="PC11" pad="112"/>
<connect gate="A" pin="PC12" pad="113"/>
<connect gate="A" pin="PC13" pad="7"/>
<connect gate="A" pin="PC14" pad="8"/>
<connect gate="A" pin="PC15" pad="9"/>
<connect gate="A" pin="PC2" pad="28"/>
<connect gate="A" pin="PC3" pad="29"/>
<connect gate="A" pin="PC4" pad="44"/>
<connect gate="A" pin="PC5" pad="45"/>
<connect gate="A" pin="PC6" pad="96"/>
<connect gate="A" pin="PC7" pad="97"/>
<connect gate="A" pin="PC8" pad="98"/>
<connect gate="A" pin="PC9" pad="99"/>
<connect gate="A" pin="PD0" pad="114"/>
<connect gate="A" pin="PD1" pad="115"/>
<connect gate="A" pin="PD10" pad="79"/>
<connect gate="A" pin="PD11" pad="80"/>
<connect gate="A" pin="PD12" pad="81"/>
<connect gate="A" pin="PD13" pad="82"/>
<connect gate="A" pin="PD14" pad="85"/>
<connect gate="A" pin="PD15" pad="86"/>
<connect gate="A" pin="PD2" pad="116"/>
<connect gate="A" pin="PD3" pad="117"/>
<connect gate="A" pin="PD4" pad="118"/>
<connect gate="A" pin="PD5" pad="119"/>
<connect gate="A" pin="PD6" pad="122"/>
<connect gate="A" pin="PD7" pad="123"/>
<connect gate="A" pin="PD8" pad="77"/>
<connect gate="A" pin="PD9" pad="78"/>
<connect gate="B" pin="BOOT0" pad="138"/>
<connect gate="B" pin="NRST" pad="25"/>
<connect gate="B" pin="PDR_ON" pad="143"/>
<connect gate="B" pin="PE0" pad="141"/>
<connect gate="B" pin="PE1" pad="142"/>
<connect gate="B" pin="PE10" pad="63"/>
<connect gate="B" pin="PE11" pad="64"/>
<connect gate="B" pin="PE12" pad="65"/>
<connect gate="B" pin="PE13" pad="66"/>
<connect gate="B" pin="PE14" pad="67"/>
<connect gate="B" pin="PE15" pad="68"/>
<connect gate="B" pin="PE2" pad="1"/>
<connect gate="B" pin="PE3" pad="2"/>
<connect gate="B" pin="PE4" pad="3"/>
<connect gate="B" pin="PE5" pad="4"/>
<connect gate="B" pin="PE6" pad="5"/>
<connect gate="B" pin="PE7" pad="58"/>
<connect gate="B" pin="PE8" pad="59"/>
<connect gate="B" pin="PE9" pad="60"/>
<connect gate="B" pin="PF0" pad="10"/>
<connect gate="B" pin="PF1" pad="11"/>
<connect gate="B" pin="PF10" pad="22"/>
<connect gate="B" pin="PF11" pad="49"/>
<connect gate="B" pin="PF12" pad="50"/>
<connect gate="B" pin="PF13" pad="53"/>
<connect gate="B" pin="PF14" pad="54"/>
<connect gate="B" pin="PF15" pad="55"/>
<connect gate="B" pin="PF2" pad="12"/>
<connect gate="B" pin="PF3" pad="13"/>
<connect gate="B" pin="PF4" pad="14"/>
<connect gate="B" pin="PF5" pad="15"/>
<connect gate="B" pin="PF6" pad="18"/>
<connect gate="B" pin="PF7" pad="19"/>
<connect gate="B" pin="PF8" pad="20"/>
<connect gate="B" pin="PF9" pad="21"/>
<connect gate="B" pin="PG0" pad="56"/>
<connect gate="B" pin="PG1" pad="57"/>
<connect gate="B" pin="PG10" pad="125"/>
<connect gate="B" pin="PG11" pad="126"/>
<connect gate="B" pin="PG12" pad="127"/>
<connect gate="B" pin="PG13" pad="128"/>
<connect gate="B" pin="PG14" pad="129"/>
<connect gate="B" pin="PG15" pad="132"/>
<connect gate="B" pin="PG2" pad="87"/>
<connect gate="B" pin="PG3" pad="88"/>
<connect gate="B" pin="PG4" pad="89"/>
<connect gate="B" pin="PG5" pad="90"/>
<connect gate="B" pin="PG6" pad="91"/>
<connect gate="B" pin="PG7" pad="92"/>
<connect gate="B" pin="PG8" pad="93"/>
<connect gate="B" pin="PG9" pad="124"/>
<connect gate="B" pin="PH0" pad="23"/>
<connect gate="B" pin="PH1" pad="24"/>
<connect gate="C" pin="VBAT" pad="6"/>
<connect gate="C" pin="VCAP_1" pad="71"/>
<connect gate="C" pin="VCAP_2" pad="106"/>
<connect gate="C" pin="VDD" pad="144"/>
<connect gate="C" pin="VDDA" pad="33"/>
<connect gate="C" pin="VDDUSB" pad="95"/>
<connect gate="C" pin="VDD_10" pad="121"/>
<connect gate="C" pin="VDD_11" pad="131"/>
<connect gate="C" pin="VDD_2" pad="17"/>
<connect gate="C" pin="VDD_3" pad="30"/>
<connect gate="C" pin="VDD_4" pad="39"/>
<connect gate="C" pin="VDD_5" pad="52"/>
<connect gate="C" pin="VDD_6" pad="62"/>
<connect gate="C" pin="VDD_7" pad="72"/>
<connect gate="C" pin="VDD_8" pad="84"/>
<connect gate="C" pin="VDD_9" pad="108"/>
<connect gate="C" pin="VREF+" pad="32"/>
<connect gate="C" pin="VSS" pad="130"/>
<connect gate="C" pin="VSSA" pad="31"/>
<connect gate="C" pin="VSS_2" pad="16"/>
<connect gate="C" pin="VSS_3" pad="38"/>
<connect gate="C" pin="VSS_4" pad="51"/>
<connect gate="C" pin="VSS_5" pad="61"/>
<connect gate="C" pin="VSS_6" pad="83"/>
<connect gate="C" pin="VSS_7" pad="94"/>
<connect gate="C" pin="VSS_8" pad="107"/>
<connect gate="C" pin="VSS_9" pad="120"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="STM32F746ZGT7"/>
<attribute name="MFR_NAME" value="STMicroelectronics"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="MT25QL01GBBB1EW9-0SIT" prefix="U">
<gates>
<gate name="A" symbol="MT25QL01GBBB1EW9-0SIT"/>
</gates>
<devices>
<device name="" package="W-PDFN8(MLP8)_W9_MRN">
<connects>
<connect gate="A" pin="C" pad="6"/>
<connect gate="A" pin="DQ0" pad="5"/>
<connect gate="A" pin="DQ1" pad="2"/>
<connect gate="A" pin="DQ3/HOLD" pad="7"/>
<connect gate="A" pin="S" pad="1"/>
<connect gate="A" pin="VCC" pad="8"/>
<connect gate="A" pin="VSS" pad="9"/>
<connect gate="A" pin="VSS_2" pad="4"/>
<connect gate="A" pin="W/DQ2" pad="3"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="MT25QL01GBBB1EW9-0SIT"/>
<attribute name="MFR_NAME" value="Micron"/>
</technology>
</technologies>
</device>
<device name="W-PDFN8(MLP8)_W9_MRN-M" package="W-PDFN8(MLP8)_W9_MRN-M">
<connects>
<connect gate="A" pin="C" pad="6"/>
<connect gate="A" pin="DQ0" pad="5"/>
<connect gate="A" pin="DQ1" pad="2"/>
<connect gate="A" pin="DQ3/HOLD" pad="7"/>
<connect gate="A" pin="S" pad="1"/>
<connect gate="A" pin="VCC" pad="8"/>
<connect gate="A" pin="VSS" pad="9"/>
<connect gate="A" pin="VSS_2" pad="4"/>
<connect gate="A" pin="W/DQ2" pad="3"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="MT25QL01GBBB1EW9-0SIT"/>
<attribute name="MFR_NAME" value="Micron"/>
</technology>
</technologies>
</device>
<device name="W-PDFN8(MLP8)_W9_MRN-L" package="W-PDFN8(MLP8)_W9_MRN-L">
<connects>
<connect gate="A" pin="C" pad="6"/>
<connect gate="A" pin="DQ0" pad="5"/>
<connect gate="A" pin="DQ1" pad="2"/>
<connect gate="A" pin="DQ3/HOLD" pad="7"/>
<connect gate="A" pin="S" pad="1"/>
<connect gate="A" pin="VCC" pad="8"/>
<connect gate="A" pin="VSS" pad="9"/>
<connect gate="A" pin="VSS_2" pad="4"/>
<connect gate="A" pin="W/DQ2" pad="3"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="MT25QL01GBBB1EW9-0SIT"/>
<attribute name="MFR_NAME" value="Micron"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="TCM2-63WX+" prefix="XMER">
<gates>
<gate name="A" symbol="TCM2-63WX+"/>
</gates>
<devices>
<device name="" package="DB1627_MNC">
<connects>
<connect gate="A" pin="NC" pad="5"/>
<connect gate="A" pin="PRIMARY/GND" pad="2"/>
<connect gate="A" pin="PRIMARY/GND_2" pad="1"/>
<connect gate="A" pin="PRIMARY_DOT" pad="3"/>
<connect gate="A" pin="SECONDARY" pad="4"/>
<connect gate="A" pin="SECONDARY_DOT" pad="6"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="TCM2-63WX+"/>
<attribute name="MFR_NAME" value="Mini Circuits"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="ADP1755ACPZ-R7" prefix="U">
<gates>
<gate name="A" symbol="ADP1755ACPZ-R7"/>
</gates>
<devices>
<device name="" package="CP-16-23_ADI">
<connects>
<connect gate="A" pin="ADJ" pad="9"/>
<connect gate="A" pin="EN" pad="4"/>
<connect gate="A" pin="EPAD" pad="17"/>
<connect gate="A" pin="GND" pad="6"/>
<connect gate="A" pin="NC" pad="8"/>
<connect gate="A" pin="PG" pad="5"/>
<connect gate="A" pin="SS" pad="7"/>
<connect gate="A" pin="VIN" pad="16"/>
<connect gate="A" pin="VIN_2" pad="1"/>
<connect gate="A" pin="VIN_3" pad="2"/>
<connect gate="A" pin="VIN_4" pad="3"/>
<connect gate="A" pin="VIN_5" pad="15"/>
<connect gate="A" pin="VOUT" pad="14"/>
<connect gate="A" pin="VOUT_2" pad="10"/>
<connect gate="A" pin="VOUT_3" pad="11"/>
<connect gate="A" pin="VOUT_4" pad="12"/>
<connect gate="A" pin="VOUT_5" pad="13"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="ADP1755ACPZ-R7"/>
<attribute name="MFR_NAME" value="Analog Devices Inc"/>
</technology>
</technologies>
</device>
<device name="CP-16-23_ADI-M" package="CP-16-23_ADI-M">
<connects>
<connect gate="A" pin="ADJ" pad="9"/>
<connect gate="A" pin="EN" pad="4"/>
<connect gate="A" pin="EPAD" pad="17"/>
<connect gate="A" pin="GND" pad="6"/>
<connect gate="A" pin="NC" pad="8"/>
<connect gate="A" pin="PG" pad="5"/>
<connect gate="A" pin="SS" pad="7"/>
<connect gate="A" pin="VIN" pad="16"/>
<connect gate="A" pin="VIN_2" pad="1"/>
<connect gate="A" pin="VIN_3" pad="2"/>
<connect gate="A" pin="VIN_4" pad="3"/>
<connect gate="A" pin="VIN_5" pad="15"/>
<connect gate="A" pin="VOUT" pad="14"/>
<connect gate="A" pin="VOUT_2" pad="10"/>
<connect gate="A" pin="VOUT_3" pad="11"/>
<connect gate="A" pin="VOUT_4" pad="12"/>
<connect gate="A" pin="VOUT_5" pad="13"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="ADP1755ACPZ-R7"/>
<attribute name="MFR_NAME" value="Analog Devices Inc"/>
</technology>
</technologies>
</device>
<device name="CP-16-23_ADI-L" package="CP-16-23_ADI-L">
<connects>
<connect gate="A" pin="ADJ" pad="9"/>
<connect gate="A" pin="EN" pad="4"/>
<connect gate="A" pin="EPAD" pad="17"/>
<connect gate="A" pin="GND" pad="6"/>
<connect gate="A" pin="NC" pad="8"/>
<connect gate="A" pin="PG" pad="5"/>
<connect gate="A" pin="SS" pad="7"/>
<connect gate="A" pin="VIN" pad="16"/>
<connect gate="A" pin="VIN_2" pad="1"/>
<connect gate="A" pin="VIN_3" pad="2"/>
<connect gate="A" pin="VIN_4" pad="3"/>
<connect gate="A" pin="VIN_5" pad="15"/>
<connect gate="A" pin="VOUT" pad="14"/>
<connect gate="A" pin="VOUT_2" pad="10"/>
<connect gate="A" pin="VOUT_3" pad="11"/>
<connect gate="A" pin="VOUT_4" pad="12"/>
<connect gate="A" pin="VOUT_5" pad="13"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="ADP1755ACPZ-R7"/>
<attribute name="MFR_NAME" value="Analog Devices Inc"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="ADP2164ACPZ-R7" prefix="U">
<gates>
<gate name="A" symbol="ADP2164ACPZ-R7"/>
</gates>
<devices>
<device name="" package="CP_16_17_ADI">
<connects>
<connect gate="A" pin="EN" pad="15"/>
<connect gate="A" pin="EP" pad="17"/>
<connect gate="A" pin="FB" pad="4"/>
<connect gate="A" pin="GND" pad="5"/>
<connect gate="A" pin="PGND" pad="8"/>
<connect gate="A" pin="PGND_2" pad="6"/>
<connect gate="A" pin="PGND_3" pad="7"/>
<connect gate="A" pin="PGOOD" pad="16"/>
<connect gate="A" pin="PVIN" pad="13"/>
<connect gate="A" pin="PVIN_2" pad="12"/>
<connect gate="A" pin="RT" pad="2"/>
<connect gate="A" pin="SW" pad="11"/>
<connect gate="A" pin="SW_2" pad="9"/>
<connect gate="A" pin="SW_3" pad="10"/>
<connect gate="A" pin="SYNC" pad="1"/>
<connect gate="A" pin="TRK" pad="3"/>
<connect gate="A" pin="VIN" pad="14"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="ADP2164ACPZ-R7"/>
<attribute name="MFR_NAME" value="Analog Devices Inc"/>
</technology>
</technologies>
</device>
<device name="CP_16_17_ADI-M" package="CP_16_17_ADI-M">
<connects>
<connect gate="A" pin="EN" pad="15"/>
<connect gate="A" pin="EP" pad="17"/>
<connect gate="A" pin="FB" pad="4"/>
<connect gate="A" pin="GND" pad="5"/>
<connect gate="A" pin="PGND" pad="8"/>
<connect gate="A" pin="PGND_2" pad="6"/>
<connect gate="A" pin="PGND_3" pad="7"/>
<connect gate="A" pin="PGOOD" pad="16"/>
<connect gate="A" pin="PVIN" pad="13"/>
<connect gate="A" pin="PVIN_2" pad="12"/>
<connect gate="A" pin="RT" pad="2"/>
<connect gate="A" pin="SW" pad="11"/>
<connect gate="A" pin="SW_2" pad="9"/>
<connect gate="A" pin="SW_3" pad="10"/>
<connect gate="A" pin="SYNC" pad="1"/>
<connect gate="A" pin="TRK" pad="3"/>
<connect gate="A" pin="VIN" pad="14"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="ADP2164ACPZ-R7"/>
<attribute name="MFR_NAME" value="Analog Devices Inc"/>
</technology>
</technologies>
</device>
<device name="CP_16_17_ADI-L" package="CP_16_17_ADI-L">
<connects>
<connect gate="A" pin="EN" pad="15"/>
<connect gate="A" pin="EP" pad="17"/>
<connect gate="A" pin="FB" pad="4"/>
<connect gate="A" pin="GND" pad="5"/>
<connect gate="A" pin="PGND" pad="8"/>
<connect gate="A" pin="PGND_2" pad="6"/>
<connect gate="A" pin="PGND_3" pad="7"/>
<connect gate="A" pin="PGOOD" pad="16"/>
<connect gate="A" pin="PVIN" pad="13"/>
<connect gate="A" pin="PVIN_2" pad="12"/>
<connect gate="A" pin="RT" pad="2"/>
<connect gate="A" pin="SW" pad="11"/>
<connect gate="A" pin="SW_2" pad="9"/>
<connect gate="A" pin="SW_3" pad="10"/>
<connect gate="A" pin="SYNC" pad="1"/>
<connect gate="A" pin="TRK" pad="3"/>
<connect gate="A" pin="VIN" pad="14"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="ADP2164ACPZ-R7"/>
<attribute name="MFR_NAME" value="Analog Devices Inc"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="MAX20029ATIA/V+" prefix="U">
<gates>
<gate name="A" symbol="MAX20029ATIA/V+"/>
</gates>
<devices>
<device name="" package="21-0140L_T2855-5_MXM">
<connects>
<connect gate="A" pin="EN1" pad="1"/>
<connect gate="A" pin="EN2" pad="9"/>
<connect gate="A" pin="EN3" pad="13"/>
<connect gate="A" pin="EN4" pad="21"/>
<connect gate="A" pin="EPAD" pad="29"/>
<connect gate="A" pin="GND" pad="24"/>
<connect gate="A" pin="GND_2" pad="11"/>
<connect gate="A" pin="LX1" pad="3"/>
<connect gate="A" pin="LX2" pad="6"/>
<connect gate="A" pin="LX3" pad="16"/>
<connect gate="A" pin="LX4" pad="19"/>
<connect gate="A" pin="OUTS1" pad="28"/>
<connect gate="A" pin="OUTS2" pad="8"/>
<connect gate="A" pin="OUTS3" pad="14"/>
<connect gate="A" pin="OUTS4" pad="22"/>
<connect gate="A" pin="PG1" pad="27"/>
<connect gate="A" pin="PG2" pad="10"/>
<connect gate="A" pin="PG3" pad="12"/>
<connect gate="A" pin="PG4" pad="23"/>
<connect gate="A" pin="PGND1" pad="4"/>
<connect gate="A" pin="PGND2" pad="5"/>
<connect gate="A" pin="PGND3" pad="17"/>
<connect gate="A" pin="PGND4" pad="18"/>
<connect gate="A" pin="PV1" pad="2"/>
<connect gate="A" pin="PV2" pad="7"/>
<connect gate="A" pin="PV3" pad="15"/>
<connect gate="A" pin="PV4" pad="20"/>
<connect gate="A" pin="SYNC" pad="25"/>
<connect gate="A" pin="VA" pad="26"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="MAX20029ATIA/V+"/>
<attribute name="MFR_NAME" value="Analog Devices Inc"/>
</technology>
</technologies>
</device>
<device name="21-0140L_T2855-5_MXM-M" package="21-0140L_T2855-5_MXM-M">
<connects>
<connect gate="A" pin="EN1" pad="1"/>
<connect gate="A" pin="EN2" pad="9"/>
<connect gate="A" pin="EN3" pad="13"/>
<connect gate="A" pin="EN4" pad="21"/>
<connect gate="A" pin="EPAD" pad="29"/>
<connect gate="A" pin="GND" pad="24"/>
<connect gate="A" pin="GND_2" pad="11"/>
<connect gate="A" pin="LX1" pad="3"/>
<connect gate="A" pin="LX2" pad="6"/>
<connect gate="A" pin="LX3" pad="16"/>
<connect gate="A" pin="LX4" pad="19"/>
<connect gate="A" pin="OUTS1" pad="28"/>
<connect gate="A" pin="OUTS2" pad="8"/>
<connect gate="A" pin="OUTS3" pad="14"/>
<connect gate="A" pin="OUTS4" pad="22"/>
<connect gate="A" pin="PG1" pad="27"/>
<connect gate="A" pin="PG2" pad="10"/>
<connect gate="A" pin="PG3" pad="12"/>
<connect gate="A" pin="PG4" pad="23"/>
<connect gate="A" pin="PGND1" pad="4"/>
<connect gate="A" pin="PGND2" pad="5"/>
<connect gate="A" pin="PGND3" pad="17"/>
<connect gate="A" pin="PGND4" pad="18"/>
<connect gate="A" pin="PV1" pad="2"/>
<connect gate="A" pin="PV2" pad="7"/>
<connect gate="A" pin="PV3" pad="15"/>
<connect gate="A" pin="PV4" pad="20"/>
<connect gate="A" pin="SYNC" pad="25"/>
<connect gate="A" pin="VA" pad="26"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="MAX20029ATIA/V+"/>
<attribute name="MFR_NAME" value="Analog Devices Inc"/>
</technology>
</technologies>
</device>
<device name="21-0140L_T2855-5_MXM-L" package="21-0140L_T2855-5_MXM-L">
<connects>
<connect gate="A" pin="EN1" pad="1"/>
<connect gate="A" pin="EN2" pad="9"/>
<connect gate="A" pin="EN3" pad="13"/>
<connect gate="A" pin="EN4" pad="21"/>
<connect gate="A" pin="EPAD" pad="29"/>
<connect gate="A" pin="GND" pad="24"/>
<connect gate="A" pin="GND_2" pad="11"/>
<connect gate="A" pin="LX1" pad="3"/>
<connect gate="A" pin="LX2" pad="6"/>
<connect gate="A" pin="LX3" pad="16"/>
<connect gate="A" pin="LX4" pad="19"/>
<connect gate="A" pin="OUTS1" pad="28"/>
<connect gate="A" pin="OUTS2" pad="8"/>
<connect gate="A" pin="OUTS3" pad="14"/>
<connect gate="A" pin="OUTS4" pad="22"/>
<connect gate="A" pin="PG1" pad="27"/>
<connect gate="A" pin="PG2" pad="10"/>
<connect gate="A" pin="PG3" pad="12"/>
<connect gate="A" pin="PG4" pad="23"/>
<connect gate="A" pin="PGND1" pad="4"/>
<connect gate="A" pin="PGND2" pad="5"/>
<connect gate="A" pin="PGND3" pad="17"/>
<connect gate="A" pin="PGND4" pad="18"/>
<connect gate="A" pin="PV1" pad="2"/>
<connect gate="A" pin="PV2" pad="7"/>
<connect gate="A" pin="PV3" pad="15"/>
<connect gate="A" pin="PV4" pad="20"/>
<connect gate="A" pin="SYNC" pad="25"/>
<connect gate="A" pin="VA" pad="26"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="MAX20029ATIA/V+"/>
<attribute name="MFR_NAME" value="Analog Devices Inc"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="CYUSB3014-BZXI" prefix="U">
<gates>
<gate name="A" symbol="CYUSB3014-BZXI_A"/>
<gate name="B" symbol="CYUSB3014-BZXI_B"/>
</gates>
<devices>
<device name="" package="BGA-121">
<connects>
<connect gate="A" pin="!RESET" pad="C5"/>
<connect gate="A" pin="AVDD" pad="A7"/>
<connect gate="A" pin="AVSS" pad="B7"/>
<connect gate="A" pin="CLKIN_32" pad="D7"/>
<connect gate="A" pin="CLKIN_32_2" pad="D6"/>
<connect gate="A" pin="CVDDQ" pad="B6"/>
<connect gate="A" pin="DP" pad="A9"/>
<connect gate="A" pin="FSLC[0]" pad="B2"/>
<connect gate="A" pin="FSLC[1]" pad="B4"/>
<connect gate="A" pin="FSLC[2]" pad="E6"/>
<connect gate="A" pin="GPIO[1]" pad="F9"/>
<connect gate="A" pin="GPIO[21]" pad="G7"/>
<connect gate="A" pin="GPIO[22]" pad="G6"/>
<connect gate="A" pin="GPIO[25]" pad="G5"/>
<connect gate="A" pin="GPIO[2]" pad="F7"/>
<connect gate="A" pin="GPIO[30]" pad="G4"/>
<connect gate="A" pin="GPIO[41]" pad="F4"/>
<connect gate="A" pin="GPIO[42]" pad="G2"/>
<connect gate="A" pin="GPIO[43]" pad="G3"/>
<connect gate="A" pin="GPIO[44]" pad="F3"/>
<connect gate="A" pin="GPIO[45]" pad="F2"/>
<connect gate="A" pin="GPIO[46]" pad="F5"/>
<connect gate="A" pin="GPIO[47]" pad="E1"/>
<connect gate="A" pin="GPIO[48]" pad="E5"/>
<connect gate="A" pin="GPIO[49]" pad="E4"/>
<connect gate="A" pin="GPIO[50]" pad="D1"/>
<connect gate="A" pin="GPIO[51]" pad="D2"/>
<connect gate="A" pin="GPIO[52]" pad="D3"/>
<connect gate="A" pin="GPIO[53]" pad="D4"/>
<connect gate="A" pin="GPIO[54]" pad="C1"/>
<connect gate="A" pin="GPIO[55]" pad="C2"/>
<connect gate="A" pin="GPIO[56]" pad="D5"/>
<connect gate="A" pin="GPIO[57]" pad="C4"/>
<connect gate="A" pin="GPIO[5]" pad="F8"/>
<connect gate="A" pin="I2C_GPIO[58]" pad="D9"/>
<connect gate="A" pin="OTG_ID" pad="C9"/>
<connect gate="A" pin="R_USB2" pad="C8"/>
<connect gate="A" pin="R_USB3" pad="B3"/>
<connect gate="A" pin="SSRXM" pad="A3"/>
<connect gate="A" pin="SSRXP" pad="A4"/>
<connect gate="A" pin="SSTXM" pad="A6"/>
<connect gate="A" pin="SSTXP" pad="A5"/>
<connect gate="A" pin="TCK" pad="F6"/>
<connect gate="A" pin="TDI" pad="E7"/>
<connect gate="A" pin="TMS" pad="E8"/>
<connect gate="A" pin="U3RXVDDQ" pad="A2"/>
<connect gate="A" pin="U3TXVDDQ" pad="B5"/>
<connect gate="A" pin="U3VSSQ" pad="A1"/>
<connect gate="A" pin="VDD" pad="E9"/>
<connect gate="A" pin="VDD_2" pad="C3"/>
<connect gate="A" pin="VIO2" pad="F1"/>
<connect gate="A" pin="VIO3" pad="E3"/>
<connect gate="A" pin="VIO4" pad="B1"/>
<connect gate="A" pin="VSS" pad="G1"/>
<connect gate="A" pin="VSS_2" pad="A8"/>
<connect gate="A" pin="VSS_3" pad="B8"/>
<connect gate="A" pin="VSS_4" pad="B9"/>
<connect gate="A" pin="VSS_5" pad="D8"/>
<connect gate="A" pin="VSS_6" pad="E2"/>
<connect gate="A" pin="XTALIN" pad="C6"/>
<connect gate="A" pin="XTALOUT" pad="C7"/>
<connect gate="B" pin="!INT" pad="L8"/>
<connect gate="B" pin="!TRST" pad="B11"/>
<connect gate="B" pin="DM" pad="A10"/>
<connect gate="B" pin="GPIO[0]" pad="F10"/>
<connect gate="B" pin="GPIO[10]" pad="K11"/>
<connect gate="B" pin="GPIO[11]" pad="L10"/>
<connect gate="B" pin="GPIO[12]" pad="K10"/>
<connect gate="B" pin="GPIO[13]" pad="K9"/>
<connect gate="B" pin="GPIO[14]" pad="J8"/>
<connect gate="B" pin="GPIO[15]" pad="G8"/>
<connect gate="B" pin="GPIO[16]" pad="J6"/>
<connect gate="B" pin="GPIO[17]" pad="K8"/>
<connect gate="B" pin="GPIO[18]" pad="K7"/>
<connect gate="B" pin="GPIO[19]" pad="J7"/>
<connect gate="B" pin="GPIO[20]" pad="H7"/>
<connect gate="B" pin="GPIO[23]" pad="K6"/>
<connect gate="B" pin="GPIO[24]" pad="H8"/>
<connect gate="B" pin="GPIO[26]" pad="H6"/>
<connect gate="B" pin="GPIO[27]" pad="K5"/>
<connect gate="B" pin="GPIO[28]" pad="J5"/>
<connect gate="B" pin="GPIO[29]" pad="H5"/>
<connect gate="B" pin="GPIO[31]" pad="H4"/>
<connect gate="B" pin="GPIO[32]" pad="L4"/>
<connect gate="B" pin="GPIO[33]" pad="K2"/>
<connect gate="B" pin="GPIO[34]" pad="J4"/>
<connect gate="B" pin="GPIO[35]" pad="K1"/>
<connect gate="B" pin="GPIO[36]" pad="J2"/>
<connect gate="B" pin="GPIO[37]" pad="J3"/>
<connect gate="B" pin="GPIO[38]" pad="J1"/>
<connect gate="B" pin="GPIO[39]" pad="H2"/>
<connect gate="B" pin="GPIO[3]" pad="G10"/>
<connect gate="B" pin="GPIO[40]" pad="H3"/>
<connect gate="B" pin="GPIO[4]" pad="G9"/>
<connect gate="B" pin="GPIO[6]" pad="H10"/>
<connect gate="B" pin="GPIO[7]" pad="H9"/>
<connect gate="B" pin="GPIO[8]" pad="J10"/>
<connect gate="B" pin="GPIO[9]" pad="J9"/>
<connect gate="B" pin="I2C_GPIO[59]" pad="D10"/>
<connect gate="B" pin="NC" pad="A11"/>
<connect gate="B" pin="O[60]" pad="D11"/>
<connect gate="B" pin="TDO" pad="C10"/>
<connect gate="B" pin="VBATT" pad="E10"/>
<connect gate="B" pin="VBUS" pad="E11"/>
<connect gate="B" pin="VDD" pad="J11"/>
<connect gate="B" pin="VDD_2" pad="H1"/>
<connect gate="B" pin="VDD_3" pad="L5"/>
<connect gate="B" pin="VDD_4" pad="L7"/>
<connect gate="B" pin="VDD_5" pad="B10"/>
<connect gate="B" pin="VDD_6" pad="F11"/>
<connect gate="B" pin="VIO1" pad="H11"/>
<connect gate="B" pin="VIO1_2" pad="L9"/>
<connect gate="B" pin="VIO5" pad="C11"/>
<connect gate="B" pin="VSS" pad="L11"/>
<connect gate="B" pin="VSS_2" pad="K3"/>
<connect gate="B" pin="VSS_3" pad="K4"/>
<connect gate="B" pin="VSS_4" pad="L1"/>
<connect gate="B" pin="VSS_5" pad="L2"/>
<connect gate="B" pin="VSS_6" pad="L3"/>
<connect gate="B" pin="VSS_7" pad="L6"/>
<connect gate="B" pin="VSS_8" pad="G11"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="CYUSB3014-BZXI"/>
<attribute name="MFR_NAME" value="Cypress Semiconductor"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="LUSB359300" prefix="J">
<gates>
<gate name="A" symbol="LUSB359300"/>
</gates>
<devices>
<device name="" package="LUSB359300_AMP">
<connects>
<connect gate="A" pin="D+" pad="3"/>
<connect gate="A" pin="D-" pad="2"/>
<connect gate="A" pin="GND" pad="4"/>
<connect gate="A" pin="GND_DRAIN" pad="7"/>
<connect gate="A" pin="STDAA_SSTX+" pad="9"/>
<connect gate="A" pin="STDAA_SSTX-" pad="8"/>
<connect gate="A" pin="STDA_SSRX+" pad="6"/>
<connect gate="A" pin="STDA_SSRX-" pad="5"/>
<connect gate="A" pin="VBUS" pad="1"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="LUSB359300"/>
<attribute name="MFR_NAME" value="Amphenol ICC"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="AT25XE041B-MHNHR-T" prefix="U">
<gates>
<gate name="A" symbol="AT25XE041B-MHNHR-T"/>
</gates>
<devices>
<device name="" package="UDFN8_8MA1_ADO">
<connects>
<connect gate="A" pin="!CS" pad="1"/>
<connect gate="A" pin="!HOLD" pad="7"/>
<connect gate="A" pin="!WP" pad="3"/>
<connect gate="A" pin="GND" pad="9"/>
<connect gate="A" pin="GND_2" pad="4"/>
<connect gate="A" pin="SCK" pad="6"/>
<connect gate="A" pin="SI" pad="5"/>
<connect gate="A" pin="SO" pad="2"/>
<connect gate="A" pin="VCC" pad="8"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="AT25XE041B-MHNHR-T"/>
<attribute name="MFR_NAME" value="Adesto Technologies"/>
</technology>
</technologies>
</device>
<device name="UDFN8_8MA1_ADO-M" package="UDFN8_8MA1_ADO-M">
<connects>
<connect gate="A" pin="!CS" pad="1"/>
<connect gate="A" pin="!HOLD" pad="7"/>
<connect gate="A" pin="!WP" pad="3"/>
<connect gate="A" pin="GND" pad="9"/>
<connect gate="A" pin="GND_2" pad="4"/>
<connect gate="A" pin="SCK" pad="6"/>
<connect gate="A" pin="SI" pad="5"/>
<connect gate="A" pin="SO" pad="2"/>
<connect gate="A" pin="VCC" pad="8"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="AT25XE041B-MHNHR-T"/>
<attribute name="MFR_NAME" value="Adesto Technologies"/>
</technology>
</technologies>
</device>
<device name="UDFN8_8MA1_ADO-L" package="UDFN8_8MA1_ADO-L">
<connects>
<connect gate="A" pin="!CS" pad="1"/>
<connect gate="A" pin="!HOLD" pad="7"/>
<connect gate="A" pin="!WP" pad="3"/>
<connect gate="A" pin="GND" pad="9"/>
<connect gate="A" pin="GND_2" pad="4"/>
<connect gate="A" pin="SCK" pad="6"/>
<connect gate="A" pin="SI" pad="5"/>
<connect gate="A" pin="SO" pad="2"/>
<connect gate="A" pin="VCC" pad="8"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="AT25XE041B-MHNHR-T"/>
<attribute name="MFR_NAME" value="Adesto Technologies"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="CX3225SB25000D0FLJZ1" prefix="XTAL">
<gates>
<gate name="A" symbol="XTAL4_CX3225SB"/>
</gates>
<devices>
<device name="" package="XTAL4_CX3225SB_AVX">
<connects>
<connect gate="A" pin="GND" pad="4"/>
<connect gate="A" pin="GND_2" pad="2"/>
<connect gate="A" pin="HOT" pad="3"/>
<connect gate="A" pin="HOT_2" pad="1"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="CX3225SB25000D0FLJZ1"/>
<attribute name="MFR_NAME" value="KYOCERA AVX"/>
</technology>
</technologies>
</device>
<device name="XTAL4_CX3225SB_AVX-M" package="XTAL4_CX3225SB_AVX-M">
<connects>
<connect gate="A" pin="GND" pad="4"/>
<connect gate="A" pin="GND_2" pad="2"/>
<connect gate="A" pin="HOT" pad="3"/>
<connect gate="A" pin="HOT_2" pad="1"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="CX3225SB25000D0FLJZ1"/>
<attribute name="MFR_NAME" value="KYOCERA AVX"/>
</technology>
</technologies>
</device>
<device name="XTAL4_CX3225SB_AVX-L" package="XTAL4_CX3225SB_AVX-L">
<connects>
<connect gate="A" pin="GND" pad="4"/>
<connect gate="A" pin="GND_2" pad="2"/>
<connect gate="A" pin="HOT" pad="3"/>
<connect gate="A" pin="HOT_2" pad="1"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="CX3225SB25000D0FLJZ1"/>
<attribute name="MFR_NAME" value="KYOCERA AVX"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="NX3225GD-8MHZ-STD-CRA-3" prefix="XTAL">
<gates>
<gate name="A" symbol="CRYSTALH"/>
</gates>
<devices>
<device name="" package="XTAL_NX3225GD-8MHZ-STD-CRA-3_N">
<connects>
<connect gate="A" pin="1" pad="1"/>
<connect gate="A" pin="2" pad="2"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="NX3225GD-8MHZ-STD-CRA-3"/>
<attribute name="MFR_NAME" value="NDK"/>
</technology>
</technologies>
</device>
<device name="XTAL_NX3225GD-8MHZ-STD-CRA-300" package="XTAL_NX3225GD-8MHZ-STD-CRA-300">
<connects>
<connect gate="A" pin="1" pad="1"/>
<connect gate="A" pin="2" pad="2"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="NX3225GD-8MHZ-STD-CRA-3"/>
<attribute name="MFR_NAME" value="NDK"/>
</technology>
</technologies>
</device>
<device name="XTAL_NX3225GD-8MHZ-STD-CRA-301" package="XTAL_NX3225GD-8MHZ-STD-CRA-301">
<connects>
<connect gate="A" pin="1" pad="1"/>
<connect gate="A" pin="2" pad="2"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="NX3225GD-8MHZ-STD-CRA-3"/>
<attribute name="MFR_NAME" value="NDK"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="NX2520SA-16MHZ-STD-CSW-4" prefix="XTAL">
<gates>
<gate name="A" symbol="XTAL_1-3_2-4GND"/>
</gates>
<devices>
<device name="" package="NX2520SA_NDK">
<connects>
<connect gate="A" pin="1" pad="1"/>
<connect gate="A" pin="2" pad="2"/>
<connect gate="A" pin="3" pad="3"/>
<connect gate="A" pin="4" pad="4"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="NX2520SA-16MHZ-STD-CSW-4"/>
<attribute name="MFR_NAME" value="NDK"/>
</technology>
</technologies>
</device>
<device name="NX2520SA_NDK-M" package="NX2520SA_NDK-M">
<connects>
<connect gate="A" pin="1" pad="1"/>
<connect gate="A" pin="2" pad="2"/>
<connect gate="A" pin="3" pad="3"/>
<connect gate="A" pin="4" pad="4"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="NX2520SA-16MHZ-STD-CSW-4"/>
<attribute name="MFR_NAME" value="NDK"/>
</technology>
</technologies>
</device>
<device name="NX2520SA_NDK-L" package="NX2520SA_NDK-L">
<connects>
<connect gate="A" pin="1" pad="1"/>
<connect gate="A" pin="2" pad="2"/>
<connect gate="A" pin="3" pad="3"/>
<connect gate="A" pin="4" pad="4"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="NX2520SA-16MHZ-STD-CSW-4"/>
<attribute name="MFR_NAME" value="NDK"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="ADS1115LIDGSR" prefix="U">
<gates>
<gate name="A" symbol="ADS1115LIDGSR"/>
</gates>
<devices>
<device name="" package="VSSOP10_DGS_TEX">
<connects>
<connect gate="A" pin="ADDR" pad="1"/>
<connect gate="A" pin="AIN0" pad="4"/>
<connect gate="A" pin="AIN1" pad="5"/>
<connect gate="A" pin="AIN2" pad="6"/>
<connect gate="A" pin="AIN3" pad="7"/>
<connect gate="A" pin="ALERT/RDY" pad="2"/>
<connect gate="A" pin="GND" pad="3"/>
<connect gate="A" pin="SCL" pad="10"/>
<connect gate="A" pin="SDA" pad="9"/>
<connect gate="A" pin="VDD" pad="8"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="ADS1115LIDGSR"/>
<attribute name="MFR_NAME" value="Texas Instruments"/>
<attribute name="TYPE" value="Data Acquisition"/>
</technology>
</technologies>
</device>
<device name="VSSOP10_DGS_TEX-M" package="VSSOP10_DGS_TEX-M">
<connects>
<connect gate="A" pin="ADDR" pad="1"/>
<connect gate="A" pin="AIN0" pad="4"/>
<connect gate="A" pin="AIN1" pad="5"/>
<connect gate="A" pin="AIN2" pad="6"/>
<connect gate="A" pin="AIN3" pad="7"/>
<connect gate="A" pin="ALERT/RDY" pad="2"/>
<connect gate="A" pin="GND" pad="3"/>
<connect gate="A" pin="SCL" pad="10"/>
<connect gate="A" pin="SDA" pad="9"/>
<connect gate="A" pin="VDD" pad="8"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="ADS1115LIDGSR"/>
<attribute name="MFR_NAME" value="Texas Instruments"/>
<attribute name="TYPE" value="Data Acquisition"/>
</technology>
</technologies>
</device>
<device name="VSSOP10_DGS_TEX-L" package="VSSOP10_DGS_TEX-L">
<connects>
<connect gate="A" pin="ADDR" pad="1"/>
<connect gate="A" pin="AIN0" pad="4"/>
<connect gate="A" pin="AIN1" pad="5"/>
<connect gate="A" pin="AIN2" pad="6"/>
<connect gate="A" pin="AIN3" pad="7"/>
<connect gate="A" pin="ALERT/RDY" pad="2"/>
<connect gate="A" pin="GND" pad="3"/>
<connect gate="A" pin="SCL" pad="10"/>
<connect gate="A" pin="SDA" pad="9"/>
<connect gate="A" pin="VDD" pad="8"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="ADS1115LIDGSR"/>
<attribute name="MFR_NAME" value="Texas Instruments"/>
<attribute name="TYPE" value="Data Acquisition"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="MT25QL01GBBB8E12-0AUT" prefix="U">
<gates>
<gate name="A" symbol="MT25QL01GBBB8E12-0AUT"/>
</gates>
<devices>
<device name="" package="BGA24_MT25QL_MRN">
<connects>
<connect gate="A" pin="C" pad="B2"/>
<connect gate="A" pin="DQ0" pad="D3"/>
<connect gate="A" pin="DQ1" pad="D2"/>
<connect gate="A" pin="DQ3/HOLD" pad="D4"/>
<connect gate="A" pin="NC" pad="A2"/>
<connect gate="A" pin="RESET" pad="A4"/>
<connect gate="A" pin="RFU" pad="E5"/>
<connect gate="A" pin="RFU_10" pad="D5"/>
<connect gate="A" pin="RFU_11" pad="E1"/>
<connect gate="A" pin="RFU_12" pad="E2"/>
<connect gate="A" pin="RFU_13" pad="E3"/>
<connect gate="A" pin="RFU_14" pad="E4"/>
<connect gate="A" pin="RFU_2" pad="A3"/>
<connect gate="A" pin="RFU_3" pad="A5"/>
<connect gate="A" pin="RFU_4" pad="B1"/>
<connect gate="A" pin="RFU_5" pad="B5"/>
<connect gate="A" pin="RFU_6" pad="C1"/>
<connect gate="A" pin="RFU_7" pad="C3"/>
<connect gate="A" pin="RFU_8" pad="C5"/>
<connect gate="A" pin="RFU_9" pad="D1"/>
<connect gate="A" pin="S" pad="C2"/>
<connect gate="A" pin="VCC" pad="B4"/>
<connect gate="A" pin="VSS" pad="B3"/>
<connect gate="A" pin="W/DQ2" pad="C4"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="MT25QL01GBBB8E12-0AUT"/>
<attribute name="MFR_NAME" value="Micron"/>
</technology>
</technologies>
</device>
<device name="BGA24_MT25QL_MRN-M" package="BGA24_MT25QL_MRN-M">
<connects>
<connect gate="A" pin="C" pad="B2"/>
<connect gate="A" pin="DQ0" pad="D3"/>
<connect gate="A" pin="DQ1" pad="D2"/>
<connect gate="A" pin="DQ3/HOLD" pad="D4"/>
<connect gate="A" pin="NC" pad="A2"/>
<connect gate="A" pin="RESET" pad="A4"/>
<connect gate="A" pin="RFU" pad="E5"/>
<connect gate="A" pin="RFU_10" pad="D5"/>
<connect gate="A" pin="RFU_11" pad="E1"/>
<connect gate="A" pin="RFU_12" pad="E2"/>
<connect gate="A" pin="RFU_13" pad="E3"/>
<connect gate="A" pin="RFU_14" pad="E4"/>
<connect gate="A" pin="RFU_2" pad="A3"/>
<connect gate="A" pin="RFU_3" pad="A5"/>
<connect gate="A" pin="RFU_4" pad="B1"/>
<connect gate="A" pin="RFU_5" pad="B5"/>
<connect gate="A" pin="RFU_6" pad="C1"/>
<connect gate="A" pin="RFU_7" pad="C3"/>
<connect gate="A" pin="RFU_8" pad="C5"/>
<connect gate="A" pin="RFU_9" pad="D1"/>
<connect gate="A" pin="S" pad="C2"/>
<connect gate="A" pin="VCC" pad="B4"/>
<connect gate="A" pin="VSS" pad="B3"/>
<connect gate="A" pin="W/DQ2" pad="C4"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="MT25QL01GBBB8E12-0AUT"/>
<attribute name="MFR_NAME" value="Micron"/>
</technology>
</technologies>
</device>
<device name="BGA24_MT25QL_MRN-L" package="BGA24_MT25QL_MRN-L">
<connects>
<connect gate="A" pin="C" pad="B2"/>
<connect gate="A" pin="DQ0" pad="D3"/>
<connect gate="A" pin="DQ1" pad="D2"/>
<connect gate="A" pin="DQ3/HOLD" pad="D4"/>
<connect gate="A" pin="NC" pad="A2"/>
<connect gate="A" pin="RESET" pad="A4"/>
<connect gate="A" pin="RFU" pad="E5"/>
<connect gate="A" pin="RFU_10" pad="D5"/>
<connect gate="A" pin="RFU_11" pad="E1"/>
<connect gate="A" pin="RFU_12" pad="E2"/>
<connect gate="A" pin="RFU_13" pad="E3"/>
<connect gate="A" pin="RFU_14" pad="E4"/>
<connect gate="A" pin="RFU_2" pad="A3"/>
<connect gate="A" pin="RFU_3" pad="A5"/>
<connect gate="A" pin="RFU_4" pad="B1"/>
<connect gate="A" pin="RFU_5" pad="B5"/>
<connect gate="A" pin="RFU_6" pad="C1"/>
<connect gate="A" pin="RFU_7" pad="C3"/>
<connect gate="A" pin="RFU_8" pad="C5"/>
<connect gate="A" pin="RFU_9" pad="D1"/>
<connect gate="A" pin="S" pad="C2"/>
<connect gate="A" pin="VCC" pad="B4"/>
<connect gate="A" pin="VSS" pad="B3"/>
<connect gate="A" pin="W/DQ2" pad="C4"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="MT25QL01GBBB8E12-0AUT"/>
<attribute name="MFR_NAME" value="Micron"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="CONMHF1-SMD-G-T" prefix="J">
<gates>
<gate name="A" symbol="CONN_COAX_3GND_1"/>
</gates>
<devices>
<device name="" package="COAX3_CONMHF1-SMD-G-T_TEC">
<connects>
<connect gate="A" pin="GND" pad="4"/>
<connect gate="A" pin="GND_2" pad="2"/>
<connect gate="A" pin="GND_3" pad="3"/>
<connect gate="A" pin="SIGNAL" pad="1"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="CONMHF1-SMD-G-T"/>
<attribute name="MFR_NAME" value="TE Connectivity"/>
<attribute name="TYPE" value="Coaxial Connectors(RF) Assemblies"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="483910003" prefix="J">
<gates>
<gate name="A" symbol="CONN_483910003"/>
</gates>
<devices>
<device name="" package="CONN_483910003_MOL">
<connects>
<connect gate="A" pin="D+" pad="3"/>
<connect gate="A" pin="D-" pad="2"/>
<connect gate="A" pin="GND" pad="4"/>
<connect gate="A" pin="GND_DRAIN" pad="7"/>
<connect gate="A" pin="STDA_SSRX+" pad="6"/>
<connect gate="A" pin="STDA_SSRX-" pad="5"/>
<connect gate="A" pin="STDA_SSTX+" pad="9"/>
<connect gate="A" pin="STDA_SSTX-" pad="8"/>
<connect gate="A" pin="VBUS" pad="1"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="483910003"/>
<attribute name="MFR_NAME" value="Molex Connector Corporation"/>
<attribute name="TYPE" value="USB, DVI, HDMI, Connectors"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="484050003" prefix="J">
<gates>
<gate name="A" symbol="484050003"/>
</gates>
<devices>
<device name="" package="484050003_MOL">
<connects>
<connect gate="A" pin="D+" pad="3"/>
<connect gate="A" pin="D-" pad="2"/>
<connect gate="A" pin="GND" pad="4"/>
<connect gate="A" pin="GND_DRAIN" pad="7"/>
<connect gate="A" pin="STDA_SSRX+" pad="6"/>
<connect gate="A" pin="STDA_SSRX-" pad="5"/>
<connect gate="A" pin="STDA_SSTX+" pad="9"/>
<connect gate="A" pin="STDA_SSTX-" pad="8"/>
<connect gate="A" pin="VBUS" pad="1"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="484050003"/>
<attribute name="MFR_NAME" value="Molex Connector Corporation"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="AD9203ARUZ" prefix="U">
<gates>
<gate name="A" symbol="AD9203ARUZ"/>
</gates>
<devices>
<device name="" package="RU_28_ADI">
<connects>
<connect gate="A" pin="3-STATE" pad="16"/>
<connect gate="A" pin="AINN" pad="26"/>
<connect gate="A" pin="AINP" pad="25"/>
<connect gate="A" pin="AVDD" pad="28"/>
<connect gate="A" pin="AVSS" pad="27"/>
<connect gate="A" pin="CLAMP" pad="19"/>
<connect gate="A" pin="CLAMPIN" pad="20"/>
<connect gate="A" pin="CLK" pad="15"/>
<connect gate="A" pin="D0" pad="3"/>
<connect gate="A" pin="D1" pad="4"/>
<connect gate="A" pin="D2" pad="5"/>
<connect gate="A" pin="D3" pad="6"/>
<connect gate="A" pin="D4" pad="7"/>
<connect gate="A" pin="D5" pad="8"/>
<connect gate="A" pin="D6" pad="9"/>
<connect gate="A" pin="D7" pad="10"/>
<connect gate="A" pin="D8" pad="11"/>
<connect gate="A" pin="D9" pad="12"/>
<connect gate="A" pin="DFS" pad="14"/>
<connect gate="A" pin="DRVDD" pad="2"/>
<connect gate="A" pin="DRVSS" pad="1"/>
<connect gate="A" pin="OTR" pad="13"/>
<connect gate="A" pin="PWRCON" pad="21"/>
<connect gate="A" pin="REFBF" pad="24"/>
<connect gate="A" pin="REFSENSE" pad="18"/>
<connect gate="A" pin="REFTF" pad="22"/>
<connect gate="A" pin="STBY" pad="17"/>
<connect gate="A" pin="VREF" pad="23"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="AD9203ARUZ"/>
<attribute name="MFR_NAME" value="Analog Devices Inc"/>
</technology>
</technologies>
</device>
<device name="RU_28_ADI-M" package="RU_28_ADI-M">
<connects>
<connect gate="A" pin="3-STATE" pad="16"/>
<connect gate="A" pin="AINN" pad="26"/>
<connect gate="A" pin="AINP" pad="25"/>
<connect gate="A" pin="AVDD" pad="28"/>
<connect gate="A" pin="AVSS" pad="27"/>
<connect gate="A" pin="CLAMP" pad="19"/>
<connect gate="A" pin="CLAMPIN" pad="20"/>
<connect gate="A" pin="CLK" pad="15"/>
<connect gate="A" pin="D0" pad="3"/>
<connect gate="A" pin="D1" pad="4"/>
<connect gate="A" pin="D2" pad="5"/>
<connect gate="A" pin="D3" pad="6"/>
<connect gate="A" pin="D4" pad="7"/>
<connect gate="A" pin="D5" pad="8"/>
<connect gate="A" pin="D6" pad="9"/>
<connect gate="A" pin="D7" pad="10"/>
<connect gate="A" pin="D8" pad="11"/>
<connect gate="A" pin="D9" pad="12"/>
<connect gate="A" pin="DFS" pad="14"/>
<connect gate="A" pin="DRVDD" pad="2"/>
<connect gate="A" pin="DRVSS" pad="1"/>
<connect gate="A" pin="OTR" pad="13"/>
<connect gate="A" pin="PWRCON" pad="21"/>
<connect gate="A" pin="REFBF" pad="24"/>
<connect gate="A" pin="REFSENSE" pad="18"/>
<connect gate="A" pin="REFTF" pad="22"/>
<connect gate="A" pin="STBY" pad="17"/>
<connect gate="A" pin="VREF" pad="23"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="AD9203ARUZ"/>
<attribute name="MFR_NAME" value="Analog Devices Inc"/>
</technology>
</technologies>
</device>
<device name="RU_28_ADI-L" package="RU_28_ADI-L">
<connects>
<connect gate="A" pin="3-STATE" pad="16"/>
<connect gate="A" pin="AINN" pad="26"/>
<connect gate="A" pin="AINP" pad="25"/>
<connect gate="A" pin="AVDD" pad="28"/>
<connect gate="A" pin="AVSS" pad="27"/>
<connect gate="A" pin="CLAMP" pad="19"/>
<connect gate="A" pin="CLAMPIN" pad="20"/>
<connect gate="A" pin="CLK" pad="15"/>
<connect gate="A" pin="D0" pad="3"/>
<connect gate="A" pin="D1" pad="4"/>
<connect gate="A" pin="D2" pad="5"/>
<connect gate="A" pin="D3" pad="6"/>
<connect gate="A" pin="D4" pad="7"/>
<connect gate="A" pin="D5" pad="8"/>
<connect gate="A" pin="D6" pad="9"/>
<connect gate="A" pin="D7" pad="10"/>
<connect gate="A" pin="D8" pad="11"/>
<connect gate="A" pin="D9" pad="12"/>
<connect gate="A" pin="DFS" pad="14"/>
<connect gate="A" pin="DRVDD" pad="2"/>
<connect gate="A" pin="DRVSS" pad="1"/>
<connect gate="A" pin="OTR" pad="13"/>
<connect gate="A" pin="PWRCON" pad="21"/>
<connect gate="A" pin="REFBF" pad="24"/>
<connect gate="A" pin="REFSENSE" pad="18"/>
<connect gate="A" pin="REFTF" pad="22"/>
<connect gate="A" pin="STBY" pad="17"/>
<connect gate="A" pin="VREF" pad="23"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="AD9203ARUZ"/>
<attribute name="MFR_NAME" value="Analog Devices Inc"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="AD8028ARM-REEL7" prefix="U">
<gates>
<gate name="A" symbol="AD8028ARM-REEL7"/>
</gates>
<devices>
<device name="" package="RM_10_ADI">
<connects>
<connect gate="A" pin="+INA" pad="3"/>
<connect gate="A" pin="+INB" pad="7"/>
<connect gate="A" pin="+VS" pad="10"/>
<connect gate="A" pin="-INA" pad="2"/>
<connect gate="A" pin="-INB" pad="8"/>
<connect gate="A" pin="-VS" pad="4"/>
<connect gate="A" pin="DISABLE!/SELECTA" pad="5"/>
<connect gate="A" pin="DISABLE!/SELECTB" pad="6"/>
<connect gate="A" pin="VOUTA" pad="1"/>
<connect gate="A" pin="VOUTB" pad="9"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="AD8028ARM-REEL7"/>
<attribute name="MFR_NAME" value="Analog Devices Inc"/>
</technology>
</technologies>
</device>
<device name="RM_10_ADI-M" package="RM_10_ADI-M">
<connects>
<connect gate="A" pin="+INA" pad="3"/>
<connect gate="A" pin="+INB" pad="7"/>
<connect gate="A" pin="+VS" pad="10"/>
<connect gate="A" pin="-INA" pad="2"/>
<connect gate="A" pin="-INB" pad="8"/>
<connect gate="A" pin="-VS" pad="4"/>
<connect gate="A" pin="DISABLE!/SELECTA" pad="5"/>
<connect gate="A" pin="DISABLE!/SELECTB" pad="6"/>
<connect gate="A" pin="VOUTA" pad="1"/>
<connect gate="A" pin="VOUTB" pad="9"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="AD8028ARM-REEL7"/>
<attribute name="MFR_NAME" value="Analog Devices Inc"/>
</technology>
</technologies>
</device>
<device name="RM_10_ADI-L" package="RM_10_ADI-L">
<connects>
<connect gate="A" pin="+INA" pad="3"/>
<connect gate="A" pin="+INB" pad="7"/>
<connect gate="A" pin="+VS" pad="10"/>
<connect gate="A" pin="-INA" pad="2"/>
<connect gate="A" pin="-INB" pad="8"/>
<connect gate="A" pin="-VS" pad="4"/>
<connect gate="A" pin="DISABLE!/SELECTA" pad="5"/>
<connect gate="A" pin="DISABLE!/SELECTB" pad="6"/>
<connect gate="A" pin="VOUTA" pad="1"/>
<connect gate="A" pin="VOUTB" pad="9"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="AD8028ARM-REEL7"/>
<attribute name="MFR_NAME" value="Analog Devices Inc"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="LM2662MX/NOPB" prefix="U">
<gates>
<gate name="A" symbol="LM2662M"/>
</gates>
<devices>
<device name="" package="M08A">
<connects>
<connect gate="A" pin="C1+" pad="2"/>
<connect gate="A" pin="C1-" pad="4"/>
<connect gate="A" pin="FC" pad="1"/>
<connect gate="A" pin="GND" pad="3"/>
<connect gate="A" pin="LV" pad="6"/>
<connect gate="A" pin="OSC" pad="7"/>
<connect gate="A" pin="OUT" pad="5"/>
<connect gate="A" pin="V+" pad="8"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="LM2662MX/NOPB"/>
<attribute name="MFR_NAME" value="Texas Instruments"/>
<attribute name="TYPE" value="LM2662M"/>
</technology>
</technologies>
</device>
<device name="M08A-M" package="M08A-M">
<connects>
<connect gate="A" pin="C1+" pad="2"/>
<connect gate="A" pin="C1-" pad="4"/>
<connect gate="A" pin="FC" pad="1"/>
<connect gate="A" pin="GND" pad="3"/>
<connect gate="A" pin="LV" pad="6"/>
<connect gate="A" pin="OSC" pad="7"/>
<connect gate="A" pin="OUT" pad="5"/>
<connect gate="A" pin="V+" pad="8"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="LM2662MX/NOPB"/>
<attribute name="MFR_NAME" value="Texas Instruments"/>
<attribute name="TYPE" value="LM2662M"/>
</technology>
</technologies>
</device>
<device name="M08A-L" package="M08A-L">
<connects>
<connect gate="A" pin="C1+" pad="2"/>
<connect gate="A" pin="C1-" pad="4"/>
<connect gate="A" pin="FC" pad="1"/>
<connect gate="A" pin="GND" pad="3"/>
<connect gate="A" pin="LV" pad="6"/>
<connect gate="A" pin="OSC" pad="7"/>
<connect gate="A" pin="OUT" pad="5"/>
<connect gate="A" pin="V+" pad="8"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="LM2662MX/NOPB"/>
<attribute name="MFR_NAME" value="Texas Instruments"/>
<attribute name="TYPE" value="LM2662M"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="MAX2829ETN+" prefix="U">
<gates>
<gate name="A" symbol="MAX2829ETN+"/>
</gates>
<devices>
<device name="" package="21-0135_T5688+2_MXM">
<connects>
<connect gate="A" pin="!CS" pad="28"/>
<connect gate="A" pin="!SHDN" pad="39"/>
<connect gate="A" pin="B1" pad="48"/>
<connect gate="A" pin="B2" pad="50"/>
<connect gate="A" pin="B3" pad="53"/>
<connect gate="A" pin="B4" pad="54"/>
<connect gate="A" pin="B5" pad="56"/>
<connect gate="A" pin="B6" pad="1"/>
<connect gate="A" pin="B7" pad="3"/>
<connect gate="A" pin="BYPASS" pad="37"/>
<connect gate="A" pin="CPOUT" pad="33"/>
<connect gate="A" pin="DIN" pad="26"/>
<connect gate="A" pin="EPAD" pad="57"/>
<connect gate="A" pin="GND" pad="51"/>
<connect gate="A" pin="GND_2" pad="5"/>
<connect gate="A" pin="GND_3" pad="7"/>
<connect gate="A" pin="GND_4" pad="24"/>
<connect gate="A" pin="GND_5" pad="32"/>
<connect gate="A" pin="GND_6" pad="34"/>
<connect gate="A" pin="GND_7" pad="35"/>
<connect gate="A" pin="LD" pad="29"/>
<connect gate="A" pin="PABIAS" pad="14"/>
<connect gate="A" pin="RBIAS" pad="21"/>
<connect gate="A" pin="ROSC" pad="30"/>
<connect gate="A" pin="RSSI" pad="40"/>
<connect gate="A" pin="RXBBI+" pad="46"/>
<connect gate="A" pin="RXBBI-" pad="45"/>
<connect gate="A" pin="RXBBQ+" pad="44"/>
<connect gate="A" pin="RXBBQ-" pad="43"/>
<connect gate="A" pin="RXENA" pad="41"/>
<connect gate="A" pin="RXHP" pad="42"/>
<connect gate="A" pin="RXRFH" pad="6"/>
<connect gate="A" pin="RXRFL" pad="4"/>
<connect gate="A" pin="SCLK" pad="27"/>
<connect gate="A" pin="TUNE" pad="36"/>
<connect gate="A" pin="TXBBI+" pad="16"/>
<connect gate="A" pin="TXBBI-" pad="17"/>
<connect gate="A" pin="TXBBQ+" pad="18"/>
<connect gate="A" pin="TXBBQ-" pad="19"/>
<connect gate="A" pin="TXENA" pad="13"/>
<connect gate="A" pin="TXRFH+" pad="8"/>
<connect gate="A" pin="TXRFH-" pad="9"/>
<connect gate="A" pin="TXRFL+" pad="11"/>
<connect gate="A" pin="TXRFL-" pad="12"/>
<connect gate="A" pin="VCC" pad="55"/>
<connect gate="A" pin="VCC_10" pad="47"/>
<connect gate="A" pin="VCC_11" pad="49"/>
<connect gate="A" pin="VCC_12" pad="52"/>
<connect gate="A" pin="VCC_2" pad="2"/>
<connect gate="A" pin="VCC_3" pad="10"/>
<connect gate="A" pin="VCC_4" pad="15"/>
<connect gate="A" pin="VCC_5" pad="20"/>
<connect gate="A" pin="VCC_6" pad="22"/>
<connect gate="A" pin="VCC_7" pad="25"/>
<connect gate="A" pin="VCC_8" pad="31"/>
<connect gate="A" pin="VCC_9" pad="38"/>
<connect gate="A" pin="VREF" pad="23"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="MAX2829ETN+"/>
<attribute name="MFR_NAME" value="Analog Devices Inc"/>
</technology>
</technologies>
</device>
<device name="21-0135_T5688+2_MXM-M" package="21-0135_T5688+2_MXM-M">
<connects>
<connect gate="A" pin="!CS" pad="28"/>
<connect gate="A" pin="!SHDN" pad="39"/>
<connect gate="A" pin="B1" pad="48"/>
<connect gate="A" pin="B2" pad="50"/>
<connect gate="A" pin="B3" pad="53"/>
<connect gate="A" pin="B4" pad="54"/>
<connect gate="A" pin="B5" pad="56"/>
<connect gate="A" pin="B6" pad="1"/>
<connect gate="A" pin="B7" pad="3"/>
<connect gate="A" pin="BYPASS" pad="37"/>
<connect gate="A" pin="CPOUT" pad="33"/>
<connect gate="A" pin="DIN" pad="26"/>
<connect gate="A" pin="EPAD" pad="57"/>
<connect gate="A" pin="GND" pad="51"/>
<connect gate="A" pin="GND_2" pad="5"/>
<connect gate="A" pin="GND_3" pad="7"/>
<connect gate="A" pin="GND_4" pad="24"/>
<connect gate="A" pin="GND_5" pad="32"/>
<connect gate="A" pin="GND_6" pad="34"/>
<connect gate="A" pin="GND_7" pad="35"/>
<connect gate="A" pin="LD" pad="29"/>
<connect gate="A" pin="PABIAS" pad="14"/>
<connect gate="A" pin="RBIAS" pad="21"/>
<connect gate="A" pin="ROSC" pad="30"/>
<connect gate="A" pin="RSSI" pad="40"/>
<connect gate="A" pin="RXBBI+" pad="46"/>
<connect gate="A" pin="RXBBI-" pad="45"/>
<connect gate="A" pin="RXBBQ+" pad="44"/>
<connect gate="A" pin="RXBBQ-" pad="43"/>
<connect gate="A" pin="RXENA" pad="41"/>
<connect gate="A" pin="RXHP" pad="42"/>
<connect gate="A" pin="RXRFH" pad="6"/>
<connect gate="A" pin="RXRFL" pad="4"/>
<connect gate="A" pin="SCLK" pad="27"/>
<connect gate="A" pin="TUNE" pad="36"/>
<connect gate="A" pin="TXBBI+" pad="16"/>
<connect gate="A" pin="TXBBI-" pad="17"/>
<connect gate="A" pin="TXBBQ+" pad="18"/>
<connect gate="A" pin="TXBBQ-" pad="19"/>
<connect gate="A" pin="TXENA" pad="13"/>
<connect gate="A" pin="TXRFH+" pad="8"/>
<connect gate="A" pin="TXRFH-" pad="9"/>
<connect gate="A" pin="TXRFL+" pad="11"/>
<connect gate="A" pin="TXRFL-" pad="12"/>
<connect gate="A" pin="VCC" pad="55"/>
<connect gate="A" pin="VCC_10" pad="47"/>
<connect gate="A" pin="VCC_11" pad="49"/>
<connect gate="A" pin="VCC_12" pad="52"/>
<connect gate="A" pin="VCC_2" pad="2"/>
<connect gate="A" pin="VCC_3" pad="10"/>
<connect gate="A" pin="VCC_4" pad="15"/>
<connect gate="A" pin="VCC_5" pad="20"/>
<connect gate="A" pin="VCC_6" pad="22"/>
<connect gate="A" pin="VCC_7" pad="25"/>
<connect gate="A" pin="VCC_8" pad="31"/>
<connect gate="A" pin="VCC_9" pad="38"/>
<connect gate="A" pin="VREF" pad="23"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="MAX2829ETN+"/>
<attribute name="MFR_NAME" value="Analog Devices Inc"/>
</technology>
</technologies>
</device>
<device name="21-0135_T5688+2_MXM-L" package="21-0135_T5688+2_MXM-L">
<connects>
<connect gate="A" pin="!CS" pad="28"/>
<connect gate="A" pin="!SHDN" pad="39"/>
<connect gate="A" pin="B1" pad="48"/>
<connect gate="A" pin="B2" pad="50"/>
<connect gate="A" pin="B3" pad="53"/>
<connect gate="A" pin="B4" pad="54"/>
<connect gate="A" pin="B5" pad="56"/>
<connect gate="A" pin="B6" pad="1"/>
<connect gate="A" pin="B7" pad="3"/>
<connect gate="A" pin="BYPASS" pad="37"/>
<connect gate="A" pin="CPOUT" pad="33"/>
<connect gate="A" pin="DIN" pad="26"/>
<connect gate="A" pin="EPAD" pad="57"/>
<connect gate="A" pin="GND" pad="51"/>
<connect gate="A" pin="GND_2" pad="5"/>
<connect gate="A" pin="GND_3" pad="7"/>
<connect gate="A" pin="GND_4" pad="24"/>
<connect gate="A" pin="GND_5" pad="32"/>
<connect gate="A" pin="GND_6" pad="34"/>
<connect gate="A" pin="GND_7" pad="35"/>
<connect gate="A" pin="LD" pad="29"/>
<connect gate="A" pin="PABIAS" pad="14"/>
<connect gate="A" pin="RBIAS" pad="21"/>
<connect gate="A" pin="ROSC" pad="30"/>
<connect gate="A" pin="RSSI" pad="40"/>
<connect gate="A" pin="RXBBI+" pad="46"/>
<connect gate="A" pin="RXBBI-" pad="45"/>
<connect gate="A" pin="RXBBQ+" pad="44"/>
<connect gate="A" pin="RXBBQ-" pad="43"/>
<connect gate="A" pin="RXENA" pad="41"/>
<connect gate="A" pin="RXHP" pad="42"/>
<connect gate="A" pin="RXRFH" pad="6"/>
<connect gate="A" pin="RXRFL" pad="4"/>
<connect gate="A" pin="SCLK" pad="27"/>
<connect gate="A" pin="TUNE" pad="36"/>
<connect gate="A" pin="TXBBI+" pad="16"/>
<connect gate="A" pin="TXBBI-" pad="17"/>
<connect gate="A" pin="TXBBQ+" pad="18"/>
<connect gate="A" pin="TXBBQ-" pad="19"/>
<connect gate="A" pin="TXENA" pad="13"/>
<connect gate="A" pin="TXRFH+" pad="8"/>
<connect gate="A" pin="TXRFH-" pad="9"/>
<connect gate="A" pin="TXRFL+" pad="11"/>
<connect gate="A" pin="TXRFL-" pad="12"/>
<connect gate="A" pin="VCC" pad="55"/>
<connect gate="A" pin="VCC_10" pad="47"/>
<connect gate="A" pin="VCC_11" pad="49"/>
<connect gate="A" pin="VCC_12" pad="52"/>
<connect gate="A" pin="VCC_2" pad="2"/>
<connect gate="A" pin="VCC_3" pad="10"/>
<connect gate="A" pin="VCC_4" pad="15"/>
<connect gate="A" pin="VCC_5" pad="20"/>
<connect gate="A" pin="VCC_6" pad="22"/>
<connect gate="A" pin="VCC_7" pad="25"/>
<connect gate="A" pin="VCC_8" pad="31"/>
<connect gate="A" pin="VCC_9" pad="38"/>
<connect gate="A" pin="VREF" pad="23"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="MAX2829ETN+"/>
<attribute name="MFR_NAME" value="Analog Devices Inc"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="QPA9501TR13" prefix="U">
<gates>
<gate name="A" symbol="QPA9501SR"/>
</gates>
<devices>
<device name="" package="QFN20_9501_4X4-0P5_QOR">
<connects>
<connect gate="A" pin="DET" pad="10"/>
<connect gate="A" pin="DET_ALT" pad="7"/>
<connect gate="A" pin="GND" pad="17"/>
<connect gate="A" pin="GND_2" pad="2"/>
<connect gate="A" pin="GND_3" pad="4"/>
<connect gate="A" pin="GND_4" pad="11"/>
<connect gate="A" pin="GND_5" pad="12"/>
<connect gate="A" pin="GND_6" pad="14"/>
<connect gate="A" pin="GND_7" pad="15"/>
<connect gate="A" pin="GND_8" pad="16"/>
<connect gate="A" pin="NC" pad="8"/>
<connect gate="A" pin="NC_2" pad="1"/>
<connect gate="A" pin="NC_3" pad="6"/>
<connect gate="A" pin="PA_EN" pad="5"/>
<connect gate="A" pin="RF/DCGND" pad="21"/>
<connect gate="A" pin="RF_IN" pad="3"/>
<connect gate="A" pin="RF_OUT" pad="13"/>
<connect gate="A" pin="VCC1" pad="20"/>
<connect gate="A" pin="VCC2" pad="19"/>
<connect gate="A" pin="VCC3" pad="18"/>
<connect gate="A" pin="VCC3_2" pad="9"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="QPA9501TR13"/>
<attribute name="MFR_NAME" value="Qorvo"/>
<attribute name="TYPE" value="RF Amplifier"/>
</technology>
</technologies>
</device>
<device name="QFN20_9501_4X4-0P5_QOR-M" package="QFN20_9501_4X4-0P5_QOR-M">
<connects>
<connect gate="A" pin="DET" pad="10"/>
<connect gate="A" pin="DET_ALT" pad="7"/>
<connect gate="A" pin="GND" pad="17"/>
<connect gate="A" pin="GND_2" pad="2"/>
<connect gate="A" pin="GND_3" pad="4"/>
<connect gate="A" pin="GND_4" pad="11"/>
<connect gate="A" pin="GND_5" pad="12"/>
<connect gate="A" pin="GND_6" pad="14"/>
<connect gate="A" pin="GND_7" pad="15"/>
<connect gate="A" pin="GND_8" pad="16"/>
<connect gate="A" pin="NC" pad="8"/>
<connect gate="A" pin="NC_2" pad="1"/>
<connect gate="A" pin="NC_3" pad="6"/>
<connect gate="A" pin="PA_EN" pad="5"/>
<connect gate="A" pin="RF/DCGND" pad="21"/>
<connect gate="A" pin="RF_IN" pad="3"/>
<connect gate="A" pin="RF_OUT" pad="13"/>
<connect gate="A" pin="VCC1" pad="20"/>
<connect gate="A" pin="VCC2" pad="19"/>
<connect gate="A" pin="VCC3" pad="18"/>
<connect gate="A" pin="VCC3_2" pad="9"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="QPA9501TR13"/>
<attribute name="MFR_NAME" value="Qorvo"/>
<attribute name="TYPE" value="RF Amplifier"/>
</technology>
</technologies>
</device>
<device name="QFN20_9501_4X4-0P5_QOR-L" package="QFN20_9501_4X4-0P5_QOR-L">
<connects>
<connect gate="A" pin="DET" pad="10"/>
<connect gate="A" pin="DET_ALT" pad="7"/>
<connect gate="A" pin="GND" pad="17"/>
<connect gate="A" pin="GND_2" pad="2"/>
<connect gate="A" pin="GND_3" pad="4"/>
<connect gate="A" pin="GND_4" pad="11"/>
<connect gate="A" pin="GND_5" pad="12"/>
<connect gate="A" pin="GND_6" pad="14"/>
<connect gate="A" pin="GND_7" pad="15"/>
<connect gate="A" pin="GND_8" pad="16"/>
<connect gate="A" pin="NC" pad="8"/>
<connect gate="A" pin="NC_2" pad="1"/>
<connect gate="A" pin="NC_3" pad="6"/>
<connect gate="A" pin="PA_EN" pad="5"/>
<connect gate="A" pin="RF/DCGND" pad="21"/>
<connect gate="A" pin="RF_IN" pad="3"/>
<connect gate="A" pin="RF_OUT" pad="13"/>
<connect gate="A" pin="VCC1" pad="20"/>
<connect gate="A" pin="VCC2" pad="19"/>
<connect gate="A" pin="VCC3" pad="18"/>
<connect gate="A" pin="VCC3_2" pad="9"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="QPA9501TR13"/>
<attribute name="MFR_NAME" value="Qorvo"/>
<attribute name="TYPE" value="RF Amplifier"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="MMZ25332BT1" prefix="U">
<gates>
<gate name="A" symbol="MMZ25332BT1"/>
</gates>
<devices>
<device name="" package="QFN12_FRE">
<connects>
<connect gate="A" pin="HTAB" pad="HTAB"/>
<connect gate="A" pin="N.C" pad="1"/>
<connect gate="A" pin="PDET" pad="10"/>
<connect gate="A" pin="RFIN" pad="3"/>
<connect gate="A" pin="RFIN_2" pad="2"/>
<connect gate="A" pin="VBA1" pad="4"/>
<connect gate="A" pin="VBA2" pad="5"/>
<connect gate="A" pin="VBIAS" pad="6"/>
<connect gate="A" pin="VCC1" pad="12"/>
<connect gate="A" pin="VCC1_2" pad="11"/>
<connect gate="A" pin="VCC2/RFOUT" pad="9"/>
<connect gate="A" pin="VCC2/RFOUT_2" pad="7"/>
<connect gate="A" pin="VCC2/RFOUT_3" pad="8"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="MMZ25332BT1"/>
<attribute name="MFR_NAME" value="NXP"/>
</technology>
</technologies>
</device>
<device name="QFN12_FRE-M" package="QFN12_FRE-M">
<connects>
<connect gate="A" pin="HTAB" pad="HTAB"/>
<connect gate="A" pin="N.C" pad="1"/>
<connect gate="A" pin="PDET" pad="10"/>
<connect gate="A" pin="RFIN" pad="3"/>
<connect gate="A" pin="RFIN_2" pad="2"/>
<connect gate="A" pin="VBA1" pad="4"/>
<connect gate="A" pin="VBA2" pad="5"/>
<connect gate="A" pin="VBIAS" pad="6"/>
<connect gate="A" pin="VCC1" pad="12"/>
<connect gate="A" pin="VCC1_2" pad="11"/>
<connect gate="A" pin="VCC2/RFOUT" pad="9"/>
<connect gate="A" pin="VCC2/RFOUT_2" pad="7"/>
<connect gate="A" pin="VCC2/RFOUT_3" pad="8"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="MMZ25332BT1"/>
<attribute name="MFR_NAME" value="NXP"/>
</technology>
</technologies>
</device>
<device name="QFN12_FRE-L" package="QFN12_FRE-L">
<connects>
<connect gate="A" pin="HTAB" pad="HTAB"/>
<connect gate="A" pin="N.C" pad="1"/>
<connect gate="A" pin="PDET" pad="10"/>
<connect gate="A" pin="RFIN" pad="3"/>
<connect gate="A" pin="RFIN_2" pad="2"/>
<connect gate="A" pin="VBA1" pad="4"/>
<connect gate="A" pin="VBA2" pad="5"/>
<connect gate="A" pin="VBIAS" pad="6"/>
<connect gate="A" pin="VCC1" pad="12"/>
<connect gate="A" pin="VCC1_2" pad="11"/>
<connect gate="A" pin="VCC2/RFOUT" pad="9"/>
<connect gate="A" pin="VCC2/RFOUT_2" pad="7"/>
<connect gate="A" pin="VCC2/RFOUT_3" pad="8"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="MMZ25332BT1"/>
<attribute name="MFR_NAME" value="NXP"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="DF37NC-30DS-0.4V(53)" prefix="J">
<gates>
<gate name="A" symbol="CONN_030P_000C_1"/>
</gates>
<devices>
<device name="" package="CONN_DF37NC-30DS-0.4V(53)_HIR">
<connects>
<connect gate="A" pin="1" pad="1"/>
<connect gate="A" pin="10" pad="10"/>
<connect gate="A" pin="11" pad="11"/>
<connect gate="A" pin="12" pad="12"/>
<connect gate="A" pin="13" pad="13"/>
<connect gate="A" pin="14" pad="14"/>
<connect gate="A" pin="15" pad="15"/>
<connect gate="A" pin="16" pad="16"/>
<connect gate="A" pin="17" pad="17"/>
<connect gate="A" pin="18" pad="18"/>
<connect gate="A" pin="19" pad="19"/>
<connect gate="A" pin="2" pad="2"/>
<connect gate="A" pin="20" pad="20"/>
<connect gate="A" pin="21" pad="21"/>
<connect gate="A" pin="22" pad="22"/>
<connect gate="A" pin="23" pad="23"/>
<connect gate="A" pin="24" pad="24"/>
<connect gate="A" pin="25" pad="25"/>
<connect gate="A" pin="26" pad="26"/>
<connect gate="A" pin="27" pad="27"/>
<connect gate="A" pin="28" pad="28"/>
<connect gate="A" pin="29" pad="29"/>
<connect gate="A" pin="3" pad="3"/>
<connect gate="A" pin="30" pad="30"/>
<connect gate="A" pin="4" pad="4"/>
<connect gate="A" pin="5" pad="5"/>
<connect gate="A" pin="6" pad="6"/>
<connect gate="A" pin="7" pad="7"/>
<connect gate="A" pin="8" pad="8"/>
<connect gate="A" pin="9" pad="9"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="DF37NC-30DS-0.4V(53)"/>
<attribute name="MFR_NAME" value="Hirose"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="LM1084ISX-3.3/NOPB" prefix="U">
<gates>
<gate name="A" symbol="LM1084IS-3.3"/>
</gates>
<devices>
<device name="" package="TS3B">
<connects>
<connect gate="A" pin="4" pad="4"/>
<connect gate="A" pin="ADJ/GND" pad="1"/>
<connect gate="A" pin="VIN" pad="3"/>
<connect gate="A" pin="VOUT" pad="2"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="LM1084ISX-3.3/NOPB"/>
<attribute name="MFR_NAME" value="Texas Instruments"/>
<attribute name="TYPE" value="LM1084IS-3.3"/>
</technology>
</technologies>
</device>
<device name="TS3B-M" package="TS3B-M">
<connects>
<connect gate="A" pin="4" pad="4"/>
<connect gate="A" pin="ADJ/GND" pad="1"/>
<connect gate="A" pin="VIN" pad="3"/>
<connect gate="A" pin="VOUT" pad="2"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="LM1084ISX-3.3/NOPB"/>
<attribute name="MFR_NAME" value="Texas Instruments"/>
<attribute name="TYPE" value="LM1084IS-3.3"/>
</technology>
</technologies>
</device>
<device name="TS3B-L" package="TS3B-L">
<connects>
<connect gate="A" pin="4" pad="4"/>
<connect gate="A" pin="ADJ/GND" pad="1"/>
<connect gate="A" pin="VIN" pad="3"/>
<connect gate="A" pin="VOUT" pad="2"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="LM1084ISX-3.3/NOPB"/>
<attribute name="MFR_NAME" value="Texas Instruments"/>
<attribute name="TYPE" value="LM1084IS-3.3"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="BLP9G0722-20G" prefix="MOSFET">
<gates>
<gate name="A" symbol="TRANS_N-LDMOS_1D_2G_3S"/>
</gates>
<devices>
<device name="" package="SOT1483-1_AML">
<connects>
<connect gate="A" pin="D" pad="1"/>
<connect gate="A" pin="G" pad="2"/>
<connect gate="A" pin="S" pad="3"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="BLP9G0722-20G"/>
<attribute name="MFR_NAME" value="Ampleon"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="IPD60R145CFD7ATMA1" prefix="Q">
<gates>
<gate name="A" symbol="TRANS_N-MOSFET_1G_2D_3S"/>
</gates>
<devices>
<device name="" package="PG-TO252-3-341_INF">
<connects>
<connect gate="A" pin="D" pad="2"/>
<connect gate="A" pin="G" pad="1"/>
<connect gate="A" pin="S" pad="3"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="IPD60R145CFD7ATMA1"/>
<attribute name="MFR_NAME" value="Infineon"/>
</technology>
</technologies>
</device>
<device name="PG-TO252-3-341_INF-M" package="PG-TO252-3-341_INF-M">
<connects>
<connect gate="A" pin="D" pad="2"/>
<connect gate="A" pin="G" pad="1"/>
<connect gate="A" pin="S" pad="3"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="IPD60R145CFD7ATMA1"/>
<attribute name="MFR_NAME" value="Infineon"/>
</technology>
</technologies>
</device>
<device name="PG-TO252-3-341_INF-L" package="PG-TO252-3-341_INF-L">
<connects>
<connect gate="A" pin="D" pad="2"/>
<connect gate="A" pin="G" pad="1"/>
<connect gate="A" pin="S" pad="3"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="IPD60R145CFD7ATMA1"/>
<attribute name="MFR_NAME" value="Infineon"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="10118192-0002LF" prefix="J">
<gates>
<gate name="A" symbol="CONN_005P_000C_1"/>
</gates>
<devices>
<device name="" package="CONN_10118192-0002LF_AMP">
<connects>
<connect gate="A" pin="1" pad="1"/>
<connect gate="A" pin="2" pad="2"/>
<connect gate="A" pin="3" pad="3"/>
<connect gate="A" pin="4" pad="4"/>
<connect gate="A" pin="5" pad="5"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2024 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="10118192-0002LF"/>
<attribute name="MFR_NAME" value="Amphenol ICC"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="ADT1-1+" prefix="T">
<gates>
<gate name="A" symbol="ADT1-1+"/>
</gates>
<devices>
<device name="" package="ADT1-1+_MNC">
<connects>
<connect gate="A" pin="1" pad="1"/>
<connect gate="A" pin="2" pad="2"/>
<connect gate="A" pin="3" pad="3"/>
<connect gate="A" pin="4" pad="4"/>
<connect gate="A" pin="5" pad="5"/>
<connect gate="A" pin="6" pad="6"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2025 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="ADT1-1+"/>
<attribute name="MFR_NAME" value="Mini Circuits"/>
</technology>
</technologies>
</device>
<device name="ADT1-1+_MNC-M" package="ADT1-1+_MNC-M">
<connects>
<connect gate="A" pin="1" pad="1"/>
<connect gate="A" pin="2" pad="2"/>
<connect gate="A" pin="3" pad="3"/>
<connect gate="A" pin="4" pad="4"/>
<connect gate="A" pin="5" pad="5"/>
<connect gate="A" pin="6" pad="6"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2025 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="ADT1-1+"/>
<attribute name="MFR_NAME" value="Mini Circuits"/>
</technology>
</technologies>
</device>
<device name="ADT1-1+_MNC-L" package="ADT1-1+_MNC-L">
<connects>
<connect gate="A" pin="1" pad="1"/>
<connect gate="A" pin="2" pad="2"/>
<connect gate="A" pin="3" pad="3"/>
<connect gate="A" pin="4" pad="4"/>
<connect gate="A" pin="5" pad="5"/>
<connect gate="A" pin="6" pad="6"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2025 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="ADT1-1+"/>
<attribute name="MFR_NAME" value="Mini Circuits"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="TPS61088RHLT" prefix="U">
<gates>
<gate name="A" symbol="TPS61088RHL"/>
</gates>
<devices>
<device name="" package="RHL0020A">
<connects>
<connect gate="A" pin="AGND" pad="20"/>
<connect gate="A" pin="BOOT" pad="8"/>
<connect gate="A" pin="COMP" pad="18"/>
<connect gate="A" pin="EN" pad="2"/>
<connect gate="A" pin="FB" pad="17"/>
<connect gate="A" pin="FSW" pad="3"/>
<connect gate="A" pin="ILIM" pad="19"/>
<connect gate="A" pin="MODE" pad="13"/>
<connect gate="A" pin="NC" pad="12"/>
<connect gate="A" pin="NC_2" pad="11"/>
<connect gate="A" pin="PGND" pad="21"/>
<connect gate="A" pin="SS" pad="10"/>
<connect gate="A" pin="SW" pad="7"/>
<connect gate="A" pin="SW_2" pad="4"/>
<connect gate="A" pin="SW_3" pad="5"/>
<connect gate="A" pin="SW_4" pad="6"/>
<connect gate="A" pin="VCC" pad="1"/>
<connect gate="A" pin="VIN" pad="9"/>
<connect gate="A" pin="VOUT" pad="16"/>
<connect gate="A" pin="VOUT_2" pad="14"/>
<connect gate="A" pin="VOUT_3" pad="15"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2025 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="TPS61088RHLT"/>
<attribute name="MFR_NAME" value="Texas Instruments"/>
<attribute name="REFDES" value="RefDes"/>
<attribute name="TYPE" value="TYPE"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="STM32C011F4U6TR" prefix="U">
<gates>
<gate name="A" symbol="STM32C011F4U6TR"/>
</gates>
<devices>
<device name="" package="UFQFPN20_3X3_STM">
<connects>
<connect gate="A" pin="PA0" pad="5"/>
<connect gate="A" pin="PA1" pad="6"/>
<connect gate="A" pin="PA11[PA9]" pad="14"/>
<connect gate="A" pin="PA12[PA10]" pad="15"/>
<connect gate="A" pin="PA13" pad="16"/>
<connect gate="A" pin="PA14-BOOT0" pad="17"/>
<connect gate="A" pin="PA2" pad="7"/>
<connect gate="A" pin="PA3" pad="8"/>
<connect gate="A" pin="PA4" pad="9"/>
<connect gate="A" pin="PA5" pad="10"/>
<connect gate="A" pin="PA6" pad="11"/>
<connect gate="A" pin="PA7" pad="12"/>
<connect gate="A" pin="PA8" pad="13"/>
<connect gate="A" pin="PB6" pad="18"/>
<connect gate="A" pin="PB7" pad="19"/>
<connect gate="A" pin="PC14-OSCX_IN" pad="20"/>
<connect gate="A" pin="PC15-OSCX_OUT" pad="1"/>
<connect gate="A" pin="PF2-NRST" pad="4"/>
<connect gate="A" pin="VDD/VDDA" pad="2"/>
<connect gate="A" pin="VSS/VSSA" pad="3"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2025 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="STM32C011F4U6TR"/>
<attribute name="MFR_NAME" value="STMicroelectronics"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="LSM6DS3TR" prefix="U">
<gates>
<gate name="A" symbol="LSM6DS3TR"/>
</gates>
<devices>
<device name="" package="LGA-14L_2P5X3X0P83_STM">
<connects>
<connect gate="A" pin="CS" pad="12"/>
<connect gate="A" pin="GND" pad="7"/>
<connect gate="A" pin="GND_2" pad="6"/>
<connect gate="A" pin="INT1" pad="4"/>
<connect gate="A" pin="INT2" pad="9"/>
<connect gate="A" pin="NC" pad="11"/>
<connect gate="A" pin="NC_2" pad="10"/>
<connect gate="A" pin="SCL" pad="13"/>
<connect gate="A" pin="SCX" pad="3"/>
<connect gate="A" pin="SDA" pad="14"/>
<connect gate="A" pin="SDO/SA0" pad="1"/>
<connect gate="A" pin="SDX" pad="2"/>
<connect gate="A" pin="VDD" pad="8"/>
<connect gate="A" pin="VDDIO" pad="5"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2025 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="LSM6DS3TR"/>
<attribute name="MFR_NAME" value="STMicroelectronics"/>
</technology>
</technologies>
</device>
<device name="LGA-14L_2P5X3X0P83_STM-M" package="LGA-14L_2P5X3X0P83_STM-M">
<connects>
<connect gate="A" pin="CS" pad="12"/>
<connect gate="A" pin="GND" pad="7"/>
<connect gate="A" pin="GND_2" pad="6"/>
<connect gate="A" pin="INT1" pad="4"/>
<connect gate="A" pin="INT2" pad="9"/>
<connect gate="A" pin="NC" pad="11"/>
<connect gate="A" pin="NC_2" pad="10"/>
<connect gate="A" pin="SCL" pad="13"/>
<connect gate="A" pin="SCX" pad="3"/>
<connect gate="A" pin="SDA" pad="14"/>
<connect gate="A" pin="SDO/SA0" pad="1"/>
<connect gate="A" pin="SDX" pad="2"/>
<connect gate="A" pin="VDD" pad="8"/>
<connect gate="A" pin="VDDIO" pad="5"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2025 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="LSM6DS3TR"/>
<attribute name="MFR_NAME" value="STMicroelectronics"/>
</technology>
</technologies>
</device>
<device name="LGA-14L_2P5X3X0P83_STM-L" package="LGA-14L_2P5X3X0P83_STM-L">
<connects>
<connect gate="A" pin="CS" pad="12"/>
<connect gate="A" pin="GND" pad="7"/>
<connect gate="A" pin="GND_2" pad="6"/>
<connect gate="A" pin="INT1" pad="4"/>
<connect gate="A" pin="INT2" pad="9"/>
<connect gate="A" pin="NC" pad="11"/>
<connect gate="A" pin="NC_2" pad="10"/>
<connect gate="A" pin="SCL" pad="13"/>
<connect gate="A" pin="SCX" pad="3"/>
<connect gate="A" pin="SDA" pad="14"/>
<connect gate="A" pin="SDO/SA0" pad="1"/>
<connect gate="A" pin="SDX" pad="2"/>
<connect gate="A" pin="VDD" pad="8"/>
<connect gate="A" pin="VDDIO" pad="5"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2025 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="LSM6DS3TR"/>
<attribute name="MFR_NAME" value="STMicroelectronics"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="TPS62162DSGT" prefix="U">
<gates>
<gate name="A" symbol="TPS62162DSG"/>
</gates>
<devices>
<device name="" package="DSG0008A">
<connects>
<connect gate="A" pin="AGND" pad="4"/>
<connect gate="A" pin="EN" pad="3"/>
<connect gate="A" pin="FB" pad="5"/>
<connect gate="A" pin="PAD" pad="9"/>
<connect gate="A" pin="PG" pad="8"/>
<connect gate="A" pin="PGND" pad="1"/>
<connect gate="A" pin="SW" pad="7"/>
<connect gate="A" pin="VIN" pad="2"/>
<connect gate="A" pin="VOS" pad="6"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2025 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="TPS62162DSGT"/>
<attribute name="MFR_NAME" value="Texas Instruments"/>
<attribute name="REFDES" value="RefDes"/>
<attribute name="TYPE" value="TYPE"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="TPSM863252RDXR" prefix="U">
<gates>
<gate name="A" symbol="TPSM863252RDX"/>
</gates>
<devices>
<device name="" package="RDX0007A-MFG">
<connects>
<connect gate="A" pin="EN" pad="6"/>
<connect gate="A" pin="FB" pad="7"/>
<connect gate="A" pin="PG" pad="5"/>
<connect gate="A" pin="PGND" pad="4"/>
<connect gate="A" pin="SW" pad="2"/>
<connect gate="A" pin="VIN" pad="1"/>
<connect gate="A" pin="VOUT" pad="3"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2025 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="TPSM863252RDXR"/>
<attribute name="MFR_NAME" value="Texas Instruments"/>
<attribute name="REFDES" value="RefDes"/>
<attribute name="TYPE" value="TYPE"/>
</technology>
</technologies>
</device>
<device name="RDX0007A-MFG_NOVIA" package="RDX0007A-MFG_NOVIA">
<connects>
<connect gate="A" pin="EN" pad="6"/>
<connect gate="A" pin="FB" pad="7"/>
<connect gate="A" pin="PG" pad="5"/>
<connect gate="A" pin="PGND" pad="4"/>
<connect gate="A" pin="SW" pad="2"/>
<connect gate="A" pin="VIN" pad="1"/>
<connect gate="A" pin="VOUT" pad="3"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2025 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="TPSM863252RDXR"/>
<attribute name="MFR_NAME" value="Texas Instruments"/>
<attribute name="REFDES" value="RefDes"/>
<attribute name="TYPE" value="TYPE"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="TPS65253RHDT" prefix="U">
<gates>
<gate name="A" symbol="TPS65253RHD"/>
</gates>
<devices>
<device name="" package="RHD0028A">
<connects>
<connect gate="A" pin="BST1" pad="7"/>
<connect gate="A" pin="BST2" pad="14"/>
<connect gate="A" pin="CMP1" pad="3"/>
<connect gate="A" pin="CMP2" pad="18"/>
<connect gate="A" pin="EN1" pad="6"/>
<connect gate="A" pin="EN2" pad="15"/>
<connect gate="A" pin="FB1" pad="2"/>
<connect gate="A" pin="FB2" pad="19"/>
<connect gate="A" pin="GND" pad="28"/>
<connect gate="A" pin="GND_2" pad="23"/>
<connect gate="A" pin="GND_3" pad="25"/>
<connect gate="A" pin="GND_4" pad="26"/>
<connect gate="A" pin="GND_5" pad="27"/>
<connect gate="A" pin="LOW_P" pad="20"/>
<connect gate="A" pin="LX1" pad="10"/>
<connect gate="A" pin="LX1_2" pad="9"/>
<connect gate="A" pin="LX2" pad="12"/>
<connect gate="A" pin="LX2_2" pad="11"/>
<connect gate="A" pin="PAD" pad="29"/>
<connect gate="A" pin="PGOOD" pad="24"/>
<connect gate="A" pin="RLIM1" pad="5"/>
<connect gate="A" pin="RLIM2" pad="16"/>
<connect gate="A" pin="ROSC" pad="1"/>
<connect gate="A" pin="SS1" pad="4"/>
<connect gate="A" pin="SS2" pad="17"/>
<connect gate="A" pin="V3V" pad="22"/>
<connect gate="A" pin="V7V" pad="21"/>
<connect gate="A" pin="VIN1" pad="8"/>
<connect gate="A" pin="VIN2" pad="13"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2025 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="TPS65253RHDT"/>
<attribute name="MFR_NAME" value="Texas Instruments"/>
<attribute name="REFDES" value="RefDes"/>
<attribute name="TYPE" value="TYPE"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="BAJ2DD0WHFP-TR" prefix="U">
<gates>
<gate name="A" symbol="BAJ2DD0WHFP-TR"/>
</gates>
<devices>
<device name="" package="HRP5_ROM">
<connects>
<connect gate="A" pin="CTL" pad="1"/>
<connect gate="A" pin="EPAD" pad="6"/>
<connect gate="A" pin="N.C." pad="5"/>
<connect gate="A" pin="N.C./GND" pad="3"/>
<connect gate="A" pin="OUT" pad="4"/>
<connect gate="A" pin="VCC" pad="2"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2025 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="BAJ2DD0WHFP-TR"/>
<attribute name="MFR_NAME" value="ROHM Semiconductor"/>
</technology>
</technologies>
</device>
<device name="HRP5_ROM-M" package="HRP5_ROM-M">
<connects>
<connect gate="A" pin="CTL" pad="1"/>
<connect gate="A" pin="EPAD" pad="6"/>
<connect gate="A" pin="N.C." pad="5"/>
<connect gate="A" pin="N.C./GND" pad="3"/>
<connect gate="A" pin="OUT" pad="4"/>
<connect gate="A" pin="VCC" pad="2"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2025 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="BAJ2DD0WHFP-TR"/>
<attribute name="MFR_NAME" value="ROHM Semiconductor"/>
</technology>
</technologies>
</device>
<device name="HRP5_ROM-L" package="HRP5_ROM-L">
<connects>
<connect gate="A" pin="CTL" pad="1"/>
<connect gate="A" pin="EPAD" pad="6"/>
<connect gate="A" pin="N.C." pad="5"/>
<connect gate="A" pin="N.C./GND" pad="3"/>
<connect gate="A" pin="OUT" pad="4"/>
<connect gate="A" pin="VCC" pad="2"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2025 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="BAJ2DD0WHFP-TR"/>
<attribute name="MFR_NAME" value="ROHM Semiconductor"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="1805375" prefix="J">
<gates>
<gate name="A" symbol="CONN_002P_000C_1"/>
</gates>
<devices>
<device name="" package="CONN_1805375_RSP">
<connects>
<connect gate="A" pin="1" pad="1"/>
<connect gate="A" pin="2" pad="2"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2025 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="1805375"/>
<attribute name="MFR_NAME" value="RS Pro"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="ADV7611WBSWZ" prefix="U">
<gates>
<gate name="A" symbol="ADV7611"/>
</gates>
<devices>
<device name="" package="SW-64-2_ADI">
<connects>
<connect gate="A" pin="!RESET" pad="56"/>
<connect gate="A" pin="AP" pad="48"/>
<connect gate="A" pin="CEC" pad="61"/>
<connect gate="A" pin="CVDD" pad="14"/>
<connect gate="A" pin="CVDD_2" pad="2"/>
<connect gate="A" pin="DDCA_SCL" pad="62"/>
<connect gate="A" pin="DDCA_SDA" pad="63"/>
<connect gate="A" pin="DE" pad="45"/>
<connect gate="A" pin="DVDD" pad="60"/>
<connect gate="A" pin="DVDDIO" pad="44"/>
<connect gate="A" pin="DVDDIO_2" pad="23"/>
<connect gate="A" pin="DVDDIO_3" pad="34"/>
<connect gate="A" pin="DVDD_2" pad="24"/>
<connect gate="A" pin="DVDD_3" pad="40"/>
<connect gate="A" pin="DVDD_4" pad="52"/>
<connect gate="A" pin="GND" pad="EPAD"/>
<connect gate="A" pin="HPA_A/INT2" pad="1"/>
<connect gate="A" pin="HS" pad="46"/>
<connect gate="A" pin="INT1" pad="55"/>
<connect gate="A" pin="LLC" pad="25"/>
<connect gate="A" pin="LRCLK" pad="50"/>
<connect gate="A" pin="MCLK/INT2" pad="51"/>
<connect gate="A" pin="P0" pad="43"/>
<connect gate="A" pin="P1" pad="42"/>
<connect gate="A" pin="P10" pad="31"/>
<connect gate="A" pin="P11" pad="30"/>
<connect gate="A" pin="P12" pad="29"/>
<connect gate="A" pin="P13" pad="28"/>
<connect gate="A" pin="P14" pad="27"/>
<connect gate="A" pin="P15" pad="26"/>
<connect gate="A" pin="P16" pad="22"/>
<connect gate="A" pin="P17" pad="21"/>
<connect gate="A" pin="P18" pad="20"/>
<connect gate="A" pin="P19" pad="19"/>
<connect gate="A" pin="P2" pad="41"/>
<connect gate="A" pin="P20" pad="18"/>
<connect gate="A" pin="P21" pad="17"/>
<connect gate="A" pin="P22" pad="16"/>
<connect gate="A" pin="P23" pad="15"/>
<connect gate="A" pin="P3" pad="39"/>
<connect gate="A" pin="P4" pad="38"/>
<connect gate="A" pin="P5" pad="37"/>
<connect gate="A" pin="P6" pad="36"/>
<connect gate="A" pin="P7" pad="35"/>
<connect gate="A" pin="P8" pad="33"/>
<connect gate="A" pin="P9" pad="32"/>
<connect gate="A" pin="PVDD" pad="57"/>
<connect gate="A" pin="RXA_0+" pad="7"/>
<connect gate="A" pin="RXA_0-" pad="6"/>
<connect gate="A" pin="RXA_1+" pad="10"/>
<connect gate="A" pin="RXA_1-" pad="9"/>
<connect gate="A" pin="RXA_2+" pad="13"/>
<connect gate="A" pin="RXA_2-" pad="12"/>
<connect gate="A" pin="RXA_5V" pad="64"/>
<connect gate="A" pin="RXA_C+" pad="4"/>
<connect gate="A" pin="RXA_C-" pad="3"/>
<connect gate="A" pin="SCL" pad="53"/>
<connect gate="A" pin="SCLK/INT2" pad="49"/>
<connect gate="A" pin="SDA" pad="54"/>
<connect gate="A" pin="TVDD" pad="11"/>
<connect gate="A" pin="TVDD_2" pad="5"/>
<connect gate="A" pin="TVDD_3" pad="8"/>
<connect gate="A" pin="VS/FIELD/ALSB" pad="47"/>
<connect gate="A" pin="XTALN" pad="59"/>
<connect gate="A" pin="XTALP" pad="58"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2025 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="ADV7611WBSWZ"/>
<attribute name="MFR_NAME" value="Analog Devices Inc"/>
<attribute name="TYPE" value="Linear"/>
</technology>
</technologies>
</device>
<device name="SW-64-2_ADI-M" package="SW-64-2_ADI-M">
<connects>
<connect gate="A" pin="!RESET" pad="56"/>
<connect gate="A" pin="AP" pad="48"/>
<connect gate="A" pin="CEC" pad="61"/>
<connect gate="A" pin="CVDD" pad="14"/>
<connect gate="A" pin="CVDD_2" pad="2"/>
<connect gate="A" pin="DDCA_SCL" pad="62"/>
<connect gate="A" pin="DDCA_SDA" pad="63"/>
<connect gate="A" pin="DE" pad="45"/>
<connect gate="A" pin="DVDD" pad="60"/>
<connect gate="A" pin="DVDDIO" pad="44"/>
<connect gate="A" pin="DVDDIO_2" pad="23"/>
<connect gate="A" pin="DVDDIO_3" pad="34"/>
<connect gate="A" pin="DVDD_2" pad="24"/>
<connect gate="A" pin="DVDD_3" pad="40"/>
<connect gate="A" pin="DVDD_4" pad="52"/>
<connect gate="A" pin="GND" pad="EPAD"/>
<connect gate="A" pin="HPA_A/INT2" pad="1"/>
<connect gate="A" pin="HS" pad="46"/>
<connect gate="A" pin="INT1" pad="55"/>
<connect gate="A" pin="LLC" pad="25"/>
<connect gate="A" pin="LRCLK" pad="50"/>
<connect gate="A" pin="MCLK/INT2" pad="51"/>
<connect gate="A" pin="P0" pad="43"/>
<connect gate="A" pin="P1" pad="42"/>
<connect gate="A" pin="P10" pad="31"/>
<connect gate="A" pin="P11" pad="30"/>
<connect gate="A" pin="P12" pad="29"/>
<connect gate="A" pin="P13" pad="28"/>
<connect gate="A" pin="P14" pad="27"/>
<connect gate="A" pin="P15" pad="26"/>
<connect gate="A" pin="P16" pad="22"/>
<connect gate="A" pin="P17" pad="21"/>
<connect gate="A" pin="P18" pad="20"/>
<connect gate="A" pin="P19" pad="19"/>
<connect gate="A" pin="P2" pad="41"/>
<connect gate="A" pin="P20" pad="18"/>
<connect gate="A" pin="P21" pad="17"/>
<connect gate="A" pin="P22" pad="16"/>
<connect gate="A" pin="P23" pad="15"/>
<connect gate="A" pin="P3" pad="39"/>
<connect gate="A" pin="P4" pad="38"/>
<connect gate="A" pin="P5" pad="37"/>
<connect gate="A" pin="P6" pad="36"/>
<connect gate="A" pin="P7" pad="35"/>
<connect gate="A" pin="P8" pad="33"/>
<connect gate="A" pin="P9" pad="32"/>
<connect gate="A" pin="PVDD" pad="57"/>
<connect gate="A" pin="RXA_0+" pad="7"/>
<connect gate="A" pin="RXA_0-" pad="6"/>
<connect gate="A" pin="RXA_1+" pad="10"/>
<connect gate="A" pin="RXA_1-" pad="9"/>
<connect gate="A" pin="RXA_2+" pad="13"/>
<connect gate="A" pin="RXA_2-" pad="12"/>
<connect gate="A" pin="RXA_5V" pad="64"/>
<connect gate="A" pin="RXA_C+" pad="4"/>
<connect gate="A" pin="RXA_C-" pad="3"/>
<connect gate="A" pin="SCL" pad="53"/>
<connect gate="A" pin="SCLK/INT2" pad="49"/>
<connect gate="A" pin="SDA" pad="54"/>
<connect gate="A" pin="TVDD" pad="11"/>
<connect gate="A" pin="TVDD_2" pad="5"/>
<connect gate="A" pin="TVDD_3" pad="8"/>
<connect gate="A" pin="VS/FIELD/ALSB" pad="47"/>
<connect gate="A" pin="XTALN" pad="59"/>
<connect gate="A" pin="XTALP" pad="58"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2025 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="ADV7611WBSWZ"/>
<attribute name="MFR_NAME" value="Analog Devices Inc"/>
<attribute name="TYPE" value="Linear"/>
</technology>
</technologies>
</device>
<device name="SW-64-2_ADI-L" package="SW-64-2_ADI-L">
<connects>
<connect gate="A" pin="!RESET" pad="56"/>
<connect gate="A" pin="AP" pad="48"/>
<connect gate="A" pin="CEC" pad="61"/>
<connect gate="A" pin="CVDD" pad="14"/>
<connect gate="A" pin="CVDD_2" pad="2"/>
<connect gate="A" pin="DDCA_SCL" pad="62"/>
<connect gate="A" pin="DDCA_SDA" pad="63"/>
<connect gate="A" pin="DE" pad="45"/>
<connect gate="A" pin="DVDD" pad="60"/>
<connect gate="A" pin="DVDDIO" pad="44"/>
<connect gate="A" pin="DVDDIO_2" pad="23"/>
<connect gate="A" pin="DVDDIO_3" pad="34"/>
<connect gate="A" pin="DVDD_2" pad="24"/>
<connect gate="A" pin="DVDD_3" pad="40"/>
<connect gate="A" pin="DVDD_4" pad="52"/>
<connect gate="A" pin="GND" pad="EPAD"/>
<connect gate="A" pin="HPA_A/INT2" pad="1"/>
<connect gate="A" pin="HS" pad="46"/>
<connect gate="A" pin="INT1" pad="55"/>
<connect gate="A" pin="LLC" pad="25"/>
<connect gate="A" pin="LRCLK" pad="50"/>
<connect gate="A" pin="MCLK/INT2" pad="51"/>
<connect gate="A" pin="P0" pad="43"/>
<connect gate="A" pin="P1" pad="42"/>
<connect gate="A" pin="P10" pad="31"/>
<connect gate="A" pin="P11" pad="30"/>
<connect gate="A" pin="P12" pad="29"/>
<connect gate="A" pin="P13" pad="28"/>
<connect gate="A" pin="P14" pad="27"/>
<connect gate="A" pin="P15" pad="26"/>
<connect gate="A" pin="P16" pad="22"/>
<connect gate="A" pin="P17" pad="21"/>
<connect gate="A" pin="P18" pad="20"/>
<connect gate="A" pin="P19" pad="19"/>
<connect gate="A" pin="P2" pad="41"/>
<connect gate="A" pin="P20" pad="18"/>
<connect gate="A" pin="P21" pad="17"/>
<connect gate="A" pin="P22" pad="16"/>
<connect gate="A" pin="P23" pad="15"/>
<connect gate="A" pin="P3" pad="39"/>
<connect gate="A" pin="P4" pad="38"/>
<connect gate="A" pin="P5" pad="37"/>
<connect gate="A" pin="P6" pad="36"/>
<connect gate="A" pin="P7" pad="35"/>
<connect gate="A" pin="P8" pad="33"/>
<connect gate="A" pin="P9" pad="32"/>
<connect gate="A" pin="PVDD" pad="57"/>
<connect gate="A" pin="RXA_0+" pad="7"/>
<connect gate="A" pin="RXA_0-" pad="6"/>
<connect gate="A" pin="RXA_1+" pad="10"/>
<connect gate="A" pin="RXA_1-" pad="9"/>
<connect gate="A" pin="RXA_2+" pad="13"/>
<connect gate="A" pin="RXA_2-" pad="12"/>
<connect gate="A" pin="RXA_5V" pad="64"/>
<connect gate="A" pin="RXA_C+" pad="4"/>
<connect gate="A" pin="RXA_C-" pad="3"/>
<connect gate="A" pin="SCL" pad="53"/>
<connect gate="A" pin="SCLK/INT2" pad="49"/>
<connect gate="A" pin="SDA" pad="54"/>
<connect gate="A" pin="TVDD" pad="11"/>
<connect gate="A" pin="TVDD_2" pad="5"/>
<connect gate="A" pin="TVDD_3" pad="8"/>
<connect gate="A" pin="VS/FIELD/ALSB" pad="47"/>
<connect gate="A" pin="XTALN" pad="59"/>
<connect gate="A" pin="XTALP" pad="58"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2025 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="ADV7611WBSWZ"/>
<attribute name="MFR_NAME" value="Analog Devices Inc"/>
<attribute name="TYPE" value="Linear"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="MCP4728A0-E/UN" prefix="U">
<gates>
<gate name="A" symbol="MCP4728A0-E/UN"/>
</gates>
<devices>
<device name="" package="MSOP10_MC_MCH">
<connects>
<connect gate="A" pin="!LDAC" pad="4"/>
<connect gate="A" pin="RDY/!BSY" pad="5"/>
<connect gate="A" pin="SCL" pad="2"/>
<connect gate="A" pin="SDA" pad="3"/>
<connect gate="A" pin="VDD" pad="1"/>
<connect gate="A" pin="VOUTA" pad="6"/>
<connect gate="A" pin="VOUTB" pad="7"/>
<connect gate="A" pin="VOUTC" pad="8"/>
<connect gate="A" pin="VOUTD" pad="9"/>
<connect gate="A" pin="VSS" pad="10"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2025 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="MCP4728A0-E/UN"/>
<attribute name="MFR_NAME" value="Microchip"/>
</technology>
</technologies>
</device>
<device name="MSOP10_MC_MCH-M" package="MSOP10_MC_MCH-M">
<connects>
<connect gate="A" pin="!LDAC" pad="4"/>
<connect gate="A" pin="RDY/!BSY" pad="5"/>
<connect gate="A" pin="SCL" pad="2"/>
<connect gate="A" pin="SDA" pad="3"/>
<connect gate="A" pin="VDD" pad="1"/>
<connect gate="A" pin="VOUTA" pad="6"/>
<connect gate="A" pin="VOUTB" pad="7"/>
<connect gate="A" pin="VOUTC" pad="8"/>
<connect gate="A" pin="VOUTD" pad="9"/>
<connect gate="A" pin="VSS" pad="10"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2025 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="MCP4728A0-E/UN"/>
<attribute name="MFR_NAME" value="Microchip"/>
</technology>
</technologies>
</device>
<device name="MSOP10_MC_MCH-L" package="MSOP10_MC_MCH-L">
<connects>
<connect gate="A" pin="!LDAC" pad="4"/>
<connect gate="A" pin="RDY/!BSY" pad="5"/>
<connect gate="A" pin="SCL" pad="2"/>
<connect gate="A" pin="SDA" pad="3"/>
<connect gate="A" pin="VDD" pad="1"/>
<connect gate="A" pin="VOUTA" pad="6"/>
<connect gate="A" pin="VOUTB" pad="7"/>
<connect gate="A" pin="VOUTC" pad="8"/>
<connect gate="A" pin="VOUTD" pad="9"/>
<connect gate="A" pin="VSS" pad="10"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2025 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="MCP4728A0-E/UN"/>
<attribute name="MFR_NAME" value="Microchip"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="XC7A100T-2FTG256I" prefix="U">
<gates>
<gate name="A" symbol="XC7A100T-2FTG256I"/>
<gate name="B" symbol="XC7A100T-2FTG256I_A"/>
<gate name="C" symbol="XC7A100T-2FTG256I_B"/>
<gate name="D" symbol="XC7A100T-2FTG256I_C"/>
<gate name="E" symbol="XC7A100T-2FTG256I_D"/>
</gates>
<devices>
<device name="" package="FTG256_AMD">
<connects>
<connect gate="A" pin="CCLK_0" pad="E8"/>
<connect gate="A" pin="CFGBVS_0" pad="E7"/>
<connect gate="A" pin="DONE_0" pad="H10"/>
<connect gate="A" pin="DXN_0" pad="K7"/>
<connect gate="A" pin="DXP_0" pad="K8"/>
<connect gate="A" pin="INIT_B_0" pad="K10"/>
<connect gate="A" pin="IO_0_14" pad="K12"/>
<connect gate="A" pin="IO_0_15" pad="D10"/>
<connect gate="A" pin="IO_0_34" pad="L5"/>
<connect gate="A" pin="IO_0_35" pad="E6"/>
<connect gate="A" pin="IO_25_14" pad="P6"/>
<connect gate="A" pin="IO_25_15" pad="G11"/>
<connect gate="A" pin="IO_25_35" pad="K5"/>
<connect gate="A" pin="IO_L15N_T2_DQS_DOUT_CSO_B_14" pad="T12"/>
<connect gate="A" pin="M0_0" pad="M9"/>
<connect gate="A" pin="M1_0" pad="M10"/>
<connect gate="A" pin="M2_0" pad="M11"/>
<connect gate="A" pin="PROGRAM_B_0" pad="L9"/>
<connect gate="A" pin="TCK_0" pad="L7"/>
<connect gate="A" pin="TDI_0" pad="N7"/>
<connect gate="A" pin="TDO_0" pad="N8"/>
<connect gate="A" pin="TMS_0" pad="M7"/>
<connect gate="A" pin="VN_0" pad="J7"/>
<connect gate="A" pin="VP_0" pad="H8"/>
<connect gate="B" pin="IO_L10N_T1_AD11N_15" pad="B16"/>
<connect gate="B" pin="IO_L10N_T1_AD15N_35" pad="D1"/>
<connect gate="B" pin="IO_L10N_T1_D15_14" pad="T15"/>
<connect gate="B" pin="IO_L10P_T1_34" pad="P5"/>
<connect gate="B" pin="IO_L10P_T1_AD11P_15" pad="C16"/>
<connect gate="B" pin="IO_L10P_T1_AD15P_35" pad="E2"/>
<connect gate="B" pin="IO_L10P_T1_D14_14" pad="T14"/>
<connect gate="B" pin="IO_L11N_T1_SRCC_14" pad="P13"/>
<connect gate="B" pin="IO_L11N_T1_SRCC_15" pad="C12"/>
<connect gate="B" pin="IO_L11N_T1_SRCC_35" pad="D3"/>
<connect gate="B" pin="IO_L11P_T1_SRCC_14" pad="N13"/>
<connect gate="B" pin="IO_L11P_T1_SRCC_15" pad="C11"/>
<connect gate="B" pin="IO_L11P_T1_SRCC_35" pad="E3"/>
<connect gate="B" pin="IO_L12N_T1_MRCC_14" pad="P14"/>
<connect gate="B" pin="IO_L12N_T1_MRCC_15" pad="C13"/>
<connect gate="B" pin="IO_L12N_T1_MRCC_35" pad="C4"/>
<connect gate="B" pin="IO_L12P_T1_MRCC_14" pad="N14"/>
<connect gate="B" pin="IO_L12P_T1_MRCC_15" pad="D13"/>
<connect gate="B" pin="IO_L12P_T1_MRCC_35" pad="D4"/>
<connect gate="B" pin="IO_L13N_T2_MRCC_14" pad="N12"/>
<connect gate="B" pin="IO_L13N_T2_MRCC_15" pad="E13"/>
<connect gate="B" pin="IO_L13N_T2_MRCC_35" pad="E5"/>
<connect gate="B" pin="IO_L13P_T2_MRCC_14" pad="N11"/>
<connect gate="B" pin="IO_L13P_T2_MRCC_15" pad="E12"/>
<connect gate="B" pin="IO_L13P_T2_MRCC_35" pad="F5"/>
<connect gate="B" pin="IO_L14N_T2_SRCC_14" pad="P11"/>
<connect gate="B" pin="IO_L14N_T2_SRCC_15" pad="D11"/>
<connect gate="B" pin="IO_L14N_T2_SRCC_35" pad="F3"/>
<connect gate="B" pin="IO_L14P_T2_SRCC_14" pad="P10"/>
<connect gate="B" pin="IO_L16N_T2_A15_D31_14" pad="T13"/>
<connect gate="B" pin="IO_L17N_T2_A13_D29_14" pad="R11"/>
<connect gate="B" pin="IO_L17P_T2_A14_D30_14" pad="R10"/>
<connect gate="B" pin="IO_L1N_T0_34" pad="M4"/>
<connect gate="B" pin="IO_L1N_T0_AD0N_15" pad="C9"/>
<connect gate="B" pin="IO_L1N_T0_AD4N_35" pad="A7"/>
<connect gate="B" pin="IO_L1N_T0_D01_DIN_14" pad="J14"/>
<connect gate="B" pin="IO_L1P_T0_34" pad="L4"/>
<connect gate="B" pin="IO_L1P_T0_AD0P_15" pad="C8"/>
<connect gate="B" pin="IO_L1P_T0_AD4P_35" pad="B7"/>
<connect gate="B" pin="IO_L1P_T0_D00_MOSI_14" pad="J13"/>
<connect gate="B" pin="IO_L2N_T0_34" pad="M1"/>
<connect gate="B" pin="IO_L2N_T0_AD12N_35" pad="B5"/>
<connect gate="B" pin="IO_L2N_T0_AD8N_15" pad="A9"/>
<connect gate="B" pin="IO_L2N_T0_D03_14" pad="K16"/>
<connect gate="B" pin="IO_L2P_T0_34" pad="M2"/>
<connect gate="B" pin="IO_L2P_T0_AD12P_35" pad="B6"/>
<connect gate="B" pin="IO_L2P_T0_AD8P_15" pad="A8"/>
<connect gate="B" pin="IO_L2P_T0_D02_14" pad="K15"/>
<connect gate="B" pin="IO_L3N_T0_DQS_34" pad="N2"/>
<connect gate="B" pin="IO_L3N_T0_DQS_AD1N_15" pad="A10"/>
<connect gate="B" pin="IO_L3N_T0_DQS_AD5N_35" pad="A4"/>
<connect gate="B" pin="IO_L3N_T0_DQS_EMCCLK_14" pad="M15"/>
<connect gate="B" pin="IO_L3P_T0_DQS_34" pad="N3"/>
<connect gate="B" pin="IO_L3P_T0_DQS_AD1P_15" pad="B9"/>
<connect gate="B" pin="IO_L3P_T0_DQS_AD5P_35" pad="A5"/>
<connect gate="B" pin="IO_L3P_T0_DQS_PUDC_B_14" pad="L15"/>
<connect gate="B" pin="IO_L4N_T0_15" pad="B11"/>
<connect gate="B" pin="IO_L4N_T0_34" pad="P1"/>
<connect gate="B" pin="IO_L4N_T0_35" pad="A3"/>
<connect gate="B" pin="IO_L4N_T0_D05_14" pad="M14"/>
<connect gate="B" pin="IO_L4P_T0_15" pad="B10"/>
<connect gate="B" pin="IO_L4P_T0_34" pad="N1"/>
<connect gate="B" pin="IO_L4P_T0_35" pad="B4"/>
<connect gate="B" pin="IO_L4P_T0_D04_14" pad="L14"/>
<connect gate="B" pin="IO_L5N_T0_34" pad="P3"/>
<connect gate="B" pin="IO_L5N_T0_AD13N_35" pad="C6"/>
<connect gate="B" pin="IO_L5N_T0_AD9N_15" pad="A12"/>
<connect gate="B" pin="IO_L5N_T0_D07_14" pad="L13"/>
<connect gate="B" pin="IO_L5P_T0_34" pad="P4"/>
<connect gate="B" pin="IO_L5P_T0_AD13P_35" pad="C7"/>
<connect gate="B" pin="IO_L5P_T0_AD9P_15" pad="B12"/>
<connect gate="B" pin="IO_L5P_T0_D06_14" pad="K13"/>
<connect gate="B" pin="IO_L6P_T0_15" pad="D8"/>
<connect gate="B" pin="IO_L6P_T0_34" pad="M5"/>
<connect gate="B" pin="IO_L6P_T0_35" pad="D6"/>
<connect gate="B" pin="IO_L6P_T0_FCS_B_14" pad="L12"/>
<connect gate="B" pin="IO_L7N_T1_34" pad="R1"/>
<connect gate="B" pin="IO_L7N_T1_AD2N_15" pad="A14"/>
<connect gate="B" pin="IO_L7N_T1_AD6N_35" pad="C2"/>
<connect gate="B" pin="IO_L7N_T1_D10_14" pad="N16"/>
<connect gate="B" pin="IO_L7P_T1_34" pad="R2"/>
<connect gate="B" pin="IO_L7P_T1_AD2P_15" pad="A13"/>
<connect gate="B" pin="IO_L7P_T1_AD6P_35" pad="C3"/>
<connect gate="B" pin="IO_L7P_T1_D09_14" pad="M16"/>
<connect gate="B" pin="IO_L8N_T1_34" pad="T2"/>
<connect gate="B" pin="IO_L8N_T1_AD10N_15" pad="B14"/>
<connect gate="B" pin="IO_L8N_T1_AD14N_35" pad="A2"/>
<connect gate="B" pin="IO_L8N_T1_D12_14" pad="P16"/>
<connect gate="B" pin="IO_L8P_T1_34" pad="R3"/>
<connect gate="B" pin="IO_L8P_T1_AD10P_15" pad="C14"/>
<connect gate="B" pin="IO_L8P_T1_AD14P_35" pad="B2"/>
<connect gate="B" pin="IO_L8P_T1_D11_14" pad="P15"/>
<connect gate="B" pin="IO_L9N_T1_DQS_34" pad="T3"/>
<connect gate="B" pin="IO_L9N_T1_DQS_AD3N_15" pad="A15"/>
<connect gate="B" pin="IO_L9N_T1_DQS_AD7N_35" pad="B1"/>
<connect gate="B" pin="IO_L9N_T1_DQS_D13_14" pad="R16"/>
<connect gate="B" pin="IO_L9P_T1_DQS_14" pad="R15"/>
<connect gate="B" pin="IO_L9P_T1_DQS_34" pad="T4"/>
<connect gate="B" pin="IO_L9P_T1_DQS_AD3P_15" pad="B15"/>
<connect gate="B" pin="IO_L9P_T1_DQS_AD7P_35" pad="C1"/>
<connect gate="C" pin="IO_L14P_T2_SRCC_15" pad="E11"/>
<connect gate="C" pin="IO_L14P_T2_SRCC_35" pad="F4"/>
<connect gate="C" pin="IO_L15N_T2_DQS_35" pad="E1"/>
<connect gate="C" pin="IO_L15N_T2_DQS_ADV_B_15" pad="D15"/>
<connect gate="C" pin="IO_L15P_T2_DQS_15" pad="D14"/>
<connect gate="C" pin="IO_L15P_T2_DQS_35" pad="F2"/>
<connect gate="C" pin="IO_L15P_T2_DQS_RDWR_B_14" pad="R12"/>
<connect gate="C" pin="IO_L16N_T2_35" pad="G4"/>
<connect gate="C" pin="IO_L16N_T2_A27_15" pad="F13"/>
<connect gate="C" pin="IO_L16P_T2_35" pad="G5"/>
<connect gate="C" pin="IO_L16P_T2_A28_15" pad="F12"/>
<connect gate="C" pin="IO_L16P_T2_CSI_B_14" pad="R13"/>
<connect gate="C" pin="IO_L17N_T2_35" pad="G1"/>
<connect gate="C" pin="IO_L17N_T2_A25_15" pad="D16"/>
<connect gate="C" pin="IO_L17P_T2_35" pad="G2"/>
<connect gate="C" pin="IO_L17P_T2_A26_15" pad="E16"/>
<connect gate="C" pin="IO_L18N_T2_35" pad="H4"/>
<connect gate="C" pin="IO_L18N_T2_A11_D27_14" pad="P9"/>
<connect gate="C" pin="IO_L18N_T2_A23_15" pad="E15"/>
<connect gate="C" pin="IO_L18P_T2_35" pad="H5"/>
<connect gate="C" pin="IO_L18P_T2_A12_D28_14" pad="N9"/>
<connect gate="C" pin="IO_L18P_T2_A24_15" pad="F15"/>
<connect gate="C" pin="IO_L19P_T3_35" pad="J5"/>
<connect gate="C" pin="IO_L19P_T3_A10_D26_14" pad="M6"/>
<connect gate="C" pin="IO_L19P_T3_A22_15" pad="H11"/>
<connect gate="C" pin="IO_L20N_T3_35" pad="H1"/>
<connect gate="C" pin="IO_L20N_T3_A07_D23_14" pad="R8"/>
<connect gate="C" pin="IO_L20N_T3_A19_15" pad="H13"/>
<connect gate="C" pin="IO_L20P_T3_35" pad="H2"/>
<connect gate="C" pin="IO_L20P_T3_A08_D24_14" pad="P8"/>
<connect gate="C" pin="IO_L20P_T3_A20_15" pad="H12"/>
<connect gate="C" pin="IO_L21N_T3_DQS_35" pad="H3"/>
<connect gate="C" pin="IO_L21N_T3_DQS_A06_D22_14" pad="T8"/>
<connect gate="C" pin="IO_L21N_T3_DQS_A18_15" pad="F14"/>
<connect gate="C" pin="IO_L21P_T3_DQS_14" pad="T7"/>
<connect gate="C" pin="IO_L21P_T3_DQS_15" pad="G14"/>
<connect gate="C" pin="IO_L21P_T3_DQS_35" pad="J3"/>
<connect gate="C" pin="IO_L22N_T3_35" pad="J1"/>
<connect gate="C" pin="IO_L22N_T3_A04_D20_14" pad="T10"/>
<connect gate="C" pin="IO_L22N_T3_A16_15" pad="G16"/>
<connect gate="C" pin="IO_L22P_T3_35" pad="K1"/>
<connect gate="C" pin="IO_L22P_T3_A05_D21_14" pad="T9"/>
<connect gate="C" pin="IO_L22P_T3_A17_15" pad="H16"/>
<connect gate="C" pin="IO_L23N_T3_35" pad="L2"/>
<connect gate="C" pin="IO_L23N_T3_A02_D18_14" pad="T5"/>
<connect gate="C" pin="IO_L23N_T3_FWE_B_15" pad="J16"/>
<connect gate="C" pin="IO_L23P_T3_35" pad="L3"/>
<connect gate="C" pin="IO_L23P_T3_A03_D19_14" pad="R5"/>
<connect gate="C" pin="IO_L23P_T3_FOE_B_15" pad="J15"/>
<connect gate="C" pin="IO_L24N_T3_35" pad="K2"/>
<connect gate="C" pin="IO_L24N_T3_A00_D16_14" pad="R7"/>
<connect gate="C" pin="IO_L24N_T3_RS0_15" pad="G15"/>
<connect gate="C" pin="IO_L24P_T3_35" pad="K3"/>
<connect gate="C" pin="IO_L24P_T3_A01_D17_14" pad="R6"/>
<connect gate="C" pin="IO_L24P_T3_RS1_15" pad="H14"/>
<connect gate="D" pin="IO_L19N_T3_A09_D25_VREF_14" pad="N6"/>
<connect gate="D" pin="IO_L19N_T3_A21_VREF_15" pad="G12"/>
<connect gate="D" pin="IO_L19N_T3_VREF_35" pad="J4"/>
<connect gate="D" pin="IO_L6N_T0_D08_VREF_14" pad="M12"/>
<connect gate="D" pin="IO_L6N_T0_VREF_15" pad="D9"/>
<connect gate="D" pin="IO_L6N_T0_VREF_34" pad="N4"/>
<connect gate="D" pin="IO_L6N_T0_VREF_35" pad="D5"/>
<connect gate="D" pin="VCCADC_0" pad="G8"/>
<connect gate="D" pin="VCCAUX" pad="L10"/>
<connect gate="D" pin="VCCAUX_2" pad="G10"/>
<connect gate="D" pin="VCCAUX_3" pad="J10"/>
<connect gate="D" pin="VCCAUX_4" pad="K11"/>
<connect gate="D" pin="VCCBATT_0" pad="F8"/>
<connect gate="D" pin="VCCBRAM" pad="F11"/>
<connect gate="D" pin="VCCBRAM_2" pad="E10"/>
<connect gate="D" pin="VCCINT" pad="L8"/>
<connect gate="D" pin="VCCINT_2" pad="F7"/>
<connect gate="D" pin="VCCINT_3" pad="F9"/>
<connect gate="D" pin="VCCINT_4" pad="G6"/>
<connect gate="D" pin="VCCINT_5" pad="H9"/>
<connect gate="D" pin="VCCINT_6" pad="J6"/>
<connect gate="D" pin="VCCINT_7" pad="K9"/>
<connect gate="D" pin="VCCO_0" pad="L6"/>
<connect gate="D" pin="VCCO_14" pad="T11"/>
<connect gate="D" pin="VCCO_14_2" pad="L16"/>
<connect gate="D" pin="VCCO_14_3" pad="M13"/>
<connect gate="D" pin="VCCO_14_4" pad="N10"/>
<connect gate="D" pin="VCCO_14_5" pad="P7"/>
<connect gate="D" pin="VCCO_14_6" pad="R14"/>
<connect gate="D" pin="VCCO_15" pad="J12"/>
<connect gate="D" pin="VCCO_15_2" pad="A16"/>
<connect gate="D" pin="VCCO_15_3" pad="B13"/>
<connect gate="D" pin="VCCO_15_4" pad="C10"/>
<connect gate="D" pin="VCCO_15_5" pad="E14"/>
<connect gate="D" pin="VCCO_15_6" pad="H15"/>
<connect gate="D" pin="VCCO_34" pad="T1"/>
<connect gate="D" pin="VCCO_34_2" pad="M3"/>
<connect gate="D" pin="VCCO_34_3" pad="R4"/>
<connect gate="D" pin="VCCO_35" pad="J2"/>
<connect gate="D" pin="VCCO_35_2" pad="A6"/>
<connect gate="D" pin="VCCO_35_3" pad="B3"/>
<connect gate="D" pin="VCCO_35_4" pad="D7"/>
<connect gate="D" pin="VCCO_35_5" pad="E4"/>
<connect gate="D" pin="VCCO_35_6" pad="F1"/>
<connect gate="E" pin="GND" pad="T16"/>
<connect gate="E" pin="GNDADC_0" pad="G7"/>
<connect gate="E" pin="GND_10" pad="F6"/>
<connect gate="E" pin="GND_11" pad="F10"/>
<connect gate="E" pin="GND_12" pad="F16"/>
<connect gate="E" pin="GND_13" pad="G3"/>
<connect gate="E" pin="GND_14" pad="G9"/>
<connect gate="E" pin="GND_15" pad="G13"/>
<connect gate="E" pin="GND_16" pad="H6"/>
<connect gate="E" pin="GND_17" pad="J9"/>
<connect gate="E" pin="GND_18" pad="J11"/>
<connect gate="E" pin="GND_19" pad="K4"/>
<connect gate="E" pin="GND_2" pad="A1"/>
<connect gate="E" pin="GND_20" pad="K6"/>
<connect gate="E" pin="GND_21" pad="K14"/>
<connect gate="E" pin="GND_22" pad="L1"/>
<connect gate="E" pin="GND_23" pad="L11"/>
<connect gate="E" pin="GND_24" pad="M8"/>
<connect gate="E" pin="GND_25" pad="N5"/>
<connect gate="E" pin="GND_26" pad="N15"/>
<connect gate="E" pin="GND_27" pad="P2"/>
<connect gate="E" pin="GND_28" pad="P12"/>
<connect gate="E" pin="GND_29" pad="R9"/>
<connect gate="E" pin="GND_3" pad="A11"/>
<connect gate="E" pin="GND_30" pad="T6"/>
<connect gate="E" pin="GND_4" pad="B8"/>
<connect gate="E" pin="GND_5" pad="C5"/>
<connect gate="E" pin="GND_6" pad="C15"/>
<connect gate="E" pin="GND_7" pad="D2"/>
<connect gate="E" pin="GND_8" pad="D12"/>
<connect gate="E" pin="GND_9" pad="E9"/>
<connect gate="E" pin="VREFN_0" pad="H7"/>
<connect gate="E" pin="VREFP_0" pad="J8"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2025 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_NAME" value="AMD"/>
<attribute name="MANUFACTURER_PART_NUMBER" value="XC7A100T-2FTG256I"/>
<attribute name="TYPE" value="Embedded"/>
</technology>
</technologies>
</device>
<device name="FTG256_AMD-M" package="FTG256_AMD-M">
<connects>
<connect gate="A" pin="CCLK_0" pad="E8"/>
<connect gate="A" pin="CFGBVS_0" pad="E7"/>
<connect gate="A" pin="DONE_0" pad="H10"/>
<connect gate="A" pin="DXN_0" pad="K7"/>
<connect gate="A" pin="DXP_0" pad="K8"/>
<connect gate="A" pin="INIT_B_0" pad="K10"/>
<connect gate="A" pin="IO_0_14" pad="K12"/>
<connect gate="A" pin="IO_0_15" pad="D10"/>
<connect gate="A" pin="IO_0_34" pad="L5"/>
<connect gate="A" pin="IO_0_35" pad="E6"/>
<connect gate="A" pin="IO_25_14" pad="P6"/>
<connect gate="A" pin="IO_25_15" pad="G11"/>
<connect gate="A" pin="IO_25_35" pad="K5"/>
<connect gate="A" pin="IO_L15N_T2_DQS_DOUT_CSO_B_14" pad="T12"/>
<connect gate="A" pin="M0_0" pad="M9"/>
<connect gate="A" pin="M1_0" pad="M10"/>
<connect gate="A" pin="M2_0" pad="M11"/>
<connect gate="A" pin="PROGRAM_B_0" pad="L9"/>
<connect gate="A" pin="TCK_0" pad="L7"/>
<connect gate="A" pin="TDI_0" pad="N7"/>
<connect gate="A" pin="TDO_0" pad="N8"/>
<connect gate="A" pin="TMS_0" pad="M7"/>
<connect gate="A" pin="VN_0" pad="J7"/>
<connect gate="A" pin="VP_0" pad="H8"/>
<connect gate="B" pin="IO_L10N_T1_AD11N_15" pad="B16"/>
<connect gate="B" pin="IO_L10N_T1_AD15N_35" pad="D1"/>
<connect gate="B" pin="IO_L10N_T1_D15_14" pad="T15"/>
<connect gate="B" pin="IO_L10P_T1_34" pad="P5"/>
<connect gate="B" pin="IO_L10P_T1_AD11P_15" pad="C16"/>
<connect gate="B" pin="IO_L10P_T1_AD15P_35" pad="E2"/>
<connect gate="B" pin="IO_L10P_T1_D14_14" pad="T14"/>
<connect gate="B" pin="IO_L11N_T1_SRCC_14" pad="P13"/>
<connect gate="B" pin="IO_L11N_T1_SRCC_15" pad="C12"/>
<connect gate="B" pin="IO_L11N_T1_SRCC_35" pad="D3"/>
<connect gate="B" pin="IO_L11P_T1_SRCC_14" pad="N13"/>
<connect gate="B" pin="IO_L11P_T1_SRCC_15" pad="C11"/>
<connect gate="B" pin="IO_L11P_T1_SRCC_35" pad="E3"/>
<connect gate="B" pin="IO_L12N_T1_MRCC_14" pad="P14"/>
<connect gate="B" pin="IO_L12N_T1_MRCC_15" pad="C13"/>
<connect gate="B" pin="IO_L12N_T1_MRCC_35" pad="C4"/>
<connect gate="B" pin="IO_L12P_T1_MRCC_14" pad="N14"/>
<connect gate="B" pin="IO_L12P_T1_MRCC_15" pad="D13"/>
<connect gate="B" pin="IO_L12P_T1_MRCC_35" pad="D4"/>
<connect gate="B" pin="IO_L13N_T2_MRCC_14" pad="N12"/>
<connect gate="B" pin="IO_L13N_T2_MRCC_15" pad="E13"/>
<connect gate="B" pin="IO_L13N_T2_MRCC_35" pad="E5"/>
<connect gate="B" pin="IO_L13P_T2_MRCC_14" pad="N11"/>
<connect gate="B" pin="IO_L13P_T2_MRCC_15" pad="E12"/>
<connect gate="B" pin="IO_L13P_T2_MRCC_35" pad="F5"/>
<connect gate="B" pin="IO_L14N_T2_SRCC_14" pad="P11"/>
<connect gate="B" pin="IO_L14N_T2_SRCC_15" pad="D11"/>
<connect gate="B" pin="IO_L14N_T2_SRCC_35" pad="F3"/>
<connect gate="B" pin="IO_L14P_T2_SRCC_14" pad="P10"/>
<connect gate="B" pin="IO_L16N_T2_A15_D31_14" pad="T13"/>
<connect gate="B" pin="IO_L17N_T2_A13_D29_14" pad="R11"/>
<connect gate="B" pin="IO_L17P_T2_A14_D30_14" pad="R10"/>
<connect gate="B" pin="IO_L1N_T0_34" pad="M4"/>
<connect gate="B" pin="IO_L1N_T0_AD0N_15" pad="C9"/>
<connect gate="B" pin="IO_L1N_T0_AD4N_35" pad="A7"/>
<connect gate="B" pin="IO_L1N_T0_D01_DIN_14" pad="J14"/>
<connect gate="B" pin="IO_L1P_T0_34" pad="L4"/>
<connect gate="B" pin="IO_L1P_T0_AD0P_15" pad="C8"/>
<connect gate="B" pin="IO_L1P_T0_AD4P_35" pad="B7"/>
<connect gate="B" pin="IO_L1P_T0_D00_MOSI_14" pad="J13"/>
<connect gate="B" pin="IO_L2N_T0_34" pad="M1"/>
<connect gate="B" pin="IO_L2N_T0_AD12N_35" pad="B5"/>
<connect gate="B" pin="IO_L2N_T0_AD8N_15" pad="A9"/>
<connect gate="B" pin="IO_L2N_T0_D03_14" pad="K16"/>
<connect gate="B" pin="IO_L2P_T0_34" pad="M2"/>
<connect gate="B" pin="IO_L2P_T0_AD12P_35" pad="B6"/>
<connect gate="B" pin="IO_L2P_T0_AD8P_15" pad="A8"/>
<connect gate="B" pin="IO_L2P_T0_D02_14" pad="K15"/>
<connect gate="B" pin="IO_L3N_T0_DQS_34" pad="N2"/>
<connect gate="B" pin="IO_L3N_T0_DQS_AD1N_15" pad="A10"/>
<connect gate="B" pin="IO_L3N_T0_DQS_AD5N_35" pad="A4"/>
<connect gate="B" pin="IO_L3N_T0_DQS_EMCCLK_14" pad="M15"/>
<connect gate="B" pin="IO_L3P_T0_DQS_34" pad="N3"/>
<connect gate="B" pin="IO_L3P_T0_DQS_AD1P_15" pad="B9"/>
<connect gate="B" pin="IO_L3P_T0_DQS_AD5P_35" pad="A5"/>
<connect gate="B" pin="IO_L3P_T0_DQS_PUDC_B_14" pad="L15"/>
<connect gate="B" pin="IO_L4N_T0_15" pad="B11"/>
<connect gate="B" pin="IO_L4N_T0_34" pad="P1"/>
<connect gate="B" pin="IO_L4N_T0_35" pad="A3"/>
<connect gate="B" pin="IO_L4N_T0_D05_14" pad="M14"/>
<connect gate="B" pin="IO_L4P_T0_15" pad="B10"/>
<connect gate="B" pin="IO_L4P_T0_34" pad="N1"/>
<connect gate="B" pin="IO_L4P_T0_35" pad="B4"/>
<connect gate="B" pin="IO_L4P_T0_D04_14" pad="L14"/>
<connect gate="B" pin="IO_L5N_T0_34" pad="P3"/>
<connect gate="B" pin="IO_L5N_T0_AD13N_35" pad="C6"/>
<connect gate="B" pin="IO_L5N_T0_AD9N_15" pad="A12"/>
<connect gate="B" pin="IO_L5N_T0_D07_14" pad="L13"/>
<connect gate="B" pin="IO_L5P_T0_34" pad="P4"/>
<connect gate="B" pin="IO_L5P_T0_AD13P_35" pad="C7"/>
<connect gate="B" pin="IO_L5P_T0_AD9P_15" pad="B12"/>
<connect gate="B" pin="IO_L5P_T0_D06_14" pad="K13"/>
<connect gate="B" pin="IO_L6P_T0_15" pad="D8"/>
<connect gate="B" pin="IO_L6P_T0_34" pad="M5"/>
<connect gate="B" pin="IO_L6P_T0_35" pad="D6"/>
<connect gate="B" pin="IO_L6P_T0_FCS_B_14" pad="L12"/>
<connect gate="B" pin="IO_L7N_T1_34" pad="R1"/>
<connect gate="B" pin="IO_L7N_T1_AD2N_15" pad="A14"/>
<connect gate="B" pin="IO_L7N_T1_AD6N_35" pad="C2"/>
<connect gate="B" pin="IO_L7N_T1_D10_14" pad="N16"/>
<connect gate="B" pin="IO_L7P_T1_34" pad="R2"/>
<connect gate="B" pin="IO_L7P_T1_AD2P_15" pad="A13"/>
<connect gate="B" pin="IO_L7P_T1_AD6P_35" pad="C3"/>
<connect gate="B" pin="IO_L7P_T1_D09_14" pad="M16"/>
<connect gate="B" pin="IO_L8N_T1_34" pad="T2"/>
<connect gate="B" pin="IO_L8N_T1_AD10N_15" pad="B14"/>
<connect gate="B" pin="IO_L8N_T1_AD14N_35" pad="A2"/>
<connect gate="B" pin="IO_L8N_T1_D12_14" pad="P16"/>
<connect gate="B" pin="IO_L8P_T1_34" pad="R3"/>
<connect gate="B" pin="IO_L8P_T1_AD10P_15" pad="C14"/>
<connect gate="B" pin="IO_L8P_T1_AD14P_35" pad="B2"/>
<connect gate="B" pin="IO_L8P_T1_D11_14" pad="P15"/>
<connect gate="B" pin="IO_L9N_T1_DQS_34" pad="T3"/>
<connect gate="B" pin="IO_L9N_T1_DQS_AD3N_15" pad="A15"/>
<connect gate="B" pin="IO_L9N_T1_DQS_AD7N_35" pad="B1"/>
<connect gate="B" pin="IO_L9N_T1_DQS_D13_14" pad="R16"/>
<connect gate="B" pin="IO_L9P_T1_DQS_14" pad="R15"/>
<connect gate="B" pin="IO_L9P_T1_DQS_34" pad="T4"/>
<connect gate="B" pin="IO_L9P_T1_DQS_AD3P_15" pad="B15"/>
<connect gate="B" pin="IO_L9P_T1_DQS_AD7P_35" pad="C1"/>
<connect gate="C" pin="IO_L14P_T2_SRCC_15" pad="E11"/>
<connect gate="C" pin="IO_L14P_T2_SRCC_35" pad="F4"/>
<connect gate="C" pin="IO_L15N_T2_DQS_35" pad="E1"/>
<connect gate="C" pin="IO_L15N_T2_DQS_ADV_B_15" pad="D15"/>
<connect gate="C" pin="IO_L15P_T2_DQS_15" pad="D14"/>
<connect gate="C" pin="IO_L15P_T2_DQS_35" pad="F2"/>
<connect gate="C" pin="IO_L15P_T2_DQS_RDWR_B_14" pad="R12"/>
<connect gate="C" pin="IO_L16N_T2_35" pad="G4"/>
<connect gate="C" pin="IO_L16N_T2_A27_15" pad="F13"/>
<connect gate="C" pin="IO_L16P_T2_35" pad="G5"/>
<connect gate="C" pin="IO_L16P_T2_A28_15" pad="F12"/>
<connect gate="C" pin="IO_L16P_T2_CSI_B_14" pad="R13"/>
<connect gate="C" pin="IO_L17N_T2_35" pad="G1"/>
<connect gate="C" pin="IO_L17N_T2_A25_15" pad="D16"/>
<connect gate="C" pin="IO_L17P_T2_35" pad="G2"/>
<connect gate="C" pin="IO_L17P_T2_A26_15" pad="E16"/>
<connect gate="C" pin="IO_L18N_T2_35" pad="H4"/>
<connect gate="C" pin="IO_L18N_T2_A11_D27_14" pad="P9"/>
<connect gate="C" pin="IO_L18N_T2_A23_15" pad="E15"/>
<connect gate="C" pin="IO_L18P_T2_35" pad="H5"/>
<connect gate="C" pin="IO_L18P_T2_A12_D28_14" pad="N9"/>
<connect gate="C" pin="IO_L18P_T2_A24_15" pad="F15"/>
<connect gate="C" pin="IO_L19P_T3_35" pad="J5"/>
<connect gate="C" pin="IO_L19P_T3_A10_D26_14" pad="M6"/>
<connect gate="C" pin="IO_L19P_T3_A22_15" pad="H11"/>
<connect gate="C" pin="IO_L20N_T3_35" pad="H1"/>
<connect gate="C" pin="IO_L20N_T3_A07_D23_14" pad="R8"/>
<connect gate="C" pin="IO_L20N_T3_A19_15" pad="H13"/>
<connect gate="C" pin="IO_L20P_T3_35" pad="H2"/>
<connect gate="C" pin="IO_L20P_T3_A08_D24_14" pad="P8"/>
<connect gate="C" pin="IO_L20P_T3_A20_15" pad="H12"/>
<connect gate="C" pin="IO_L21N_T3_DQS_35" pad="H3"/>
<connect gate="C" pin="IO_L21N_T3_DQS_A06_D22_14" pad="T8"/>
<connect gate="C" pin="IO_L21N_T3_DQS_A18_15" pad="F14"/>
<connect gate="C" pin="IO_L21P_T3_DQS_14" pad="T7"/>
<connect gate="C" pin="IO_L21P_T3_DQS_15" pad="G14"/>
<connect gate="C" pin="IO_L21P_T3_DQS_35" pad="J3"/>
<connect gate="C" pin="IO_L22N_T3_35" pad="J1"/>
<connect gate="C" pin="IO_L22N_T3_A04_D20_14" pad="T10"/>
<connect gate="C" pin="IO_L22N_T3_A16_15" pad="G16"/>
<connect gate="C" pin="IO_L22P_T3_35" pad="K1"/>
<connect gate="C" pin="IO_L22P_T3_A05_D21_14" pad="T9"/>
<connect gate="C" pin="IO_L22P_T3_A17_15" pad="H16"/>
<connect gate="C" pin="IO_L23N_T3_35" pad="L2"/>
<connect gate="C" pin="IO_L23N_T3_A02_D18_14" pad="T5"/>
<connect gate="C" pin="IO_L23N_T3_FWE_B_15" pad="J16"/>
<connect gate="C" pin="IO_L23P_T3_35" pad="L3"/>
<connect gate="C" pin="IO_L23P_T3_A03_D19_14" pad="R5"/>
<connect gate="C" pin="IO_L23P_T3_FOE_B_15" pad="J15"/>
<connect gate="C" pin="IO_L24N_T3_35" pad="K2"/>
<connect gate="C" pin="IO_L24N_T3_A00_D16_14" pad="R7"/>
<connect gate="C" pin="IO_L24N_T3_RS0_15" pad="G15"/>
<connect gate="C" pin="IO_L24P_T3_35" pad="K3"/>
<connect gate="C" pin="IO_L24P_T3_A01_D17_14" pad="R6"/>
<connect gate="C" pin="IO_L24P_T3_RS1_15" pad="H14"/>
<connect gate="D" pin="IO_L19N_T3_A09_D25_VREF_14" pad="N6"/>
<connect gate="D" pin="IO_L19N_T3_A21_VREF_15" pad="G12"/>
<connect gate="D" pin="IO_L19N_T3_VREF_35" pad="J4"/>
<connect gate="D" pin="IO_L6N_T0_D08_VREF_14" pad="M12"/>
<connect gate="D" pin="IO_L6N_T0_VREF_15" pad="D9"/>
<connect gate="D" pin="IO_L6N_T0_VREF_34" pad="N4"/>
<connect gate="D" pin="IO_L6N_T0_VREF_35" pad="D5"/>
<connect gate="D" pin="VCCADC_0" pad="G8"/>
<connect gate="D" pin="VCCAUX" pad="L10"/>
<connect gate="D" pin="VCCAUX_2" pad="G10"/>
<connect gate="D" pin="VCCAUX_3" pad="J10"/>
<connect gate="D" pin="VCCAUX_4" pad="K11"/>
<connect gate="D" pin="VCCBATT_0" pad="F8"/>
<connect gate="D" pin="VCCBRAM" pad="F11"/>
<connect gate="D" pin="VCCBRAM_2" pad="E10"/>
<connect gate="D" pin="VCCINT" pad="L8"/>
<connect gate="D" pin="VCCINT_2" pad="F7"/>
<connect gate="D" pin="VCCINT_3" pad="F9"/>
<connect gate="D" pin="VCCINT_4" pad="G6"/>
<connect gate="D" pin="VCCINT_5" pad="H9"/>
<connect gate="D" pin="VCCINT_6" pad="J6"/>
<connect gate="D" pin="VCCINT_7" pad="K9"/>
<connect gate="D" pin="VCCO_0" pad="L6"/>
<connect gate="D" pin="VCCO_14" pad="T11"/>
<connect gate="D" pin="VCCO_14_2" pad="L16"/>
<connect gate="D" pin="VCCO_14_3" pad="M13"/>
<connect gate="D" pin="VCCO_14_4" pad="N10"/>
<connect gate="D" pin="VCCO_14_5" pad="P7"/>
<connect gate="D" pin="VCCO_14_6" pad="R14"/>
<connect gate="D" pin="VCCO_15" pad="J12"/>
<connect gate="D" pin="VCCO_15_2" pad="A16"/>
<connect gate="D" pin="VCCO_15_3" pad="B13"/>
<connect gate="D" pin="VCCO_15_4" pad="C10"/>
<connect gate="D" pin="VCCO_15_5" pad="E14"/>
<connect gate="D" pin="VCCO_15_6" pad="H15"/>
<connect gate="D" pin="VCCO_34" pad="T1"/>
<connect gate="D" pin="VCCO_34_2" pad="M3"/>
<connect gate="D" pin="VCCO_34_3" pad="R4"/>
<connect gate="D" pin="VCCO_35" pad="J2"/>
<connect gate="D" pin="VCCO_35_2" pad="A6"/>
<connect gate="D" pin="VCCO_35_3" pad="B3"/>
<connect gate="D" pin="VCCO_35_4" pad="D7"/>
<connect gate="D" pin="VCCO_35_5" pad="E4"/>
<connect gate="D" pin="VCCO_35_6" pad="F1"/>
<connect gate="E" pin="GND" pad="T16"/>
<connect gate="E" pin="GNDADC_0" pad="G7"/>
<connect gate="E" pin="GND_10" pad="F6"/>
<connect gate="E" pin="GND_11" pad="F10"/>
<connect gate="E" pin="GND_12" pad="F16"/>
<connect gate="E" pin="GND_13" pad="G3"/>
<connect gate="E" pin="GND_14" pad="G9"/>
<connect gate="E" pin="GND_15" pad="G13"/>
<connect gate="E" pin="GND_16" pad="H6"/>
<connect gate="E" pin="GND_17" pad="J9"/>
<connect gate="E" pin="GND_18" pad="J11"/>
<connect gate="E" pin="GND_19" pad="K4"/>
<connect gate="E" pin="GND_2" pad="A1"/>
<connect gate="E" pin="GND_20" pad="K6"/>
<connect gate="E" pin="GND_21" pad="K14"/>
<connect gate="E" pin="GND_22" pad="L1"/>
<connect gate="E" pin="GND_23" pad="L11"/>
<connect gate="E" pin="GND_24" pad="M8"/>
<connect gate="E" pin="GND_25" pad="N5"/>
<connect gate="E" pin="GND_26" pad="N15"/>
<connect gate="E" pin="GND_27" pad="P2"/>
<connect gate="E" pin="GND_28" pad="P12"/>
<connect gate="E" pin="GND_29" pad="R9"/>
<connect gate="E" pin="GND_3" pad="A11"/>
<connect gate="E" pin="GND_30" pad="T6"/>
<connect gate="E" pin="GND_4" pad="B8"/>
<connect gate="E" pin="GND_5" pad="C5"/>
<connect gate="E" pin="GND_6" pad="C15"/>
<connect gate="E" pin="GND_7" pad="D2"/>
<connect gate="E" pin="GND_8" pad="D12"/>
<connect gate="E" pin="GND_9" pad="E9"/>
<connect gate="E" pin="VREFN_0" pad="H7"/>
<connect gate="E" pin="VREFP_0" pad="J8"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2025 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_NAME" value="AMD"/>
<attribute name="MANUFACTURER_PART_NUMBER" value="XC7A100T-2FTG256I"/>
<attribute name="TYPE" value="Embedded"/>
</technology>
</technologies>
</device>
<device name="FTG256_AMD-L" package="FTG256_AMD-L">
<connects>
<connect gate="A" pin="CCLK_0" pad="E8"/>
<connect gate="A" pin="CFGBVS_0" pad="E7"/>
<connect gate="A" pin="DONE_0" pad="H10"/>
<connect gate="A" pin="DXN_0" pad="K7"/>
<connect gate="A" pin="DXP_0" pad="K8"/>
<connect gate="A" pin="INIT_B_0" pad="K10"/>
<connect gate="A" pin="IO_0_14" pad="K12"/>
<connect gate="A" pin="IO_0_15" pad="D10"/>
<connect gate="A" pin="IO_0_34" pad="L5"/>
<connect gate="A" pin="IO_0_35" pad="E6"/>
<connect gate="A" pin="IO_25_14" pad="P6"/>
<connect gate="A" pin="IO_25_15" pad="G11"/>
<connect gate="A" pin="IO_25_35" pad="K5"/>
<connect gate="A" pin="IO_L15N_T2_DQS_DOUT_CSO_B_14" pad="T12"/>
<connect gate="A" pin="M0_0" pad="M9"/>
<connect gate="A" pin="M1_0" pad="M10"/>
<connect gate="A" pin="M2_0" pad="M11"/>
<connect gate="A" pin="PROGRAM_B_0" pad="L9"/>
<connect gate="A" pin="TCK_0" pad="L7"/>
<connect gate="A" pin="TDI_0" pad="N7"/>
<connect gate="A" pin="TDO_0" pad="N8"/>
<connect gate="A" pin="TMS_0" pad="M7"/>
<connect gate="A" pin="VN_0" pad="J7"/>
<connect gate="A" pin="VP_0" pad="H8"/>
<connect gate="B" pin="IO_L10N_T1_AD11N_15" pad="B16"/>
<connect gate="B" pin="IO_L10N_T1_AD15N_35" pad="D1"/>
<connect gate="B" pin="IO_L10N_T1_D15_14" pad="T15"/>
<connect gate="B" pin="IO_L10P_T1_34" pad="P5"/>
<connect gate="B" pin="IO_L10P_T1_AD11P_15" pad="C16"/>
<connect gate="B" pin="IO_L10P_T1_AD15P_35" pad="E2"/>
<connect gate="B" pin="IO_L10P_T1_D14_14" pad="T14"/>
<connect gate="B" pin="IO_L11N_T1_SRCC_14" pad="P13"/>
<connect gate="B" pin="IO_L11N_T1_SRCC_15" pad="C12"/>
<connect gate="B" pin="IO_L11N_T1_SRCC_35" pad="D3"/>
<connect gate="B" pin="IO_L11P_T1_SRCC_14" pad="N13"/>
<connect gate="B" pin="IO_L11P_T1_SRCC_15" pad="C11"/>
<connect gate="B" pin="IO_L11P_T1_SRCC_35" pad="E3"/>
<connect gate="B" pin="IO_L12N_T1_MRCC_14" pad="P14"/>
<connect gate="B" pin="IO_L12N_T1_MRCC_15" pad="C13"/>
<connect gate="B" pin="IO_L12N_T1_MRCC_35" pad="C4"/>
<connect gate="B" pin="IO_L12P_T1_MRCC_14" pad="N14"/>
<connect gate="B" pin="IO_L12P_T1_MRCC_15" pad="D13"/>
<connect gate="B" pin="IO_L12P_T1_MRCC_35" pad="D4"/>
<connect gate="B" pin="IO_L13N_T2_MRCC_14" pad="N12"/>
<connect gate="B" pin="IO_L13N_T2_MRCC_15" pad="E13"/>
<connect gate="B" pin="IO_L13N_T2_MRCC_35" pad="E5"/>
<connect gate="B" pin="IO_L13P_T2_MRCC_14" pad="N11"/>
<connect gate="B" pin="IO_L13P_T2_MRCC_15" pad="E12"/>
<connect gate="B" pin="IO_L13P_T2_MRCC_35" pad="F5"/>
<connect gate="B" pin="IO_L14N_T2_SRCC_14" pad="P11"/>
<connect gate="B" pin="IO_L14N_T2_SRCC_15" pad="D11"/>
<connect gate="B" pin="IO_L14N_T2_SRCC_35" pad="F3"/>
<connect gate="B" pin="IO_L14P_T2_SRCC_14" pad="P10"/>
<connect gate="B" pin="IO_L16N_T2_A15_D31_14" pad="T13"/>
<connect gate="B" pin="IO_L17N_T2_A13_D29_14" pad="R11"/>
<connect gate="B" pin="IO_L17P_T2_A14_D30_14" pad="R10"/>
<connect gate="B" pin="IO_L1N_T0_34" pad="M4"/>
<connect gate="B" pin="IO_L1N_T0_AD0N_15" pad="C9"/>
<connect gate="B" pin="IO_L1N_T0_AD4N_35" pad="A7"/>
<connect gate="B" pin="IO_L1N_T0_D01_DIN_14" pad="J14"/>
<connect gate="B" pin="IO_L1P_T0_34" pad="L4"/>
<connect gate="B" pin="IO_L1P_T0_AD0P_15" pad="C8"/>
<connect gate="B" pin="IO_L1P_T0_AD4P_35" pad="B7"/>
<connect gate="B" pin="IO_L1P_T0_D00_MOSI_14" pad="J13"/>
<connect gate="B" pin="IO_L2N_T0_34" pad="M1"/>
<connect gate="B" pin="IO_L2N_T0_AD12N_35" pad="B5"/>
<connect gate="B" pin="IO_L2N_T0_AD8N_15" pad="A9"/>
<connect gate="B" pin="IO_L2N_T0_D03_14" pad="K16"/>
<connect gate="B" pin="IO_L2P_T0_34" pad="M2"/>
<connect gate="B" pin="IO_L2P_T0_AD12P_35" pad="B6"/>
<connect gate="B" pin="IO_L2P_T0_AD8P_15" pad="A8"/>
<connect gate="B" pin="IO_L2P_T0_D02_14" pad="K15"/>
<connect gate="B" pin="IO_L3N_T0_DQS_34" pad="N2"/>
<connect gate="B" pin="IO_L3N_T0_DQS_AD1N_15" pad="A10"/>
<connect gate="B" pin="IO_L3N_T0_DQS_AD5N_35" pad="A4"/>
<connect gate="B" pin="IO_L3N_T0_DQS_EMCCLK_14" pad="M15"/>
<connect gate="B" pin="IO_L3P_T0_DQS_34" pad="N3"/>
<connect gate="B" pin="IO_L3P_T0_DQS_AD1P_15" pad="B9"/>
<connect gate="B" pin="IO_L3P_T0_DQS_AD5P_35" pad="A5"/>
<connect gate="B" pin="IO_L3P_T0_DQS_PUDC_B_14" pad="L15"/>
<connect gate="B" pin="IO_L4N_T0_15" pad="B11"/>
<connect gate="B" pin="IO_L4N_T0_34" pad="P1"/>
<connect gate="B" pin="IO_L4N_T0_35" pad="A3"/>
<connect gate="B" pin="IO_L4N_T0_D05_14" pad="M14"/>
<connect gate="B" pin="IO_L4P_T0_15" pad="B10"/>
<connect gate="B" pin="IO_L4P_T0_34" pad="N1"/>
<connect gate="B" pin="IO_L4P_T0_35" pad="B4"/>
<connect gate="B" pin="IO_L4P_T0_D04_14" pad="L14"/>
<connect gate="B" pin="IO_L5N_T0_34" pad="P3"/>
<connect gate="B" pin="IO_L5N_T0_AD13N_35" pad="C6"/>
<connect gate="B" pin="IO_L5N_T0_AD9N_15" pad="A12"/>
<connect gate="B" pin="IO_L5N_T0_D07_14" pad="L13"/>
<connect gate="B" pin="IO_L5P_T0_34" pad="P4"/>
<connect gate="B" pin="IO_L5P_T0_AD13P_35" pad="C7"/>
<connect gate="B" pin="IO_L5P_T0_AD9P_15" pad="B12"/>
<connect gate="B" pin="IO_L5P_T0_D06_14" pad="K13"/>
<connect gate="B" pin="IO_L6P_T0_15" pad="D8"/>
<connect gate="B" pin="IO_L6P_T0_34" pad="M5"/>
<connect gate="B" pin="IO_L6P_T0_35" pad="D6"/>
<connect gate="B" pin="IO_L6P_T0_FCS_B_14" pad="L12"/>
<connect gate="B" pin="IO_L7N_T1_34" pad="R1"/>
<connect gate="B" pin="IO_L7N_T1_AD2N_15" pad="A14"/>
<connect gate="B" pin="IO_L7N_T1_AD6N_35" pad="C2"/>
<connect gate="B" pin="IO_L7N_T1_D10_14" pad="N16"/>
<connect gate="B" pin="IO_L7P_T1_34" pad="R2"/>
<connect gate="B" pin="IO_L7P_T1_AD2P_15" pad="A13"/>
<connect gate="B" pin="IO_L7P_T1_AD6P_35" pad="C3"/>
<connect gate="B" pin="IO_L7P_T1_D09_14" pad="M16"/>
<connect gate="B" pin="IO_L8N_T1_34" pad="T2"/>
<connect gate="B" pin="IO_L8N_T1_AD10N_15" pad="B14"/>
<connect gate="B" pin="IO_L8N_T1_AD14N_35" pad="A2"/>
<connect gate="B" pin="IO_L8N_T1_D12_14" pad="P16"/>
<connect gate="B" pin="IO_L8P_T1_34" pad="R3"/>
<connect gate="B" pin="IO_L8P_T1_AD10P_15" pad="C14"/>
<connect gate="B" pin="IO_L8P_T1_AD14P_35" pad="B2"/>
<connect gate="B" pin="IO_L8P_T1_D11_14" pad="P15"/>
<connect gate="B" pin="IO_L9N_T1_DQS_34" pad="T3"/>
<connect gate="B" pin="IO_L9N_T1_DQS_AD3N_15" pad="A15"/>
<connect gate="B" pin="IO_L9N_T1_DQS_AD7N_35" pad="B1"/>
<connect gate="B" pin="IO_L9N_T1_DQS_D13_14" pad="R16"/>
<connect gate="B" pin="IO_L9P_T1_DQS_14" pad="R15"/>
<connect gate="B" pin="IO_L9P_T1_DQS_34" pad="T4"/>
<connect gate="B" pin="IO_L9P_T1_DQS_AD3P_15" pad="B15"/>
<connect gate="B" pin="IO_L9P_T1_DQS_AD7P_35" pad="C1"/>
<connect gate="C" pin="IO_L14P_T2_SRCC_15" pad="E11"/>
<connect gate="C" pin="IO_L14P_T2_SRCC_35" pad="F4"/>
<connect gate="C" pin="IO_L15N_T2_DQS_35" pad="E1"/>
<connect gate="C" pin="IO_L15N_T2_DQS_ADV_B_15" pad="D15"/>
<connect gate="C" pin="IO_L15P_T2_DQS_15" pad="D14"/>
<connect gate="C" pin="IO_L15P_T2_DQS_35" pad="F2"/>
<connect gate="C" pin="IO_L15P_T2_DQS_RDWR_B_14" pad="R12"/>
<connect gate="C" pin="IO_L16N_T2_35" pad="G4"/>
<connect gate="C" pin="IO_L16N_T2_A27_15" pad="F13"/>
<connect gate="C" pin="IO_L16P_T2_35" pad="G5"/>
<connect gate="C" pin="IO_L16P_T2_A28_15" pad="F12"/>
<connect gate="C" pin="IO_L16P_T2_CSI_B_14" pad="R13"/>
<connect gate="C" pin="IO_L17N_T2_35" pad="G1"/>
<connect gate="C" pin="IO_L17N_T2_A25_15" pad="D16"/>
<connect gate="C" pin="IO_L17P_T2_35" pad="G2"/>
<connect gate="C" pin="IO_L17P_T2_A26_15" pad="E16"/>
<connect gate="C" pin="IO_L18N_T2_35" pad="H4"/>
<connect gate="C" pin="IO_L18N_T2_A11_D27_14" pad="P9"/>
<connect gate="C" pin="IO_L18N_T2_A23_15" pad="E15"/>
<connect gate="C" pin="IO_L18P_T2_35" pad="H5"/>
<connect gate="C" pin="IO_L18P_T2_A12_D28_14" pad="N9"/>
<connect gate="C" pin="IO_L18P_T2_A24_15" pad="F15"/>
<connect gate="C" pin="IO_L19P_T3_35" pad="J5"/>
<connect gate="C" pin="IO_L19P_T3_A10_D26_14" pad="M6"/>
<connect gate="C" pin="IO_L19P_T3_A22_15" pad="H11"/>
<connect gate="C" pin="IO_L20N_T3_35" pad="H1"/>
<connect gate="C" pin="IO_L20N_T3_A07_D23_14" pad="R8"/>
<connect gate="C" pin="IO_L20N_T3_A19_15" pad="H13"/>
<connect gate="C" pin="IO_L20P_T3_35" pad="H2"/>
<connect gate="C" pin="IO_L20P_T3_A08_D24_14" pad="P8"/>
<connect gate="C" pin="IO_L20P_T3_A20_15" pad="H12"/>
<connect gate="C" pin="IO_L21N_T3_DQS_35" pad="H3"/>
<connect gate="C" pin="IO_L21N_T3_DQS_A06_D22_14" pad="T8"/>
<connect gate="C" pin="IO_L21N_T3_DQS_A18_15" pad="F14"/>
<connect gate="C" pin="IO_L21P_T3_DQS_14" pad="T7"/>
<connect gate="C" pin="IO_L21P_T3_DQS_15" pad="G14"/>
<connect gate="C" pin="IO_L21P_T3_DQS_35" pad="J3"/>
<connect gate="C" pin="IO_L22N_T3_35" pad="J1"/>
<connect gate="C" pin="IO_L22N_T3_A04_D20_14" pad="T10"/>
<connect gate="C" pin="IO_L22N_T3_A16_15" pad="G16"/>
<connect gate="C" pin="IO_L22P_T3_35" pad="K1"/>
<connect gate="C" pin="IO_L22P_T3_A05_D21_14" pad="T9"/>
<connect gate="C" pin="IO_L22P_T3_A17_15" pad="H16"/>
<connect gate="C" pin="IO_L23N_T3_35" pad="L2"/>
<connect gate="C" pin="IO_L23N_T3_A02_D18_14" pad="T5"/>
<connect gate="C" pin="IO_L23N_T3_FWE_B_15" pad="J16"/>
<connect gate="C" pin="IO_L23P_T3_35" pad="L3"/>
<connect gate="C" pin="IO_L23P_T3_A03_D19_14" pad="R5"/>
<connect gate="C" pin="IO_L23P_T3_FOE_B_15" pad="J15"/>
<connect gate="C" pin="IO_L24N_T3_35" pad="K2"/>
<connect gate="C" pin="IO_L24N_T3_A00_D16_14" pad="R7"/>
<connect gate="C" pin="IO_L24N_T3_RS0_15" pad="G15"/>
<connect gate="C" pin="IO_L24P_T3_35" pad="K3"/>
<connect gate="C" pin="IO_L24P_T3_A01_D17_14" pad="R6"/>
<connect gate="C" pin="IO_L24P_T3_RS1_15" pad="H14"/>
<connect gate="D" pin="IO_L19N_T3_A09_D25_VREF_14" pad="N6"/>
<connect gate="D" pin="IO_L19N_T3_A21_VREF_15" pad="G12"/>
<connect gate="D" pin="IO_L19N_T3_VREF_35" pad="J4"/>
<connect gate="D" pin="IO_L6N_T0_D08_VREF_14" pad="M12"/>
<connect gate="D" pin="IO_L6N_T0_VREF_15" pad="D9"/>
<connect gate="D" pin="IO_L6N_T0_VREF_34" pad="N4"/>
<connect gate="D" pin="IO_L6N_T0_VREF_35" pad="D5"/>
<connect gate="D" pin="VCCADC_0" pad="G8"/>
<connect gate="D" pin="VCCAUX" pad="L10"/>
<connect gate="D" pin="VCCAUX_2" pad="G10"/>
<connect gate="D" pin="VCCAUX_3" pad="J10"/>
<connect gate="D" pin="VCCAUX_4" pad="K11"/>
<connect gate="D" pin="VCCBATT_0" pad="F8"/>
<connect gate="D" pin="VCCBRAM" pad="F11"/>
<connect gate="D" pin="VCCBRAM_2" pad="E10"/>
<connect gate="D" pin="VCCINT" pad="L8"/>
<connect gate="D" pin="VCCINT_2" pad="F7"/>
<connect gate="D" pin="VCCINT_3" pad="F9"/>
<connect gate="D" pin="VCCINT_4" pad="G6"/>
<connect gate="D" pin="VCCINT_5" pad="H9"/>
<connect gate="D" pin="VCCINT_6" pad="J6"/>
<connect gate="D" pin="VCCINT_7" pad="K9"/>
<connect gate="D" pin="VCCO_0" pad="L6"/>
<connect gate="D" pin="VCCO_14" pad="T11"/>
<connect gate="D" pin="VCCO_14_2" pad="L16"/>
<connect gate="D" pin="VCCO_14_3" pad="M13"/>
<connect gate="D" pin="VCCO_14_4" pad="N10"/>
<connect gate="D" pin="VCCO_14_5" pad="P7"/>
<connect gate="D" pin="VCCO_14_6" pad="R14"/>
<connect gate="D" pin="VCCO_15" pad="J12"/>
<connect gate="D" pin="VCCO_15_2" pad="A16"/>
<connect gate="D" pin="VCCO_15_3" pad="B13"/>
<connect gate="D" pin="VCCO_15_4" pad="C10"/>
<connect gate="D" pin="VCCO_15_5" pad="E14"/>
<connect gate="D" pin="VCCO_15_6" pad="H15"/>
<connect gate="D" pin="VCCO_34" pad="T1"/>
<connect gate="D" pin="VCCO_34_2" pad="M3"/>
<connect gate="D" pin="VCCO_34_3" pad="R4"/>
<connect gate="D" pin="VCCO_35" pad="J2"/>
<connect gate="D" pin="VCCO_35_2" pad="A6"/>
<connect gate="D" pin="VCCO_35_3" pad="B3"/>
<connect gate="D" pin="VCCO_35_4" pad="D7"/>
<connect gate="D" pin="VCCO_35_5" pad="E4"/>
<connect gate="D" pin="VCCO_35_6" pad="F1"/>
<connect gate="E" pin="GND" pad="T16"/>
<connect gate="E" pin="GNDADC_0" pad="G7"/>
<connect gate="E" pin="GND_10" pad="F6"/>
<connect gate="E" pin="GND_11" pad="F10"/>
<connect gate="E" pin="GND_12" pad="F16"/>
<connect gate="E" pin="GND_13" pad="G3"/>
<connect gate="E" pin="GND_14" pad="G9"/>
<connect gate="E" pin="GND_15" pad="G13"/>
<connect gate="E" pin="GND_16" pad="H6"/>
<connect gate="E" pin="GND_17" pad="J9"/>
<connect gate="E" pin="GND_18" pad="J11"/>
<connect gate="E" pin="GND_19" pad="K4"/>
<connect gate="E" pin="GND_2" pad="A1"/>
<connect gate="E" pin="GND_20" pad="K6"/>
<connect gate="E" pin="GND_21" pad="K14"/>
<connect gate="E" pin="GND_22" pad="L1"/>
<connect gate="E" pin="GND_23" pad="L11"/>
<connect gate="E" pin="GND_24" pad="M8"/>
<connect gate="E" pin="GND_25" pad="N5"/>
<connect gate="E" pin="GND_26" pad="N15"/>
<connect gate="E" pin="GND_27" pad="P2"/>
<connect gate="E" pin="GND_28" pad="P12"/>
<connect gate="E" pin="GND_29" pad="R9"/>
<connect gate="E" pin="GND_3" pad="A11"/>
<connect gate="E" pin="GND_30" pad="T6"/>
<connect gate="E" pin="GND_4" pad="B8"/>
<connect gate="E" pin="GND_5" pad="C5"/>
<connect gate="E" pin="GND_6" pad="C15"/>
<connect gate="E" pin="GND_7" pad="D2"/>
<connect gate="E" pin="GND_8" pad="D12"/>
<connect gate="E" pin="GND_9" pad="E9"/>
<connect gate="E" pin="VREFN_0" pad="H7"/>
<connect gate="E" pin="VREFP_0" pad="J8"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2025 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_NAME" value="AMD"/>
<attribute name="MANUFACTURER_PART_NUMBER" value="XC7A100T-2FTG256I"/>
<attribute name="TYPE" value="Embedded"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="STM32F103C8T6" prefix="U">
<gates>
<gate name="A" symbol="STM32F103C8T6"/>
<gate name="B" symbol="STM32F103C8T6_02"/>
</gates>
<devices>
<device name="" package="LQFP48_STM">
<connects>
<connect gate="A" pin="BOOT0" pad="44"/>
<connect gate="A" pin="NRST" pad="7"/>
<connect gate="A" pin="OSC_IN" pad="5"/>
<connect gate="A" pin="OSC_OUT" pad="6"/>
<connect gate="A" pin="PA0-WKUP" pad="10"/>
<connect gate="A" pin="PA1" pad="11"/>
<connect gate="A" pin="PA10" pad="31"/>
<connect gate="A" pin="PA11" pad="32"/>
<connect gate="A" pin="PA12" pad="33"/>
<connect gate="A" pin="PA13" pad="34"/>
<connect gate="A" pin="PA14" pad="37"/>
<connect gate="A" pin="PA15" pad="38"/>
<connect gate="A" pin="PA2" pad="12"/>
<connect gate="A" pin="PA3" pad="13"/>
<connect gate="A" pin="PA4" pad="14"/>
<connect gate="A" pin="PA5" pad="15"/>
<connect gate="A" pin="PA6" pad="16"/>
<connect gate="A" pin="PA7" pad="17"/>
<connect gate="A" pin="PA8" pad="29"/>
<connect gate="A" pin="PA9" pad="30"/>
<connect gate="A" pin="PB0" pad="18"/>
<connect gate="A" pin="PB1" pad="19"/>
<connect gate="A" pin="PB10" pad="21"/>
<connect gate="A" pin="PB11" pad="22"/>
<connect gate="A" pin="PB12" pad="25"/>
<connect gate="A" pin="PB13" pad="26"/>
<connect gate="A" pin="PB14" pad="27"/>
<connect gate="A" pin="PB15" pad="28"/>
<connect gate="A" pin="PB2" pad="20"/>
<connect gate="A" pin="PB3" pad="39"/>
<connect gate="A" pin="PB4" pad="40"/>
<connect gate="A" pin="PB5" pad="41"/>
<connect gate="A" pin="PB6" pad="42"/>
<connect gate="A" pin="PB7" pad="43"/>
<connect gate="A" pin="PB8" pad="45"/>
<connect gate="A" pin="PB9" pad="46"/>
<connect gate="A" pin="PC13" pad="2"/>
<connect gate="A" pin="PC14-OSC32_IN" pad="3"/>
<connect gate="A" pin="PC15-OSC32_OUT" pad="4"/>
<connect gate="B" pin="VBAT" pad="1"/>
<connect gate="B" pin="VDDA" pad="9"/>
<connect gate="B" pin="VDD_1" pad="24"/>
<connect gate="B" pin="VDD_2" pad="36"/>
<connect gate="B" pin="VDD_3" pad="48"/>
<connect gate="B" pin="VSSA" pad="8"/>
<connect gate="B" pin="VSS_1" pad="23"/>
<connect gate="B" pin="VSS_2" pad="35"/>
<connect gate="B" pin="VSS_3" pad="47"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2026 Ultra Librarian. All rights reserved."/>
<attribute name="DATASHEET" value="https://www.st.com/resource/en/datasheet/stm32f103c8.pdf"/>
<attribute name="DESCRIPTION" value="Mainstream Performance line, Arm Cortex-M3 MCU with 64 Kbytes of Flash memory, 72 MHz CPU, motor control, USB and CAN"/>
<attribute name="MANUFACTURER_NAME" value="STMicroelectronics"/>
<attribute name="MANUFACTURER_PART_NUMBER" value="STM32F103C8T6"/>
</technology>
</technologies>
</device>
<device name="LQFP48_STM-M" package="LQFP48_STM-M">
<connects>
<connect gate="A" pin="BOOT0" pad="44"/>
<connect gate="A" pin="NRST" pad="7"/>
<connect gate="A" pin="OSC_IN" pad="5"/>
<connect gate="A" pin="OSC_OUT" pad="6"/>
<connect gate="A" pin="PA0-WKUP" pad="10"/>
<connect gate="A" pin="PA1" pad="11"/>
<connect gate="A" pin="PA10" pad="31"/>
<connect gate="A" pin="PA11" pad="32"/>
<connect gate="A" pin="PA12" pad="33"/>
<connect gate="A" pin="PA13" pad="34"/>
<connect gate="A" pin="PA14" pad="37"/>
<connect gate="A" pin="PA15" pad="38"/>
<connect gate="A" pin="PA2" pad="12"/>
<connect gate="A" pin="PA3" pad="13"/>
<connect gate="A" pin="PA4" pad="14"/>
<connect gate="A" pin="PA5" pad="15"/>
<connect gate="A" pin="PA6" pad="16"/>
<connect gate="A" pin="PA7" pad="17"/>
<connect gate="A" pin="PA8" pad="29"/>
<connect gate="A" pin="PA9" pad="30"/>
<connect gate="A" pin="PB0" pad="18"/>
<connect gate="A" pin="PB1" pad="19"/>
<connect gate="A" pin="PB10" pad="21"/>
<connect gate="A" pin="PB11" pad="22"/>
<connect gate="A" pin="PB12" pad="25"/>
<connect gate="A" pin="PB13" pad="26"/>
<connect gate="A" pin="PB14" pad="27"/>
<connect gate="A" pin="PB15" pad="28"/>
<connect gate="A" pin="PB2" pad="20"/>
<connect gate="A" pin="PB3" pad="39"/>
<connect gate="A" pin="PB4" pad="40"/>
<connect gate="A" pin="PB5" pad="41"/>
<connect gate="A" pin="PB6" pad="42"/>
<connect gate="A" pin="PB7" pad="43"/>
<connect gate="A" pin="PB8" pad="45"/>
<connect gate="A" pin="PB9" pad="46"/>
<connect gate="A" pin="PC13" pad="2"/>
<connect gate="A" pin="PC14-OSC32_IN" pad="3"/>
<connect gate="A" pin="PC15-OSC32_OUT" pad="4"/>
<connect gate="B" pin="VBAT" pad="1"/>
<connect gate="B" pin="VDDA" pad="9"/>
<connect gate="B" pin="VDD_1" pad="24"/>
<connect gate="B" pin="VDD_2" pad="36"/>
<connect gate="B" pin="VDD_3" pad="48"/>
<connect gate="B" pin="VSSA" pad="8"/>
<connect gate="B" pin="VSS_1" pad="23"/>
<connect gate="B" pin="VSS_2" pad="35"/>
<connect gate="B" pin="VSS_3" pad="47"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2026 Ultra Librarian. All rights reserved."/>
<attribute name="DATASHEET" value="https://www.st.com/resource/en/datasheet/stm32f103c8.pdf"/>
<attribute name="DESCRIPTION" value="Mainstream Performance line, Arm Cortex-M3 MCU with 64 Kbytes of Flash memory, 72 MHz CPU, motor control, USB and CAN"/>
<attribute name="MANUFACTURER_NAME" value="STMicroelectronics"/>
<attribute name="MANUFACTURER_PART_NUMBER" value="STM32F103C8T6"/>
</technology>
</technologies>
</device>
<device name="LQFP48_STM-L" package="LQFP48_STM-L">
<connects>
<connect gate="A" pin="BOOT0" pad="44"/>
<connect gate="A" pin="NRST" pad="7"/>
<connect gate="A" pin="OSC_IN" pad="5"/>
<connect gate="A" pin="OSC_OUT" pad="6"/>
<connect gate="A" pin="PA0-WKUP" pad="10"/>
<connect gate="A" pin="PA1" pad="11"/>
<connect gate="A" pin="PA10" pad="31"/>
<connect gate="A" pin="PA11" pad="32"/>
<connect gate="A" pin="PA12" pad="33"/>
<connect gate="A" pin="PA13" pad="34"/>
<connect gate="A" pin="PA14" pad="37"/>
<connect gate="A" pin="PA15" pad="38"/>
<connect gate="A" pin="PA2" pad="12"/>
<connect gate="A" pin="PA3" pad="13"/>
<connect gate="A" pin="PA4" pad="14"/>
<connect gate="A" pin="PA5" pad="15"/>
<connect gate="A" pin="PA6" pad="16"/>
<connect gate="A" pin="PA7" pad="17"/>
<connect gate="A" pin="PA8" pad="29"/>
<connect gate="A" pin="PA9" pad="30"/>
<connect gate="A" pin="PB0" pad="18"/>
<connect gate="A" pin="PB1" pad="19"/>
<connect gate="A" pin="PB10" pad="21"/>
<connect gate="A" pin="PB11" pad="22"/>
<connect gate="A" pin="PB12" pad="25"/>
<connect gate="A" pin="PB13" pad="26"/>
<connect gate="A" pin="PB14" pad="27"/>
<connect gate="A" pin="PB15" pad="28"/>
<connect gate="A" pin="PB2" pad="20"/>
<connect gate="A" pin="PB3" pad="39"/>
<connect gate="A" pin="PB4" pad="40"/>
<connect gate="A" pin="PB5" pad="41"/>
<connect gate="A" pin="PB6" pad="42"/>
<connect gate="A" pin="PB7" pad="43"/>
<connect gate="A" pin="PB8" pad="45"/>
<connect gate="A" pin="PB9" pad="46"/>
<connect gate="A" pin="PC13" pad="2"/>
<connect gate="A" pin="PC14-OSC32_IN" pad="3"/>
<connect gate="A" pin="PC15-OSC32_OUT" pad="4"/>
<connect gate="B" pin="VBAT" pad="1"/>
<connect gate="B" pin="VDDA" pad="9"/>
<connect gate="B" pin="VDD_1" pad="24"/>
<connect gate="B" pin="VDD_2" pad="36"/>
<connect gate="B" pin="VDD_3" pad="48"/>
<connect gate="B" pin="VSSA" pad="8"/>
<connect gate="B" pin="VSS_1" pad="23"/>
<connect gate="B" pin="VSS_2" pad="35"/>
<connect gate="B" pin="VSS_3" pad="47"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2026 Ultra Librarian. All rights reserved."/>
<attribute name="DATASHEET" value="https://www.st.com/resource/en/datasheet/stm32f103c8.pdf"/>
<attribute name="DESCRIPTION" value="Mainstream Performance line, Arm Cortex-M3 MCU with 64 Kbytes of Flash memory, 72 MHz CPU, motor control, USB and CAN"/>
<attribute name="MANUFACTURER_NAME" value="STMicroelectronics"/>
<attribute name="MANUFACTURER_PART_NUMBER" value="STM32F103C8T6"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="K2-6639SP-C4SC-04" prefix="SW">
<gates>
<gate name="A" symbol="SW1_1-2_3-4"/>
</gates>
<devices>
<device name="" package="K2-6639SP-C4SC-04_HRO">
<connects>
<connect gate="A" pin="1" pad="1"/>
<connect gate="A" pin="2" pad="2"/>
<connect gate="A" pin="3" pad="3"/>
<connect gate="A" pin="4" pad="4"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2026 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_NAME" value="HRO Electronics"/>
<attribute name="MANUFACTURER_PART_NUMBER" value="K2-6639SP-C4SC-04"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="TC1262-3.3VDBTR" prefix="U">
<gates>
<gate name="A" symbol="TC1262-3.3VDBTR"/>
</gates>
<devices>
<device name="" package="SOT-223_3MC_MCH">
<connects>
<connect gate="A" pin="GND" pad="2"/>
<connect gate="A" pin="VIN" pad="1"/>
<connect gate="A" pin="VOUT" pad="3"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2026 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_NAME" value="Microchip"/>
<attribute name="MANUFACTURER_PART_NUMBER" value="TC1262-3.3VDBTR"/>
</technology>
</technologies>
</device>
<device name="SOT-223_3MC_MCH-M" package="SOT-223_3MC_MCH-M">
<connects>
<connect gate="A" pin="GND" pad="2"/>
<connect gate="A" pin="VIN" pad="1"/>
<connect gate="A" pin="VOUT" pad="3"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2026 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_NAME" value="Microchip"/>
<attribute name="MANUFACTURER_PART_NUMBER" value="TC1262-3.3VDBTR"/>
</technology>
</technologies>
</device>
<device name="SOT-223_3MC_MCH-L" package="SOT-223_3MC_MCH-L">
<connects>
<connect gate="A" pin="GND" pad="2"/>
<connect gate="A" pin="VIN" pad="1"/>
<connect gate="A" pin="VOUT" pad="3"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2026 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_NAME" value="Microchip"/>
<attribute name="MANUFACTURER_PART_NUMBER" value="TC1262-3.3VDBTR"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
</devicesets>
</library>
</drawing>
</eagle>
