<?xml version="1.0" encoding="utf-8"?>
<!DOCTYPE eagle SYSTEM "eagle.dtd">
<eagle version="7.4.0">
<drawing>
<library>
<packages>
<package name="46765-1001_MOL">
</package>
<package name="CP-40-1_ADI">
</package>
<package name="CP-40-1_ADI-M">
</package>
<package name="CP-40-1_ADI-L">
</package>
<package name="CP-32-12_ADI">
</package>
<package name="CP-32-12_ADI-M">
</package>
<package name="CP-32-12_ADI-L">
</package>
<package name="FC68371_CLF">
</package>
<package name="DG984-1_MNC">
</package>
<package name="DG984-1_MNC-M">
</package>
<package name="DG984-1_MNC-L">
</package>
<package name="UTQFN-24_PF_LIT">
</package>
<package name="UTQFN-24_PF_LIT-L">
</package>
<package name="UTQFN-24_PF_LIT-M">
</package>
<package name="PBS32">
</package>
<package name="PBS32-L">
</package>
<package name="PBS32-M">
</package>
<package name="QFN36_6X6MC_MCH">
</package>
<package name="QFN36_6X6MC_MCH-L">
</package>
<package name="QFN36_6X6MC_MCH-M">
</package>
<package name="FTG256_AMD">
</package>
<package name="FTG256_AMD-M">
</package>
<package name="FTG256_AMD-L">
</package>
</packages>
<symbols>
<symbol name="46765-0001">
<pin name="HOT_PLUG_DETECT" direction="pas"/>
<pin name="UTILITY" direction="pas"/>
<pin name="TMDS_DATA2+"/>
<pin name="TMDS_DATA2_SHIELD"/>
<pin name="TMDS_DATA2-"/>
<pin name="TMDS_DATA1+"/>
<pin name="TMDS_DATA1_SHIELD"/>
<pin name="TMDS_DATA1-"/>
<pin name="TMDS_DATA0+"/>
<pin name="TMDS_DATA0_SHIELD"/>
<pin name="TMDS_DATA0-"/>
<pin name="TMDS_CLOCK+" direction="pas"/>
<pin name="TMDS_CLOCK_SHIELD" direction="pas"/>
<pin name="TMDS_CLOCK-" direction="pas"/>
<pin name="CEC" direction="pas"/>
<pin name="DDC/CEC_GROUND" direction="pas"/>
<pin name="SCL" direction="pas"/>
<pin name="SDA" direction="pas"/>
<pin name="POWER_+5V" direction="pwr"/>
</symbol>
<symbol name="AD9714BCPZ">
<pin name="DB5" direction="pas"/>
<pin name="DB4" direction="pas"/>
<pin name="DB3" direction="pas"/>
<pin name="DB2" direction="pas"/>
<pin name="DVDDIO" direction="pwr"/>
<pin name="DVSS" direction="pas"/>
<pin name="DVDD" direction="pwr"/>
<pin name="DB1" direction="pas"/>
<pin name="DB0" direction="pas"/>
<pin name="NC_2" direction="pas"/>
<pin name="NC_3" direction="pas"/>
<pin name="NC_4" direction="pas"/>
<pin name="NC_5" direction="pas"/>
<pin name="NC_6" direction="pas"/>
<pin name="NC" direction="pas"/>
<pin name="DCLKIO" direction="pas"/>
<pin name="CVDD" direction="pwr"/>
<pin name="CLKIN" direction="pas"/>
<pin name="CVSS" direction="pas"/>
<pin name="CMLQ" direction="pas"/>
<pin name="RLQN" direction="pas"/>
<pin name="QOUTN" direction="pas"/>
<pin name="QOUTP" direction="pas"/>
<pin name="RLQP" direction="pas"/>
<pin name="AVSS" direction="pas"/>
<pin name="AVDD" direction="pwr"/>
<pin name="RLIP" direction="pas"/>
<pin name="IOUTP" direction="pas"/>
<pin name="IOUTN" direction="pas"/>
<pin name="RLIN" direction="pas"/>
<pin name="CMLI" direction="pas"/>
<pin name="FSADJQ/_AUXQ" direction="pas"/>
<pin name="FSADJI/AUXI" direction="pas"/>
<pin name="REFIO" direction="pas"/>
<pin name="RESET/_PINMD" direction="pas"/>
<pin name="SCLK/CLKMD" direction="pas"/>
<pin name="SDIO/_FORMAT" direction="pas"/>
<pin name="CS/PWRDN" direction="pas"/>
<pin name="DB7(MSB)" direction="pas"/>
<pin name="DB6" direction="pas"/>
<pin name="EP" direction="pas"/>
</symbol>
<symbol name="ADF4356">
<pin name="CLK" direction="in"/>
<pin name="DATA" direction="in"/>
<pin name="LE" direction="in"/>
<pin name="CE" direction="in"/>
<pin name="AVDD_2" direction="pwr"/>
<pin name="VP" direction="pwr"/>
<pin name="CPOUT" direction="out"/>
<pin name="CPGND" direction="pas"/>
<pin name="AGND_2" direction="pas"/>
<pin name="VRF" direction="pwr"/>
<pin name="RFOUTA+" direction="out"/>
<pin name="RFOUTA-" direction="out"/>
<pin name="AGNDRF" direction="pas"/>
<pin name="RFOUTB+" direction="out"/>
<pin name="RFOUTB-" direction="out"/>
<pin name="AVDD" direction="pwr"/>
<pin name="VVCO" direction="pwr"/>
<pin name="AGNDVDO" direction="pas"/>
<pin name="VREGVCO" direction="pwr"/>
<pin name="VTUNE" direction="in"/>
<pin name="AGNDVCO" direction="pas"/>
<pin name="NIC" direction="nc"/>
<pin name="VREF" direction="pwr"/>
<pin name="VBIAS" direction="pwr"/>
<pin name="CREG1" direction="out"/>
<pin name="PDBRF" direction="pas"/>
<pin name="DVDD" direction="pwr"/>
<pin name="REFINB" direction="in"/>
<pin name="REFINA" direction="in"/>
<pin name="MUXOUT" direction="out"/>
<pin name="SDGND" direction="pas"/>
<pin name="CREG2" direction="out"/>
<pin name="AGND" direction="pas"/>
</symbol>
<symbol name="FC68371">
<pin name="1" direction="pas"/>
<pin name="2" direction="pas"/>
</symbol>
<symbol name="HSWA4-63DR+">
<pin name="GND_2" direction="pas"/>
<pin name="GND_3" direction="pas"/>
<pin name="GND_4" direction="pas"/>
<pin name="GND_5" direction="pas"/>
<pin name="RF4"/>
<pin name="GND_6" direction="pas"/>
<pin name="GND_7" direction="pas"/>
<pin name="RF3"/>
<pin name="GND_8" direction="pas"/>
<pin name="GND_9" direction="pas"/>
<pin name="RF2"/>
<pin name="GND_10" direction="pas"/>
<pin name="GND_11" direction="pas"/>
<pin name="RF1"/>
<pin name="GND_12" direction="pas"/>
<pin name="VDD" direction="pwr"/>
<pin name="CONTROL1" direction="in"/>
<pin name="CONTROL2" direction="in"/>
<pin name="CONTROL3" direction="in"/>
<pin name="GND_13" direction="pas"/>
<pin name="GND_14" direction="pas"/>
<pin name="RF_COM"/>
<pin name="GND_15" direction="pas"/>
<pin name="GND_16" direction="pas"/>
<pin name="GND" direction="pas"/>
</symbol>
<symbol name="LTC5588IPF-1TRPBF">
<pin name="EN" direction="in"/>
<pin name="GND_2" direction="pwr"/>
<pin name="LOP" direction="in"/>
<pin name="LOM" direction="in"/>
<pin name="GND_3" direction="pwr"/>
<pin name="NC_2" direction="nc"/>
<pin name="LINOPT" direction="in"/>
<pin name="GND_4" direction="pwr"/>
<pin name="BBMQ" direction="in"/>
<pin name="BBPQ" direction="in"/>
<pin name="GND_5" direction="pwr"/>
<pin name="GNDRF_2" direction="pwr"/>
<pin name="NC_3" direction="nc"/>
<pin name="GNDRF_3" direction="pwr"/>
<pin name="NC" direction="nc"/>
<pin name="RF" direction="out"/>
<pin name="GNDRF_4" direction="pwr"/>
<pin name="VCC2" direction="pwr"/>
<pin name="GNDRF_5" direction="pwr"/>
<pin name="GND_6" direction="pwr"/>
<pin name="BBPI" direction="in"/>
<pin name="BBMI" direction="in"/>
<pin name="GND_7" direction="pwr"/>
<pin name="VCC1" direction="pwr"/>
<pin name="GND" direction="pwr"/>
<pin name="GNDRF" direction="pwr"/>
</symbol>
<symbol name="TVP5150AM1_PBS_32">
<pin name="AIP1A" direction="in"/>
<pin name="AIP1B" direction="in"/>
<pin name="PLL_AGND" direction="pwr"/>
<pin name="PLL_AVDD" direction="pwr"/>
<pin name="XTAL1/OSC" direction="in"/>
<pin name="XTAL2" direction="out"/>
<pin name="NSUB" direction="in"/>
<pin name="!RESETB" direction="in"/>
<pin name="SCLK" direction="out"/>
<pin name="IO_DVDD" direction="pwr"/>
<pin name="YOUT7/I2CSEL"/>
<pin name="YOUT6" direction="out"/>
<pin name="YOUT5" direction="out"/>
<pin name="YOUT4" direction="out"/>
<pin name="YOUT3" direction="out"/>
<pin name="YOUT2" direction="out"/>
<pin name="YOUT1" direction="out"/>
<pin name="YOUT0" direction="out"/>
<pin name="DGND" direction="pwr"/>
<pin name="DVDD" direction="pwr"/>
<pin name="SCL"/>
<pin name="SDA"/>
<pin name="FID/GLCO" direction="out"/>
<pin name="VSYNC/PALI" direction="out"/>
<pin name="HSYNC" direction="out"/>
<pin name="AVID" direction="out"/>
<pin name="INTREQ/GPCL/VBLK"/>
<pin name="PDN" direction="in"/>
<pin name="REFP" direction="in"/>
<pin name="REFM" direction="in"/>
<pin name="CH1_AGND" direction="in"/>
<pin name="CH1_AVDD" direction="in"/>
</symbol>
<symbol name="USB2513BI-AEZG">
<pin name="USBDM_DN1/PRT_DIS_M1"/>
<pin name="USBDP_DN1/PRT_DIS_P1"/>
<pin name="USBDM_DN2/PRT_DIS_M2"/>
<pin name="USBDP_DN2/PRT_DIS_P2"/>
<pin name="VDDA33_2" direction="pwr"/>
<pin name="USBDM_DN3/PRT_DIS_M3"/>
<pin name="USBDP_DN3/PRT_DIS_P3"/>
<pin name="NC_2" direction="nc"/>
<pin name="NC_3" direction="nc"/>
<pin name="VDDA33_3" direction="pwr"/>
<pin name="TEST"/>
<pin name="PRTPWR1/BC_EN1"/>
<pin name="OCS_N1"/>
<pin name="CRFILT"/>
<pin name="VDD33_2" direction="pwr"/>
<pin name="PRTPWR2/BC_EN2"/>
<pin name="OCS_N2"/>
<pin name="PRTPWR3/BC_EN3"/>
<pin name="OCS_N3"/>
<pin name="NC_4" direction="nc"/>
<pin name="NC" direction="nc"/>
<pin name="SDA/SMBDATA/NON_REM1"/>
<pin name="VDD33" direction="pwr"/>
<pin name="SCL/SMBCLK/CFG_SEL0"/>
<pin name="HS_IND/CFG_SEL1"/>
<pin name="RESET_N"/>
<pin name="VBUS_DET"/>
<pin name="SUSP_IND/LOCAL_PWR/NON_REM0"/>
<pin name="VDDA33_4" direction="pwr"/>
<pin name="USBDM_UP"/>
<pin name="USBDP_UP"/>
<pin name="XTALOUT" direction="out"/>
<pin name="XTALIN/CLKIN" direction="in"/>
<pin name="PLLFILT"/>
<pin name="RBIAS"/>
<pin name="VDDA33" direction="pwr"/>
<pin name="EPAD" direction="pas"/>
</symbol>
<symbol name="XC7A100T-2FTG256I_A">
<pin name="GND_2" direction="pas"/>
<pin name="IO_L8N_T1_AD14N_35"/>
<pin name="IO_L4N_T0_35"/>
<pin name="IO_L3N_T0_DQS_AD5N_35"/>
<pin name="IO_L3P_T0_DQS_AD5P_35"/>
<pin name="VCCO_35_2" direction="pwr"/>
<pin name="IO_L1N_T0_AD4N_35"/>
<pin name="IO_L2P_T0_AD8P_15"/>
<pin name="IO_L2N_T0_AD8N_15"/>
<pin name="IO_L3N_T0_DQS_AD1N_15"/>
<pin name="GND_3" direction="pas"/>
<pin name="IO_L5N_T0_AD9N_15"/>
<pin name="IO_L7P_T1_AD2P_15"/>
<pin name="IO_L7N_T1_AD2N_15"/>
<pin name="IO_L9N_T1_DQS_AD3N_15"/>
<pin name="VCCO_15_2" direction="pwr"/>
<pin name="IO_L9N_T1_DQS_AD7N_35"/>
<pin name="IO_L8P_T1_AD14P_35"/>
<pin name="VCCO_35_3" direction="pwr"/>
<pin name="IO_L4P_T0_35"/>
<pin name="IO_L2N_T0_AD12N_35"/>
<pin name="IO_L2P_T0_AD12P_35"/>
<pin name="IO_L1P_T0_AD4P_35"/>
<pin name="GND_4" direction="pas"/>
<pin name="IO_L3P_T0_DQS_AD1P_15"/>
<pin name="IO_L4P_T0_15"/>
<pin name="IO_L4N_T0_15"/>
<pin name="IO_L5P_T0_AD9P_15"/>
<pin name="VCCO_15_3" direction="pwr"/>
<pin name="IO_L8N_T1_AD10N_15"/>
<pin name="IO_L9P_T1_DQS_AD3P_15"/>
<pin name="IO_L10N_T1_AD11N_15"/>
<pin name="IO_L9P_T1_DQS_AD7P_35"/>
<pin name="IO_L7N_T1_AD6N_35"/>
<pin name="IO_L7P_T1_AD6P_35"/>
<pin name="IO_L12N_T1_MRCC_35"/>
<pin name="GND_5" direction="pas"/>
<pin name="IO_L5N_T0_AD13N_35"/>
<pin name="IO_L5P_T0_AD13P_35"/>
<pin name="IO_L1P_T0_AD0P_15"/>
<pin name="IO_L1N_T0_AD0N_15"/>
<pin name="VCCO_15_4" direction="pwr"/>
<pin name="IO_L11P_T1_SRCC_15"/>
<pin name="IO_L11N_T1_SRCC_15"/>
<pin name="IO_L12N_T1_MRCC_15"/>
<pin name="IO_L8P_T1_AD10P_15"/>
<pin name="GND_6" direction="pas"/>
<pin name="IO_L10P_T1_AD11P_15"/>
<pin name="IO_L10N_T1_AD15N_35"/>
<pin name="GND_7" direction="pas"/>
<pin name="IO_L11N_T1_SRCC_35"/>
<pin name="IO_L12P_T1_MRCC_35"/>
<pin name="IO_L6N_T0_VREF_35"/>
<pin name="IO_L6P_T0_35"/>
<pin name="VCCO_35_4" direction="pwr"/>
<pin name="IO_L6P_T0_15"/>
<pin name="IO_L6N_T0_VREF_15"/>
<pin name="IO_0_15"/>
<pin name="IO_L14N_T2_SRCC_15"/>
<pin name="GND_8" direction="pas"/>
<pin name="IO_L12P_T1_MRCC_15"/>
<pin name="IO_L15P_T2_DQS_15"/>
<pin name="IO_L15N_T2_DQS_ADV_B_15"/>
<pin name="IO_L17N_T2_A25_15"/>
<pin name="IO_L15N_T2_DQS_35"/>
<pin name="IO_L10P_T1_AD15P_35"/>
<pin name="IO_L11P_T1_SRCC_35"/>
<pin name="VCCO_35_5" direction="pwr"/>
<pin name="IO_L13N_T2_MRCC_35"/>
<pin name="IO_0_35"/>
<pin name="CFGBVS_0" direction="in"/>
<pin name="CCLK_0"/>
<pin name="GND_9" direction="pas"/>
<pin name="VCCBRAM" direction="pwr"/>
<pin name="IO_L14P_T2_SRCC_15"/>
<pin name="IO_L13P_T2_MRCC_15"/>
<pin name="IO_L13N_T2_MRCC_15"/>
<pin name="VCCO_15" direction="pwr"/>
<pin name="IO_L18N_T2_A23_15"/>
<pin name="IO_L17P_T2_A26_15"/>
<pin name="VCCO_35" direction="pwr"/>
<pin name="IO_L15P_T2_DQS_35"/>
<pin name="IO_L14N_T2_SRCC_35"/>
<pin name="IO_L14P_T2_SRCC_35"/>
<pin name="IO_L13P_T2_MRCC_35"/>
<pin name="GND" direction="pas"/>
</symbol>
<symbol name="XC7A100T-2FTG256I_B">
<pin name="VCCINT_2" direction="pwr"/>
<pin name="VCCBATT_0" direction="pwr"/>
<pin name="VCCINT_3" direction="pwr"/>
<pin name="GND_2" direction="pas"/>
<pin name="VCCBRAM" direction="pwr"/>
<pin name="IO_L16P_T2_A28_15"/>
<pin name="IO_L16N_T2_A27_15"/>
<pin name="IO_L21N_T3_DQS_A18_15"/>
<pin name="IO_L18P_T2_A24_15"/>
<pin name="GND_3" direction="pas"/>
<pin name="IO_L17N_T2_35"/>
<pin name="IO_L17P_T2_35"/>
<pin name="GND_4" direction="pas"/>
<pin name="IO_L16N_T2_35"/>
<pin name="IO_L16P_T2_35"/>
<pin name="VCCINT_4" direction="pwr"/>
<pin name="GNDADC_0" direction="pas"/>
<pin name="VCCADC_0" direction="pwr"/>
<pin name="GND_5" direction="pas"/>
<pin name="VCCAUX_2" direction="pwr"/>
<pin name="IO_25_15"/>
<pin name="IO_L19N_T3_A21_VREF_15"/>
<pin name="GND_6" direction="pas"/>
<pin name="IO_L21P_T3_DQS_15"/>
<pin name="IO_L24N_T3_RS0_15"/>
<pin name="IO_L22N_T3_A16_15"/>
<pin name="IO_L20N_T3_35"/>
<pin name="IO_L20P_T3_35"/>
<pin name="IO_L21N_T3_DQS_35"/>
<pin name="IO_L18N_T2_35"/>
<pin name="IO_L18P_T2_35"/>
<pin name="GND_7" direction="pas"/>
<pin name="VREFN_0" direction="pwr"/>
<pin name="VP_0" direction="in"/>
<pin name="VCCINT_5" direction="pwr"/>
<pin name="DONE_0"/>
<pin name="IO_L19P_T3_A22_15"/>
<pin name="IO_L20P_T3_A20_15"/>
<pin name="IO_L20N_T3_A19_15"/>
<pin name="IO_L24P_T3_RS1_15"/>
<pin name="VCCO_15_2" direction="pwr"/>
<pin name="IO_L22P_T3_A17_15"/>
<pin name="IO_L22N_T3_35"/>
<pin name="VCCO_35" direction="pwr"/>
<pin name="IO_L21P_T3_DQS_35"/>
<pin name="IO_L19N_T3_VREF_35"/>
<pin name="IO_L19P_T3_35"/>
<pin name="VCCINT_6" direction="pwr"/>
<pin name="VN_0" direction="in"/>
<pin name="VREFP_0" direction="pwr"/>
<pin name="GND_8" direction="pas"/>
<pin name="VCCAUX_3" direction="pwr"/>
<pin name="GND_9" direction="pas"/>
<pin name="VCCO_15" direction="pwr"/>
<pin name="IO_L1P_T0_D00_MOSI_14"/>
<pin name="IO_L1N_T0_D01_DIN_14"/>
<pin name="IO_L23P_T3_FOE_B_15"/>
<pin name="IO_L23N_T3_FWE_B_15"/>
<pin name="IO_L22P_T3_35"/>
<pin name="IO_L24N_T3_35"/>
<pin name="IO_L24P_T3_35"/>
<pin name="GND_10" direction="pas"/>
<pin name="IO_25_35"/>
<pin name="GND_11" direction="pas"/>
<pin name="DXN_0" direction="pas"/>
<pin name="DXP_0" direction="pas"/>
<pin name="VCCINT_7" direction="pwr"/>
<pin name="INIT_B_0"/>
<pin name="VCCAUX_4" direction="pwr"/>
<pin name="IO_0_14"/>
<pin name="IO_L5P_T0_D06_14"/>
<pin name="GND_12" direction="pas"/>
<pin name="IO_L2P_T0_D02_14"/>
<pin name="IO_L2N_T0_D03_14"/>
<pin name="GND_13" direction="pas"/>
<pin name="IO_L23N_T3_35"/>
<pin name="IO_L23P_T3_35"/>
<pin name="IO_L1P_T0_34"/>
<pin name="IO_0_34"/>
<pin name="VCCO_0" direction="pwr"/>
<pin name="TCK_0" direction="in"/>
<pin name="VCCINT" direction="pwr"/>
<pin name="PROGRAM_B_0" direction="in"/>
<pin name="VCCAUX" direction="pwr"/>
<pin name="GND" direction="pas"/>
<pin name="IO_L6P_T0_FCS_B_14"/>
</symbol>
<symbol name="XC7A100T-2FTG256I_C">
<pin name="IO_L5N_T0_D07_14"/>
<pin name="IO_L4P_T0_D04_14"/>
<pin name="IO_L3P_T0_DQS_PUDC_B_14"/>
<pin name="VCCO_14_2" direction="pwr"/>
<pin name="IO_L2N_T0_34"/>
<pin name="IO_L2P_T0_34"/>
<pin name="VCCO_34_2" direction="pwr"/>
<pin name="IO_L1N_T0_34"/>
<pin name="IO_L6P_T0_34"/>
<pin name="IO_L19P_T3_A10_D26_14"/>
<pin name="TMS_0" direction="in"/>
<pin name="GND_2" direction="pas"/>
<pin name="M0_0" direction="in"/>
<pin name="M1_0" direction="in"/>
<pin name="M2_0" direction="in"/>
<pin name="IO_L6N_T0_D08_VREF_14"/>
<pin name="VCCO_14_3" direction="pwr"/>
<pin name="IO_L4N_T0_D05_14"/>
<pin name="IO_L3N_T0_DQS_EMCCLK_14"/>
<pin name="IO_L7P_T1_D09_14"/>
<pin name="IO_L4P_T0_34"/>
<pin name="IO_L3N_T0_DQS_34"/>
<pin name="IO_L3P_T0_DQS_34"/>
<pin name="IO_L6N_T0_VREF_34"/>
<pin name="GND_3" direction="pas"/>
<pin name="IO_L19N_T3_A09_D25_VREF_14"/>
<pin name="TDI_0" direction="in"/>
<pin name="TDO_0" direction="out"/>
<pin name="IO_L18P_T2_A12_D28_14"/>
<pin name="VCCO_14_4" direction="pwr"/>
<pin name="IO_L13P_T2_MRCC_14"/>
<pin name="IO_L13N_T2_MRCC_14"/>
<pin name="IO_L11P_T1_SRCC_14"/>
<pin name="IO_L12P_T1_MRCC_14"/>
<pin name="GND_4" direction="pas"/>
<pin name="IO_L7N_T1_D10_14"/>
<pin name="IO_L4N_T0_34"/>
<pin name="GND_5" direction="pas"/>
<pin name="IO_L5N_T0_34"/>
<pin name="IO_L5P_T0_34"/>
<pin name="IO_L10P_T1_34"/>
<pin name="IO_25_14"/>
<pin name="VCCO_14_5" direction="pwr"/>
<pin name="IO_L20P_T3_A08_D24_14"/>
<pin name="IO_L18N_T2_A11_D27_14"/>
<pin name="IO_L14P_T2_SRCC_14"/>
<pin name="IO_L14N_T2_SRCC_14"/>
<pin name="GND_6" direction="pas"/>
<pin name="IO_L11N_T1_SRCC_14"/>
<pin name="IO_L12N_T1_MRCC_14"/>
<pin name="IO_L8P_T1_D11_14"/>
<pin name="IO_L8N_T1_D12_14"/>
<pin name="IO_L7N_T1_34"/>
<pin name="IO_L7P_T1_34"/>
<pin name="IO_L8P_T1_34"/>
<pin name="VCCO_34_3" direction="pwr"/>
<pin name="IO_L23P_T3_A03_D19_14"/>
<pin name="IO_L24P_T3_A01_D17_14"/>
<pin name="IO_L24N_T3_A00_D16_14"/>
<pin name="IO_L20N_T3_A07_D23_14"/>
<pin name="GND_7" direction="pas"/>
<pin name="IO_L17P_T2_A14_D30_14"/>
<pin name="IO_L17N_T2_A13_D29_14"/>
<pin name="IO_L15P_T2_DQS_RDWR_B_14"/>
<pin name="IO_L16P_T2_CSI_B_14"/>
<pin name="VCCO_14_6" direction="pwr"/>
<pin name="IO_L9P_T1_DQS_14"/>
<pin name="IO_L9N_T1_DQS_D13_14"/>
<pin name="VCCO_34" direction="pwr"/>
<pin name="IO_L8N_T1_34"/>
<pin name="IO_L9N_T1_DQS_34"/>
<pin name="IO_L9P_T1_DQS_34"/>
<pin name="IO_L23N_T3_A02_D18_14"/>
<pin name="GND_8" direction="pas"/>
<pin name="IO_L21P_T3_DQS_14"/>
<pin name="IO_L21N_T3_DQS_A06_D22_14"/>
<pin name="IO_L22P_T3_A05_D21_14"/>
<pin name="IO_L22N_T3_A04_D20_14"/>
<pin name="VCCO_14" direction="pwr"/>
<pin name="IO_L15N_T2_DQS_DOUT_CSO_B_14"/>
<pin name="IO_L16N_T2_A15_D31_14"/>
<pin name="IO_L10P_T1_D14_14"/>
<pin name="IO_L10N_T1_D15_14"/>
<pin name="GND" direction="pas"/>
</symbol>
</symbols>
<devicesets>
<deviceset name="467651001" prefix="U">
<gates>
<gate name="A" symbol="46765-0001"/>
</gates>
<devices>
<device name="" package="46765-1001_MOL">
<connects>
<connect gate="A" pin="CEC" pad="15"/>
<connect gate="A" pin="DDC/CEC_GROUND" pad="16"/>
<connect gate="A" pin="HOT_PLUG_DETECT" pad="1"/>
<connect gate="A" pin="POWER_+5V" pad="19"/>
<connect gate="A" pin="SCL" pad="17"/>
<connect gate="A" pin="SDA" pad="18"/>
<connect gate="A" pin="TMDS_CLOCK+" pad="12"/>
<connect gate="A" pin="TMDS_CLOCK-" pad="14"/>
<connect gate="A" pin="TMDS_CLOCK_SHIELD" pad="13"/>
<connect gate="A" pin="TMDS_DATA0+" pad="9"/>
<connect gate="A" pin="TMDS_DATA0-" pad="11"/>
<connect gate="A" pin="TMDS_DATA0_SHIELD" pad="10"/>
<connect gate="A" pin="TMDS_DATA1+" pad="6"/>
<connect gate="A" pin="TMDS_DATA1-" pad="8"/>
<connect gate="A" pin="TMDS_DATA1_SHIELD" pad="7"/>
<connect gate="A" pin="TMDS_DATA2+" pad="3"/>
<connect gate="A" pin="TMDS_DATA2-" pad="5"/>
<connect gate="A" pin="TMDS_DATA2_SHIELD" pad="4"/>
<connect gate="A" pin="UTILITY" pad="2"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2025 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="467651001"/>
<attribute name="MFR_NAME" value="Molex Connector Corporation"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="AD9714BCPZ" prefix="U">
<gates>
<gate name="A" symbol="AD9714BCPZ"/>
</gates>
<devices>
<device name="" package="CP-40-1_ADI">
<connects>
<connect gate="A" pin="AVDD" pad="26"/>
<connect gate="A" pin="AVSS" pad="25"/>
<connect gate="A" pin="CLKIN" pad="18"/>
<connect gate="A" pin="CMLI" pad="31"/>
<connect gate="A" pin="CMLQ" pad="20"/>
<connect gate="A" pin="CS/PWRDN" pad="38"/>
<connect gate="A" pin="CVDD" pad="17"/>
<connect gate="A" pin="CVSS" pad="19"/>
<connect gate="A" pin="DB0" pad="9"/>
<connect gate="A" pin="DB1" pad="8"/>
<connect gate="A" pin="DB2" pad="4"/>
<connect gate="A" pin="DB3" pad="3"/>
<connect gate="A" pin="DB4" pad="2"/>
<connect gate="A" pin="DB5" pad="1"/>
<connect gate="A" pin="DB6" pad="40"/>
<connect gate="A" pin="DB7(MSB)" pad="39"/>
<connect gate="A" pin="DCLKIO" pad="16"/>
<connect gate="A" pin="DVDD" pad="7"/>
<connect gate="A" pin="DVDDIO" pad="5"/>
<connect gate="A" pin="DVSS" pad="6"/>
<connect gate="A" pin="EP" pad="41"/>
<connect gate="A" pin="FSADJI/AUXI" pad="33"/>
<connect gate="A" pin="FSADJQ/_AUXQ" pad="32"/>
<connect gate="A" pin="IOUTN" pad="29"/>
<connect gate="A" pin="IOUTP" pad="28"/>
<connect gate="A" pin="NC" pad="15"/>
<connect gate="A" pin="NC_2" pad="10"/>
<connect gate="A" pin="NC_3" pad="11"/>
<connect gate="A" pin="NC_4" pad="12"/>
<connect gate="A" pin="NC_5" pad="13"/>
<connect gate="A" pin="NC_6" pad="14"/>
<connect gate="A" pin="QOUTN" pad="22"/>
<connect gate="A" pin="QOUTP" pad="23"/>
<connect gate="A" pin="REFIO" pad="34"/>
<connect gate="A" pin="RESET/_PINMD" pad="35"/>
<connect gate="A" pin="RLIN" pad="30"/>
<connect gate="A" pin="RLIP" pad="27"/>
<connect gate="A" pin="RLQN" pad="21"/>
<connect gate="A" pin="RLQP" pad="24"/>
<connect gate="A" pin="SCLK/CLKMD" pad="36"/>
<connect gate="A" pin="SDIO/_FORMAT" pad="37"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2025 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="AD9714BCPZ"/>
<attribute name="MFR_NAME" value="Analog Devices Inc"/>
</technology>
</technologies>
</device>
<device name="CP-40-1_ADI-M" package="CP-40-1_ADI-M">
<connects>
<connect gate="A" pin="AVDD" pad="26"/>
<connect gate="A" pin="AVSS" pad="25"/>
<connect gate="A" pin="CLKIN" pad="18"/>
<connect gate="A" pin="CMLI" pad="31"/>
<connect gate="A" pin="CMLQ" pad="20"/>
<connect gate="A" pin="CS/PWRDN" pad="38"/>
<connect gate="A" pin="CVDD" pad="17"/>
<connect gate="A" pin="CVSS" pad="19"/>
<connect gate="A" pin="DB0" pad="9"/>
<connect gate="A" pin="DB1" pad="8"/>
<connect gate="A" pin="DB2" pad="4"/>
<connect gate="A" pin="DB3" pad="3"/>
<connect gate="A" pin="DB4" pad="2"/>
<connect gate="A" pin="DB5" pad="1"/>
<connect gate="A" pin="DB6" pad="40"/>
<connect gate="A" pin="DB7(MSB)" pad="39"/>
<connect gate="A" pin="DCLKIO" pad="16"/>
<connect gate="A" pin="DVDD" pad="7"/>
<connect gate="A" pin="DVDDIO" pad="5"/>
<connect gate="A" pin="DVSS" pad="6"/>
<connect gate="A" pin="EP" pad="41"/>
<connect gate="A" pin="FSADJI/AUXI" pad="33"/>
<connect gate="A" pin="FSADJQ/_AUXQ" pad="32"/>
<connect gate="A" pin="IOUTN" pad="29"/>
<connect gate="A" pin="IOUTP" pad="28"/>
<connect gate="A" pin="NC" pad="15"/>
<connect gate="A" pin="NC_2" pad="10"/>
<connect gate="A" pin="NC_3" pad="11"/>
<connect gate="A" pin="NC_4" pad="12"/>
<connect gate="A" pin="NC_5" pad="13"/>
<connect gate="A" pin="NC_6" pad="14"/>
<connect gate="A" pin="QOUTN" pad="22"/>
<connect gate="A" pin="QOUTP" pad="23"/>
<connect gate="A" pin="REFIO" pad="34"/>
<connect gate="A" pin="RESET/_PINMD" pad="35"/>
<connect gate="A" pin="RLIN" pad="30"/>
<connect gate="A" pin="RLIP" pad="27"/>
<connect gate="A" pin="RLQN" pad="21"/>
<connect gate="A" pin="RLQP" pad="24"/>
<connect gate="A" pin="SCLK/CLKMD" pad="36"/>
<connect gate="A" pin="SDIO/_FORMAT" pad="37"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2025 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="AD9714BCPZ"/>
<attribute name="MFR_NAME" value="Analog Devices Inc"/>
</technology>
</technologies>
</device>
<device name="CP-40-1_ADI-L" package="CP-40-1_ADI-L">
<connects>
<connect gate="A" pin="AVDD" pad="26"/>
<connect gate="A" pin="AVSS" pad="25"/>
<connect gate="A" pin="CLKIN" pad="18"/>
<connect gate="A" pin="CMLI" pad="31"/>
<connect gate="A" pin="CMLQ" pad="20"/>
<connect gate="A" pin="CS/PWRDN" pad="38"/>
<connect gate="A" pin="CVDD" pad="17"/>
<connect gate="A" pin="CVSS" pad="19"/>
<connect gate="A" pin="DB0" pad="9"/>
<connect gate="A" pin="DB1" pad="8"/>
<connect gate="A" pin="DB2" pad="4"/>
<connect gate="A" pin="DB3" pad="3"/>
<connect gate="A" pin="DB4" pad="2"/>
<connect gate="A" pin="DB5" pad="1"/>
<connect gate="A" pin="DB6" pad="40"/>
<connect gate="A" pin="DB7(MSB)" pad="39"/>
<connect gate="A" pin="DCLKIO" pad="16"/>
<connect gate="A" pin="DVDD" pad="7"/>
<connect gate="A" pin="DVDDIO" pad="5"/>
<connect gate="A" pin="DVSS" pad="6"/>
<connect gate="A" pin="EP" pad="41"/>
<connect gate="A" pin="FSADJI/AUXI" pad="33"/>
<connect gate="A" pin="FSADJQ/_AUXQ" pad="32"/>
<connect gate="A" pin="IOUTN" pad="29"/>
<connect gate="A" pin="IOUTP" pad="28"/>
<connect gate="A" pin="NC" pad="15"/>
<connect gate="A" pin="NC_2" pad="10"/>
<connect gate="A" pin="NC_3" pad="11"/>
<connect gate="A" pin="NC_4" pad="12"/>
<connect gate="A" pin="NC_5" pad="13"/>
<connect gate="A" pin="NC_6" pad="14"/>
<connect gate="A" pin="QOUTN" pad="22"/>
<connect gate="A" pin="QOUTP" pad="23"/>
<connect gate="A" pin="REFIO" pad="34"/>
<connect gate="A" pin="RESET/_PINMD" pad="35"/>
<connect gate="A" pin="RLIN" pad="30"/>
<connect gate="A" pin="RLIP" pad="27"/>
<connect gate="A" pin="RLQN" pad="21"/>
<connect gate="A" pin="RLQP" pad="24"/>
<connect gate="A" pin="SCLK/CLKMD" pad="36"/>
<connect gate="A" pin="SDIO/_FORMAT" pad="37"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2025 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="AD9714BCPZ"/>
<attribute name="MFR_NAME" value="Analog Devices Inc"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="ADF4356BCPZ" prefix="U">
<gates>
<gate name="A" symbol="ADF4356"/>
</gates>
<devices>
<device name="" package="CP-32-12_ADI">
<connects>
<connect gate="A" pin="AGND" pad="33"/>
<connect gate="A" pin="AGNDRF" pad="13"/>
<connect gate="A" pin="AGNDVCO" pad="21"/>
<connect gate="A" pin="AGNDVDO" pad="18"/>
<connect gate="A" pin="AGND_2" pad="9"/>
<connect gate="A" pin="AVDD" pad="16"/>
<connect gate="A" pin="AVDD_2" pad="5"/>
<connect gate="A" pin="CE" pad="4"/>
<connect gate="A" pin="CLK" pad="1"/>
<connect gate="A" pin="CPGND" pad="8"/>
<connect gate="A" pin="CPOUT" pad="7"/>
<connect gate="A" pin="CREG1" pad="25"/>
<connect gate="A" pin="CREG2" pad="32"/>
<connect gate="A" pin="DATA" pad="2"/>
<connect gate="A" pin="DVDD" pad="27"/>
<connect gate="A" pin="LE" pad="3"/>
<connect gate="A" pin="MUXOUT" pad="30"/>
<connect gate="A" pin="NIC" pad="22"/>
<connect gate="A" pin="PDBRF" pad="26"/>
<connect gate="A" pin="REFINA" pad="29"/>
<connect gate="A" pin="REFINB" pad="28"/>
<connect gate="A" pin="RFOUTA+" pad="11"/>
<connect gate="A" pin="RFOUTA-" pad="12"/>
<connect gate="A" pin="RFOUTB+" pad="14"/>
<connect gate="A" pin="RFOUTB-" pad="15"/>
<connect gate="A" pin="SDGND" pad="31"/>
<connect gate="A" pin="VBIAS" pad="24"/>
<connect gate="A" pin="VP" pad="6"/>
<connect gate="A" pin="VREF" pad="23"/>
<connect gate="A" pin="VREGVCO" pad="19"/>
<connect gate="A" pin="VRF" pad="10"/>
<connect gate="A" pin="VTUNE" pad="20"/>
<connect gate="A" pin="VVCO" pad="17"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2025 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="ADF4356BCPZ"/>
<attribute name="MFR_NAME" value="Analog Devices Inc"/>
<attribute name="TYPE" value="Clock, timing"/>
</technology>
</technologies>
</device>
<device name="CP-32-12_ADI-M" package="CP-32-12_ADI-M">
<connects>
<connect gate="A" pin="AGND" pad="33"/>
<connect gate="A" pin="AGNDRF" pad="13"/>
<connect gate="A" pin="AGNDVCO" pad="21"/>
<connect gate="A" pin="AGNDVDO" pad="18"/>
<connect gate="A" pin="AGND_2" pad="9"/>
<connect gate="A" pin="AVDD" pad="16"/>
<connect gate="A" pin="AVDD_2" pad="5"/>
<connect gate="A" pin="CE" pad="4"/>
<connect gate="A" pin="CLK" pad="1"/>
<connect gate="A" pin="CPGND" pad="8"/>
<connect gate="A" pin="CPOUT" pad="7"/>
<connect gate="A" pin="CREG1" pad="25"/>
<connect gate="A" pin="CREG2" pad="32"/>
<connect gate="A" pin="DATA" pad="2"/>
<connect gate="A" pin="DVDD" pad="27"/>
<connect gate="A" pin="LE" pad="3"/>
<connect gate="A" pin="MUXOUT" pad="30"/>
<connect gate="A" pin="NIC" pad="22"/>
<connect gate="A" pin="PDBRF" pad="26"/>
<connect gate="A" pin="REFINA" pad="29"/>
<connect gate="A" pin="REFINB" pad="28"/>
<connect gate="A" pin="RFOUTA+" pad="11"/>
<connect gate="A" pin="RFOUTA-" pad="12"/>
<connect gate="A" pin="RFOUTB+" pad="14"/>
<connect gate="A" pin="RFOUTB-" pad="15"/>
<connect gate="A" pin="SDGND" pad="31"/>
<connect gate="A" pin="VBIAS" pad="24"/>
<connect gate="A" pin="VP" pad="6"/>
<connect gate="A" pin="VREF" pad="23"/>
<connect gate="A" pin="VREGVCO" pad="19"/>
<connect gate="A" pin="VRF" pad="10"/>
<connect gate="A" pin="VTUNE" pad="20"/>
<connect gate="A" pin="VVCO" pad="17"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2025 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="ADF4356BCPZ"/>
<attribute name="MFR_NAME" value="Analog Devices Inc"/>
<attribute name="TYPE" value="Clock, timing"/>
</technology>
</technologies>
</device>
<device name="CP-32-12_ADI-L" package="CP-32-12_ADI-L">
<connects>
<connect gate="A" pin="AGND" pad="33"/>
<connect gate="A" pin="AGNDRF" pad="13"/>
<connect gate="A" pin="AGNDVCO" pad="21"/>
<connect gate="A" pin="AGNDVDO" pad="18"/>
<connect gate="A" pin="AGND_2" pad="9"/>
<connect gate="A" pin="AVDD" pad="16"/>
<connect gate="A" pin="AVDD_2" pad="5"/>
<connect gate="A" pin="CE" pad="4"/>
<connect gate="A" pin="CLK" pad="1"/>
<connect gate="A" pin="CPGND" pad="8"/>
<connect gate="A" pin="CPOUT" pad="7"/>
<connect gate="A" pin="CREG1" pad="25"/>
<connect gate="A" pin="CREG2" pad="32"/>
<connect gate="A" pin="DATA" pad="2"/>
<connect gate="A" pin="DVDD" pad="27"/>
<connect gate="A" pin="LE" pad="3"/>
<connect gate="A" pin="MUXOUT" pad="30"/>
<connect gate="A" pin="NIC" pad="22"/>
<connect gate="A" pin="PDBRF" pad="26"/>
<connect gate="A" pin="REFINA" pad="29"/>
<connect gate="A" pin="REFINB" pad="28"/>
<connect gate="A" pin="RFOUTA+" pad="11"/>
<connect gate="A" pin="RFOUTA-" pad="12"/>
<connect gate="A" pin="RFOUTB+" pad="14"/>
<connect gate="A" pin="RFOUTB-" pad="15"/>
<connect gate="A" pin="SDGND" pad="31"/>
<connect gate="A" pin="VBIAS" pad="24"/>
<connect gate="A" pin="VP" pad="6"/>
<connect gate="A" pin="VREF" pad="23"/>
<connect gate="A" pin="VREGVCO" pad="19"/>
<connect gate="A" pin="VRF" pad="10"/>
<connect gate="A" pin="VTUNE" pad="20"/>
<connect gate="A" pin="VVCO" pad="17"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2025 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="ADF4356BCPZ"/>
<attribute name="MFR_NAME" value="Analog Devices Inc"/>
<attribute name="TYPE" value="Clock, timing"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="FC68371" prefix="U">
<gates>
<gate name="A" symbol="FC68371"/>
</gates>
<devices>
<device name="" package="FC68371_CLF">
<connects>
<connect gate="A" pin="1" pad="1"/>
<connect gate="A" pin="2" pad="2"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2025 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="FC68371"/>
<attribute name="MFR_NAME" value="Cliff"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="HSWA4-63DR+" prefix="U">
<gates>
<gate name="A" symbol="HSWA4-63DR+"/>
</gates>
<devices>
<device name="" package="DG984-1_MNC">
<connects>
<connect gate="A" pin="CONTROL1" pad="17"/>
<connect gate="A" pin="CONTROL2" pad="18"/>
<connect gate="A" pin="CONTROL3" pad="19"/>
<connect gate="A" pin="GND" pad="25"/>
<connect gate="A" pin="GND_10" pad="12"/>
<connect gate="A" pin="GND_11" pad="13"/>
<connect gate="A" pin="GND_12" pad="15"/>
<connect gate="A" pin="GND_13" pad="20"/>
<connect gate="A" pin="GND_14" pad="21"/>
<connect gate="A" pin="GND_15" pad="23"/>
<connect gate="A" pin="GND_16" pad="24"/>
<connect gate="A" pin="GND_2" pad="1"/>
<connect gate="A" pin="GND_3" pad="2"/>
<connect gate="A" pin="GND_4" pad="3"/>
<connect gate="A" pin="GND_5" pad="4"/>
<connect gate="A" pin="GND_6" pad="6"/>
<connect gate="A" pin="GND_7" pad="7"/>
<connect gate="A" pin="GND_8" pad="9"/>
<connect gate="A" pin="GND_9" pad="10"/>
<connect gate="A" pin="RF1" pad="14"/>
<connect gate="A" pin="RF2" pad="11"/>
<connect gate="A" pin="RF3" pad="8"/>
<connect gate="A" pin="RF4" pad="5"/>
<connect gate="A" pin="RF_COM" pad="22"/>
<connect gate="A" pin="VDD" pad="16"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2025 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="HSWA4-63DR+"/>
<attribute name="MFR_NAME" value="Mini Circuits"/>
</technology>
</technologies>
</device>
<device name="DG984-1_MNC-M" package="DG984-1_MNC-M">
<connects>
<connect gate="A" pin="CONTROL1" pad="17"/>
<connect gate="A" pin="CONTROL2" pad="18"/>
<connect gate="A" pin="CONTROL3" pad="19"/>
<connect gate="A" pin="GND" pad="25"/>
<connect gate="A" pin="GND_10" pad="12"/>
<connect gate="A" pin="GND_11" pad="13"/>
<connect gate="A" pin="GND_12" pad="15"/>
<connect gate="A" pin="GND_13" pad="20"/>
<connect gate="A" pin="GND_14" pad="21"/>
<connect gate="A" pin="GND_15" pad="23"/>
<connect gate="A" pin="GND_16" pad="24"/>
<connect gate="A" pin="GND_2" pad="1"/>
<connect gate="A" pin="GND_3" pad="2"/>
<connect gate="A" pin="GND_4" pad="3"/>
<connect gate="A" pin="GND_5" pad="4"/>
<connect gate="A" pin="GND_6" pad="6"/>
<connect gate="A" pin="GND_7" pad="7"/>
<connect gate="A" pin="GND_8" pad="9"/>
<connect gate="A" pin="GND_9" pad="10"/>
<connect gate="A" pin="RF1" pad="14"/>
<connect gate="A" pin="RF2" pad="11"/>
<connect gate="A" pin="RF3" pad="8"/>
<connect gate="A" pin="RF4" pad="5"/>
<connect gate="A" pin="RF_COM" pad="22"/>
<connect gate="A" pin="VDD" pad="16"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2025 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="HSWA4-63DR+"/>
<attribute name="MFR_NAME" value="Mini Circuits"/>
</technology>
</technologies>
</device>
<device name="DG984-1_MNC-L" package="DG984-1_MNC-L">
<connects>
<connect gate="A" pin="CONTROL1" pad="17"/>
<connect gate="A" pin="CONTROL2" pad="18"/>
<connect gate="A" pin="CONTROL3" pad="19"/>
<connect gate="A" pin="GND" pad="25"/>
<connect gate="A" pin="GND_10" pad="12"/>
<connect gate="A" pin="GND_11" pad="13"/>
<connect gate="A" pin="GND_12" pad="15"/>
<connect gate="A" pin="GND_13" pad="20"/>
<connect gate="A" pin="GND_14" pad="21"/>
<connect gate="A" pin="GND_15" pad="23"/>
<connect gate="A" pin="GND_16" pad="24"/>
<connect gate="A" pin="GND_2" pad="1"/>
<connect gate="A" pin="GND_3" pad="2"/>
<connect gate="A" pin="GND_4" pad="3"/>
<connect gate="A" pin="GND_5" pad="4"/>
<connect gate="A" pin="GND_6" pad="6"/>
<connect gate="A" pin="GND_7" pad="7"/>
<connect gate="A" pin="GND_8" pad="9"/>
<connect gate="A" pin="GND_9" pad="10"/>
<connect gate="A" pin="RF1" pad="14"/>
<connect gate="A" pin="RF2" pad="11"/>
<connect gate="A" pin="RF3" pad="8"/>
<connect gate="A" pin="RF4" pad="5"/>
<connect gate="A" pin="RF_COM" pad="22"/>
<connect gate="A" pin="VDD" pad="16"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2025 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="HSWA4-63DR+"/>
<attribute name="MFR_NAME" value="Mini Circuits"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="LTC5588IPF-1TRPBF" prefix="U">
<gates>
<gate name="A" symbol="LTC5588IPF-1TRPBF"/>
</gates>
<devices>
<device name="" package="UTQFN-24_PF_LIT">
<connects>
<connect gate="A" pin="BBMI" pad="22"/>
<connect gate="A" pin="BBMQ" pad="9"/>
<connect gate="A" pin="BBPI" pad="21"/>
<connect gate="A" pin="BBPQ" pad="10"/>
<connect gate="A" pin="EN" pad="1"/>
<connect gate="A" pin="GND" pad="25"/>
<connect gate="A" pin="GNDRF" pad="26"/>
<connect gate="A" pin="GNDRF_2" pad="12"/>
<connect gate="A" pin="GNDRF_3" pad="14"/>
<connect gate="A" pin="GNDRF_4" pad="17"/>
<connect gate="A" pin="GNDRF_5" pad="19"/>
<connect gate="A" pin="GND_2" pad="2"/>
<connect gate="A" pin="GND_3" pad="5"/>
<connect gate="A" pin="GND_4" pad="8"/>
<connect gate="A" pin="GND_5" pad="11"/>
<connect gate="A" pin="GND_6" pad="20"/>
<connect gate="A" pin="GND_7" pad="23"/>
<connect gate="A" pin="LINOPT" pad="7"/>
<connect gate="A" pin="LOM" pad="4"/>
<connect gate="A" pin="LOP" pad="3"/>
<connect gate="A" pin="NC" pad="15"/>
<connect gate="A" pin="NC_2" pad="6"/>
<connect gate="A" pin="NC_3" pad="13"/>
<connect gate="A" pin="RF" pad="16"/>
<connect gate="A" pin="VCC1" pad="24"/>
<connect gate="A" pin="VCC2" pad="18"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2025 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="LTC5588IPF-1#TRPBF"/>
<attribute name="MFR_NAME" value="Analog Devices Inc"/>
</technology>
</technologies>
</device>
<device name="UTQFN-24_PF_LIT-M" package="UTQFN-24_PF_LIT-M">
<connects>
<connect gate="A" pin="BBMI" pad="22"/>
<connect gate="A" pin="BBMQ" pad="9"/>
<connect gate="A" pin="BBPI" pad="21"/>
<connect gate="A" pin="BBPQ" pad="10"/>
<connect gate="A" pin="EN" pad="1"/>
<connect gate="A" pin="GND" pad="25"/>
<connect gate="A" pin="GNDRF" pad="26"/>
<connect gate="A" pin="GNDRF_2" pad="12"/>
<connect gate="A" pin="GNDRF_3" pad="14"/>
<connect gate="A" pin="GNDRF_4" pad="17"/>
<connect gate="A" pin="GNDRF_5" pad="19"/>
<connect gate="A" pin="GND_2" pad="2"/>
<connect gate="A" pin="GND_3" pad="5"/>
<connect gate="A" pin="GND_4" pad="8"/>
<connect gate="A" pin="GND_5" pad="11"/>
<connect gate="A" pin="GND_6" pad="20"/>
<connect gate="A" pin="GND_7" pad="23"/>
<connect gate="A" pin="LINOPT" pad="7"/>
<connect gate="A" pin="LOM" pad="4"/>
<connect gate="A" pin="LOP" pad="3"/>
<connect gate="A" pin="NC" pad="15"/>
<connect gate="A" pin="NC_2" pad="6"/>
<connect gate="A" pin="NC_3" pad="13"/>
<connect gate="A" pin="RF" pad="16"/>
<connect gate="A" pin="VCC1" pad="24"/>
<connect gate="A" pin="VCC2" pad="18"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2025 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="LTC5588IPF-1#TRPBF"/>
<attribute name="MFR_NAME" value="Analog Devices Inc"/>
</technology>
</technologies>
</device>
<device name="UTQFN-24_PF_LIT-L" package="UTQFN-24_PF_LIT-L">
<connects>
<connect gate="A" pin="BBMI" pad="22"/>
<connect gate="A" pin="BBMQ" pad="9"/>
<connect gate="A" pin="BBPI" pad="21"/>
<connect gate="A" pin="BBPQ" pad="10"/>
<connect gate="A" pin="EN" pad="1"/>
<connect gate="A" pin="GND" pad="25"/>
<connect gate="A" pin="GNDRF" pad="26"/>
<connect gate="A" pin="GNDRF_2" pad="12"/>
<connect gate="A" pin="GNDRF_3" pad="14"/>
<connect gate="A" pin="GNDRF_4" pad="17"/>
<connect gate="A" pin="GNDRF_5" pad="19"/>
<connect gate="A" pin="GND_2" pad="2"/>
<connect gate="A" pin="GND_3" pad="5"/>
<connect gate="A" pin="GND_4" pad="8"/>
<connect gate="A" pin="GND_5" pad="11"/>
<connect gate="A" pin="GND_6" pad="20"/>
<connect gate="A" pin="GND_7" pad="23"/>
<connect gate="A" pin="LINOPT" pad="7"/>
<connect gate="A" pin="LOM" pad="4"/>
<connect gate="A" pin="LOP" pad="3"/>
<connect gate="A" pin="NC" pad="15"/>
<connect gate="A" pin="NC_2" pad="6"/>
<connect gate="A" pin="NC_3" pad="13"/>
<connect gate="A" pin="RF" pad="16"/>
<connect gate="A" pin="VCC1" pad="24"/>
<connect gate="A" pin="VCC2" pad="18"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2025 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="LTC5588IPF-1#TRPBF"/>
<attribute name="MFR_NAME" value="Analog Devices Inc"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="TVP5150AM1IPBSR" prefix="U">
<gates>
<gate name="A" symbol="TVP5150AM1_PBS_32"/>
</gates>
<devices>
<device name="" package="PBS32">
<connects>
<connect gate="A" pin="!RESETB" pad="8"/>
<connect gate="A" pin="AIP1A" pad="1"/>
<connect gate="A" pin="AIP1B" pad="2"/>
<connect gate="A" pin="AVID" pad="26"/>
<connect gate="A" pin="CH1_AGND" pad="31"/>
<connect gate="A" pin="CH1_AVDD" pad="32"/>
<connect gate="A" pin="DGND" pad="19"/>
<connect gate="A" pin="DVDD" pad="20"/>
<connect gate="A" pin="FID/GLCO" pad="23"/>
<connect gate="A" pin="HSYNC" pad="25"/>
<connect gate="A" pin="INTREQ/GPCL/VBLK" pad="27"/>
<connect gate="A" pin="IO_DVDD" pad="10"/>
<connect gate="A" pin="NSUB" pad="7"/>
<connect gate="A" pin="PDN" pad="28"/>
<connect gate="A" pin="PLL_AGND" pad="3"/>
<connect gate="A" pin="PLL_AVDD" pad="4"/>
<connect gate="A" pin="REFM" pad="30"/>
<connect gate="A" pin="REFP" pad="29"/>
<connect gate="A" pin="SCL" pad="21"/>
<connect gate="A" pin="SCLK" pad="9"/>
<connect gate="A" pin="SDA" pad="22"/>
<connect gate="A" pin="VSYNC/PALI" pad="24"/>
<connect gate="A" pin="XTAL1/OSC" pad="5"/>
<connect gate="A" pin="XTAL2" pad="6"/>
<connect gate="A" pin="YOUT0" pad="18"/>
<connect gate="A" pin="YOUT1" pad="17"/>
<connect gate="A" pin="YOUT2" pad="16"/>
<connect gate="A" pin="YOUT3" pad="15"/>
<connect gate="A" pin="YOUT4" pad="14"/>
<connect gate="A" pin="YOUT5" pad="13"/>
<connect gate="A" pin="YOUT6" pad="12"/>
<connect gate="A" pin="YOUT7/I2CSEL" pad="11"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2025 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="TVP5150AM1IPBSR"/>
<attribute name="MFR_NAME" value="Texas Instruments"/>
</technology>
</technologies>
</device>
<device name="PBS32-M" package="PBS32-M">
<connects>
<connect gate="A" pin="!RESETB" pad="8"/>
<connect gate="A" pin="AIP1A" pad="1"/>
<connect gate="A" pin="AIP1B" pad="2"/>
<connect gate="A" pin="AVID" pad="26"/>
<connect gate="A" pin="CH1_AGND" pad="31"/>
<connect gate="A" pin="CH1_AVDD" pad="32"/>
<connect gate="A" pin="DGND" pad="19"/>
<connect gate="A" pin="DVDD" pad="20"/>
<connect gate="A" pin="FID/GLCO" pad="23"/>
<connect gate="A" pin="HSYNC" pad="25"/>
<connect gate="A" pin="INTREQ/GPCL/VBLK" pad="27"/>
<connect gate="A" pin="IO_DVDD" pad="10"/>
<connect gate="A" pin="NSUB" pad="7"/>
<connect gate="A" pin="PDN" pad="28"/>
<connect gate="A" pin="PLL_AGND" pad="3"/>
<connect gate="A" pin="PLL_AVDD" pad="4"/>
<connect gate="A" pin="REFM" pad="30"/>
<connect gate="A" pin="REFP" pad="29"/>
<connect gate="A" pin="SCL" pad="21"/>
<connect gate="A" pin="SCLK" pad="9"/>
<connect gate="A" pin="SDA" pad="22"/>
<connect gate="A" pin="VSYNC/PALI" pad="24"/>
<connect gate="A" pin="XTAL1/OSC" pad="5"/>
<connect gate="A" pin="XTAL2" pad="6"/>
<connect gate="A" pin="YOUT0" pad="18"/>
<connect gate="A" pin="YOUT1" pad="17"/>
<connect gate="A" pin="YOUT2" pad="16"/>
<connect gate="A" pin="YOUT3" pad="15"/>
<connect gate="A" pin="YOUT4" pad="14"/>
<connect gate="A" pin="YOUT5" pad="13"/>
<connect gate="A" pin="YOUT6" pad="12"/>
<connect gate="A" pin="YOUT7/I2CSEL" pad="11"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2025 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="TVP5150AM1IPBSR"/>
<attribute name="MFR_NAME" value="Texas Instruments"/>
</technology>
</technologies>
</device>
<device name="PBS32-L" package="PBS32-L">
<connects>
<connect gate="A" pin="!RESETB" pad="8"/>
<connect gate="A" pin="AIP1A" pad="1"/>
<connect gate="A" pin="AIP1B" pad="2"/>
<connect gate="A" pin="AVID" pad="26"/>
<connect gate="A" pin="CH1_AGND" pad="31"/>
<connect gate="A" pin="CH1_AVDD" pad="32"/>
<connect gate="A" pin="DGND" pad="19"/>
<connect gate="A" pin="DVDD" pad="20"/>
<connect gate="A" pin="FID/GLCO" pad="23"/>
<connect gate="A" pin="HSYNC" pad="25"/>
<connect gate="A" pin="INTREQ/GPCL/VBLK" pad="27"/>
<connect gate="A" pin="IO_DVDD" pad="10"/>
<connect gate="A" pin="NSUB" pad="7"/>
<connect gate="A" pin="PDN" pad="28"/>
<connect gate="A" pin="PLL_AGND" pad="3"/>
<connect gate="A" pin="PLL_AVDD" pad="4"/>
<connect gate="A" pin="REFM" pad="30"/>
<connect gate="A" pin="REFP" pad="29"/>
<connect gate="A" pin="SCL" pad="21"/>
<connect gate="A" pin="SCLK" pad="9"/>
<connect gate="A" pin="SDA" pad="22"/>
<connect gate="A" pin="VSYNC/PALI" pad="24"/>
<connect gate="A" pin="XTAL1/OSC" pad="5"/>
<connect gate="A" pin="XTAL2" pad="6"/>
<connect gate="A" pin="YOUT0" pad="18"/>
<connect gate="A" pin="YOUT1" pad="17"/>
<connect gate="A" pin="YOUT2" pad="16"/>
<connect gate="A" pin="YOUT3" pad="15"/>
<connect gate="A" pin="YOUT4" pad="14"/>
<connect gate="A" pin="YOUT5" pad="13"/>
<connect gate="A" pin="YOUT6" pad="12"/>
<connect gate="A" pin="YOUT7/I2CSEL" pad="11"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2025 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="TVP5150AM1IPBSR"/>
<attribute name="MFR_NAME" value="Texas Instruments"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="USB2513BI-AEZG-TR" prefix="U">
<gates>
<gate name="A" symbol="USB2513BI-AEZG"/>
</gates>
<devices>
<device name="" package="QFN36_6X6MC_MCH">
<connects>
<connect gate="A" pin="CRFILT" pad="14"/>
<connect gate="A" pin="EPAD" pad="37"/>
<connect gate="A" pin="HS_IND/CFG_SEL1" pad="25"/>
<connect gate="A" pin="NC" pad="21"/>
<connect gate="A" pin="NC_2" pad="8"/>
<connect gate="A" pin="NC_3" pad="9"/>
<connect gate="A" pin="NC_4" pad="20"/>
<connect gate="A" pin="OCS_N1" pad="13"/>
<connect gate="A" pin="OCS_N2" pad="17"/>
<connect gate="A" pin="OCS_N3" pad="19"/>
<connect gate="A" pin="PLLFILT" pad="34"/>
<connect gate="A" pin="PRTPWR1/BC_EN1" pad="12"/>
<connect gate="A" pin="PRTPWR2/BC_EN2" pad="16"/>
<connect gate="A" pin="PRTPWR3/BC_EN3" pad="18"/>
<connect gate="A" pin="RBIAS" pad="35"/>
<connect gate="A" pin="RESET_N" pad="26"/>
<connect gate="A" pin="SCL/SMBCLK/CFG_SEL0" pad="24"/>
<connect gate="A" pin="SDA/SMBDATA/NON_REM1" pad="22"/>
<connect gate="A" pin="SUSP_IND/LOCAL_PWR/NON_REM0" pad="28"/>
<connect gate="A" pin="TEST" pad="11"/>
<connect gate="A" pin="USBDM_DN1/PRT_DIS_M1" pad="1"/>
<connect gate="A" pin="USBDM_DN2/PRT_DIS_M2" pad="3"/>
<connect gate="A" pin="USBDM_DN3/PRT_DIS_M3" pad="6"/>
<connect gate="A" pin="USBDM_UP" pad="30"/>
<connect gate="A" pin="USBDP_DN1/PRT_DIS_P1" pad="2"/>
<connect gate="A" pin="USBDP_DN2/PRT_DIS_P2" pad="4"/>
<connect gate="A" pin="USBDP_DN3/PRT_DIS_P3" pad="7"/>
<connect gate="A" pin="USBDP_UP" pad="31"/>
<connect gate="A" pin="VBUS_DET" pad="27"/>
<connect gate="A" pin="VDD33" pad="23"/>
<connect gate="A" pin="VDD33_2" pad="15"/>
<connect gate="A" pin="VDDA33" pad="36"/>
<connect gate="A" pin="VDDA33_2" pad="5"/>
<connect gate="A" pin="VDDA33_3" pad="10"/>
<connect gate="A" pin="VDDA33_4" pad="29"/>
<connect gate="A" pin="XTALIN/CLKIN" pad="33"/>
<connect gate="A" pin="XTALOUT" pad="32"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2025 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="USB2513BI-AEZG-TR"/>
<attribute name="MFR_NAME" value="Microchip"/>
</technology>
</technologies>
</device>
<device name="QFN36_6X6MC_MCH-M" package="QFN36_6X6MC_MCH-M">
<connects>
<connect gate="A" pin="CRFILT" pad="14"/>
<connect gate="A" pin="EPAD" pad="37"/>
<connect gate="A" pin="HS_IND/CFG_SEL1" pad="25"/>
<connect gate="A" pin="NC" pad="21"/>
<connect gate="A" pin="NC_2" pad="8"/>
<connect gate="A" pin="NC_3" pad="9"/>
<connect gate="A" pin="NC_4" pad="20"/>
<connect gate="A" pin="OCS_N1" pad="13"/>
<connect gate="A" pin="OCS_N2" pad="17"/>
<connect gate="A" pin="OCS_N3" pad="19"/>
<connect gate="A" pin="PLLFILT" pad="34"/>
<connect gate="A" pin="PRTPWR1/BC_EN1" pad="12"/>
<connect gate="A" pin="PRTPWR2/BC_EN2" pad="16"/>
<connect gate="A" pin="PRTPWR3/BC_EN3" pad="18"/>
<connect gate="A" pin="RBIAS" pad="35"/>
<connect gate="A" pin="RESET_N" pad="26"/>
<connect gate="A" pin="SCL/SMBCLK/CFG_SEL0" pad="24"/>
<connect gate="A" pin="SDA/SMBDATA/NON_REM1" pad="22"/>
<connect gate="A" pin="SUSP_IND/LOCAL_PWR/NON_REM0" pad="28"/>
<connect gate="A" pin="TEST" pad="11"/>
<connect gate="A" pin="USBDM_DN1/PRT_DIS_M1" pad="1"/>
<connect gate="A" pin="USBDM_DN2/PRT_DIS_M2" pad="3"/>
<connect gate="A" pin="USBDM_DN3/PRT_DIS_M3" pad="6"/>
<connect gate="A" pin="USBDM_UP" pad="30"/>
<connect gate="A" pin="USBDP_DN1/PRT_DIS_P1" pad="2"/>
<connect gate="A" pin="USBDP_DN2/PRT_DIS_P2" pad="4"/>
<connect gate="A" pin="USBDP_DN3/PRT_DIS_P3" pad="7"/>
<connect gate="A" pin="USBDP_UP" pad="31"/>
<connect gate="A" pin="VBUS_DET" pad="27"/>
<connect gate="A" pin="VDD33" pad="23"/>
<connect gate="A" pin="VDD33_2" pad="15"/>
<connect gate="A" pin="VDDA33" pad="36"/>
<connect gate="A" pin="VDDA33_2" pad="5"/>
<connect gate="A" pin="VDDA33_3" pad="10"/>
<connect gate="A" pin="VDDA33_4" pad="29"/>
<connect gate="A" pin="XTALIN/CLKIN" pad="33"/>
<connect gate="A" pin="XTALOUT" pad="32"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2025 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="USB2513BI-AEZG-TR"/>
<attribute name="MFR_NAME" value="Microchip"/>
</technology>
</technologies>
</device>
<device name="QFN36_6X6MC_MCH-L" package="QFN36_6X6MC_MCH-L">
<connects>
<connect gate="A" pin="CRFILT" pad="14"/>
<connect gate="A" pin="EPAD" pad="37"/>
<connect gate="A" pin="HS_IND/CFG_SEL1" pad="25"/>
<connect gate="A" pin="NC" pad="21"/>
<connect gate="A" pin="NC_2" pad="8"/>
<connect gate="A" pin="NC_3" pad="9"/>
<connect gate="A" pin="NC_4" pad="20"/>
<connect gate="A" pin="OCS_N1" pad="13"/>
<connect gate="A" pin="OCS_N2" pad="17"/>
<connect gate="A" pin="OCS_N3" pad="19"/>
<connect gate="A" pin="PLLFILT" pad="34"/>
<connect gate="A" pin="PRTPWR1/BC_EN1" pad="12"/>
<connect gate="A" pin="PRTPWR2/BC_EN2" pad="16"/>
<connect gate="A" pin="PRTPWR3/BC_EN3" pad="18"/>
<connect gate="A" pin="RBIAS" pad="35"/>
<connect gate="A" pin="RESET_N" pad="26"/>
<connect gate="A" pin="SCL/SMBCLK/CFG_SEL0" pad="24"/>
<connect gate="A" pin="SDA/SMBDATA/NON_REM1" pad="22"/>
<connect gate="A" pin="SUSP_IND/LOCAL_PWR/NON_REM0" pad="28"/>
<connect gate="A" pin="TEST" pad="11"/>
<connect gate="A" pin="USBDM_DN1/PRT_DIS_M1" pad="1"/>
<connect gate="A" pin="USBDM_DN2/PRT_DIS_M2" pad="3"/>
<connect gate="A" pin="USBDM_DN3/PRT_DIS_M3" pad="6"/>
<connect gate="A" pin="USBDM_UP" pad="30"/>
<connect gate="A" pin="USBDP_DN1/PRT_DIS_P1" pad="2"/>
<connect gate="A" pin="USBDP_DN2/PRT_DIS_P2" pad="4"/>
<connect gate="A" pin="USBDP_DN3/PRT_DIS_P3" pad="7"/>
<connect gate="A" pin="USBDP_UP" pad="31"/>
<connect gate="A" pin="VBUS_DET" pad="27"/>
<connect gate="A" pin="VDD33" pad="23"/>
<connect gate="A" pin="VDD33_2" pad="15"/>
<connect gate="A" pin="VDDA33" pad="36"/>
<connect gate="A" pin="VDDA33_2" pad="5"/>
<connect gate="A" pin="VDDA33_3" pad="10"/>
<connect gate="A" pin="VDDA33_4" pad="29"/>
<connect gate="A" pin="XTALIN/CLKIN" pad="33"/>
<connect gate="A" pin="XTALOUT" pad="32"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2025 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="USB2513BI-AEZG-TR"/>
<attribute name="MFR_NAME" value="Microchip"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="XC7A100T-2FTG256I" prefix="U">
<gates>
<gate name="A" symbol="XC7A100T-2FTG256I_A"/>
<gate name="B" symbol="XC7A100T-2FTG256I_B"/>
<gate name="C" symbol="XC7A100T-2FTG256I_C"/>
</gates>
<devices>
<device name="" package="FTG256_AMD">
<connects>
<connect gate="A" pin="CCLK_0" pad="E8"/>
<connect gate="A" pin="CFGBVS_0" pad="E7"/>
<connect gate="A" pin="GND" pad="F6"/>
<connect gate="A" pin="GND_2" pad="A1"/>
<connect gate="A" pin="GND_3" pad="A11"/>
<connect gate="A" pin="GND_4" pad="B8"/>
<connect gate="A" pin="GND_5" pad="C5"/>
<connect gate="A" pin="GND_6" pad="C15"/>
<connect gate="A" pin="GND_7" pad="D2"/>
<connect gate="A" pin="GND_8" pad="D12"/>
<connect gate="A" pin="GND_9" pad="E9"/>
<connect gate="A" pin="IO_0_15" pad="D10"/>
<connect gate="A" pin="IO_0_35" pad="E6"/>
<connect gate="A" pin="IO_L10N_T1_AD11N_15" pad="B16"/>
<connect gate="A" pin="IO_L10N_T1_AD15N_35" pad="D1"/>
<connect gate="A" pin="IO_L10P_T1_AD11P_15" pad="C16"/>
<connect gate="A" pin="IO_L10P_T1_AD15P_35" pad="E2"/>
<connect gate="A" pin="IO_L11N_T1_SRCC_15" pad="C12"/>
<connect gate="A" pin="IO_L11N_T1_SRCC_35" pad="D3"/>
<connect gate="A" pin="IO_L11P_T1_SRCC_15" pad="C11"/>
<connect gate="A" pin="IO_L11P_T1_SRCC_35" pad="E3"/>
<connect gate="A" pin="IO_L12N_T1_MRCC_15" pad="C13"/>
<connect gate="A" pin="IO_L12N_T1_MRCC_35" pad="C4"/>
<connect gate="A" pin="IO_L12P_T1_MRCC_15" pad="D13"/>
<connect gate="A" pin="IO_L12P_T1_MRCC_35" pad="D4"/>
<connect gate="A" pin="IO_L13N_T2_MRCC_15" pad="E13"/>
<connect gate="A" pin="IO_L13N_T2_MRCC_35" pad="E5"/>
<connect gate="A" pin="IO_L13P_T2_MRCC_15" pad="E12"/>
<connect gate="A" pin="IO_L13P_T2_MRCC_35" pad="F5"/>
<connect gate="A" pin="IO_L14N_T2_SRCC_15" pad="D11"/>
<connect gate="A" pin="IO_L14N_T2_SRCC_35" pad="F3"/>
<connect gate="A" pin="IO_L14P_T2_SRCC_15" pad="E11"/>
<connect gate="A" pin="IO_L14P_T2_SRCC_35" pad="F4"/>
<connect gate="A" pin="IO_L15N_T2_DQS_35" pad="E1"/>
<connect gate="A" pin="IO_L15N_T2_DQS_ADV_B_15" pad="D15"/>
<connect gate="A" pin="IO_L15P_T2_DQS_15" pad="D14"/>
<connect gate="A" pin="IO_L15P_T2_DQS_35" pad="F2"/>
<connect gate="A" pin="IO_L17N_T2_A25_15" pad="D16"/>
<connect gate="A" pin="IO_L17P_T2_A26_15" pad="E16"/>
<connect gate="A" pin="IO_L18N_T2_A23_15" pad="E15"/>
<connect gate="A" pin="IO_L1N_T0_AD0N_15" pad="C9"/>
<connect gate="A" pin="IO_L1N_T0_AD4N_35" pad="A7"/>
<connect gate="A" pin="IO_L1P_T0_AD0P_15" pad="C8"/>
<connect gate="A" pin="IO_L1P_T0_AD4P_35" pad="B7"/>
<connect gate="A" pin="IO_L2N_T0_AD12N_35" pad="B5"/>
<connect gate="A" pin="IO_L2N_T0_AD8N_15" pad="A9"/>
<connect gate="A" pin="IO_L2P_T0_AD12P_35" pad="B6"/>
<connect gate="A" pin="IO_L2P_T0_AD8P_15" pad="A8"/>
<connect gate="A" pin="IO_L3N_T0_DQS_AD1N_15" pad="A10"/>
<connect gate="A" pin="IO_L3N_T0_DQS_AD5N_35" pad="A4"/>
<connect gate="A" pin="IO_L3P_T0_DQS_AD1P_15" pad="B9"/>
<connect gate="A" pin="IO_L3P_T0_DQS_AD5P_35" pad="A5"/>
<connect gate="A" pin="IO_L4N_T0_15" pad="B11"/>
<connect gate="A" pin="IO_L4N_T0_35" pad="A3"/>
<connect gate="A" pin="IO_L4P_T0_15" pad="B10"/>
<connect gate="A" pin="IO_L4P_T0_35" pad="B4"/>
<connect gate="A" pin="IO_L5N_T0_AD13N_35" pad="C6"/>
<connect gate="A" pin="IO_L5N_T0_AD9N_15" pad="A12"/>
<connect gate="A" pin="IO_L5P_T0_AD13P_35" pad="C7"/>
<connect gate="A" pin="IO_L5P_T0_AD9P_15" pad="B12"/>
<connect gate="A" pin="IO_L6N_T0_VREF_15" pad="D9"/>
<connect gate="A" pin="IO_L6N_T0_VREF_35" pad="D5"/>
<connect gate="A" pin="IO_L6P_T0_15" pad="D8"/>
<connect gate="A" pin="IO_L6P_T0_35" pad="D6"/>
<connect gate="A" pin="IO_L7N_T1_AD2N_15" pad="A14"/>
<connect gate="A" pin="IO_L7N_T1_AD6N_35" pad="C2"/>
<connect gate="A" pin="IO_L7P_T1_AD2P_15" pad="A13"/>
<connect gate="A" pin="IO_L7P_T1_AD6P_35" pad="C3"/>
<connect gate="A" pin="IO_L8N_T1_AD10N_15" pad="B14"/>
<connect gate="A" pin="IO_L8N_T1_AD14N_35" pad="A2"/>
<connect gate="A" pin="IO_L8P_T1_AD10P_15" pad="C14"/>
<connect gate="A" pin="IO_L8P_T1_AD14P_35" pad="B2"/>
<connect gate="A" pin="IO_L9N_T1_DQS_AD3N_15" pad="A15"/>
<connect gate="A" pin="IO_L9N_T1_DQS_AD7N_35" pad="B1"/>
<connect gate="A" pin="IO_L9P_T1_DQS_AD3P_15" pad="B15"/>
<connect gate="A" pin="IO_L9P_T1_DQS_AD7P_35" pad="C1"/>
<connect gate="A" pin="VCCBRAM" pad="E10"/>
<connect gate="A" pin="VCCO_15" pad="E14"/>
<connect gate="A" pin="VCCO_15_2" pad="A16"/>
<connect gate="A" pin="VCCO_15_3" pad="B13"/>
<connect gate="A" pin="VCCO_15_4" pad="C10"/>
<connect gate="A" pin="VCCO_35" pad="F1"/>
<connect gate="A" pin="VCCO_35_2" pad="A6"/>
<connect gate="A" pin="VCCO_35_3" pad="B3"/>
<connect gate="A" pin="VCCO_35_4" pad="D7"/>
<connect gate="A" pin="VCCO_35_5" pad="E4"/>
<connect gate="B" pin="DONE_0" pad="H10"/>
<connect gate="B" pin="DXN_0" pad="K7"/>
<connect gate="B" pin="DXP_0" pad="K8"/>
<connect gate="B" pin="GND" pad="L11"/>
<connect gate="B" pin="GNDADC_0" pad="G7"/>
<connect gate="B" pin="GND_10" pad="K4"/>
<connect gate="B" pin="GND_11" pad="K6"/>
<connect gate="B" pin="GND_12" pad="K14"/>
<connect gate="B" pin="GND_13" pad="L1"/>
<connect gate="B" pin="GND_2" pad="F10"/>
<connect gate="B" pin="GND_3" pad="F16"/>
<connect gate="B" pin="GND_4" pad="G3"/>
<connect gate="B" pin="GND_5" pad="G9"/>
<connect gate="B" pin="GND_6" pad="G13"/>
<connect gate="B" pin="GND_7" pad="H6"/>
<connect gate="B" pin="GND_8" pad="J9"/>
<connect gate="B" pin="GND_9" pad="J11"/>
<connect gate="B" pin="INIT_B_0" pad="K10"/>
<connect gate="B" pin="IO_0_14" pad="K12"/>
<connect gate="B" pin="IO_0_34" pad="L5"/>
<connect gate="B" pin="IO_25_15" pad="G11"/>
<connect gate="B" pin="IO_25_35" pad="K5"/>
<connect gate="B" pin="IO_L16N_T2_35" pad="G4"/>
<connect gate="B" pin="IO_L16N_T2_A27_15" pad="F13"/>
<connect gate="B" pin="IO_L16P_T2_35" pad="G5"/>
<connect gate="B" pin="IO_L16P_T2_A28_15" pad="F12"/>
<connect gate="B" pin="IO_L17N_T2_35" pad="G1"/>
<connect gate="B" pin="IO_L17P_T2_35" pad="G2"/>
<connect gate="B" pin="IO_L18N_T2_35" pad="H4"/>
<connect gate="B" pin="IO_L18P_T2_35" pad="H5"/>
<connect gate="B" pin="IO_L18P_T2_A24_15" pad="F15"/>
<connect gate="B" pin="IO_L19N_T3_A21_VREF_15" pad="G12"/>
<connect gate="B" pin="IO_L19N_T3_VREF_35" pad="J4"/>
<connect gate="B" pin="IO_L19P_T3_35" pad="J5"/>
<connect gate="B" pin="IO_L19P_T3_A22_15" pad="H11"/>
<connect gate="B" pin="IO_L1N_T0_D01_DIN_14" pad="J14"/>
<connect gate="B" pin="IO_L1P_T0_34" pad="L4"/>
<connect gate="B" pin="IO_L1P_T0_D00_MOSI_14" pad="J13"/>
<connect gate="B" pin="IO_L20N_T3_35" pad="H1"/>
<connect gate="B" pin="IO_L20N_T3_A19_15" pad="H13"/>
<connect gate="B" pin="IO_L20P_T3_35" pad="H2"/>
<connect gate="B" pin="IO_L20P_T3_A20_15" pad="H12"/>
<connect gate="B" pin="IO_L21N_T3_DQS_35" pad="H3"/>
<connect gate="B" pin="IO_L21N_T3_DQS_A18_15" pad="F14"/>
<connect gate="B" pin="IO_L21P_T3_DQS_15" pad="G14"/>
<connect gate="B" pin="IO_L21P_T3_DQS_35" pad="J3"/>
<connect gate="B" pin="IO_L22N_T3_35" pad="J1"/>
<connect gate="B" pin="IO_L22N_T3_A16_15" pad="G16"/>
<connect gate="B" pin="IO_L22P_T3_35" pad="K1"/>
<connect gate="B" pin="IO_L22P_T3_A17_15" pad="H16"/>
<connect gate="B" pin="IO_L23N_T3_35" pad="L2"/>
<connect gate="B" pin="IO_L23N_T3_FWE_B_15" pad="J16"/>
<connect gate="B" pin="IO_L23P_T3_35" pad="L3"/>
<connect gate="B" pin="IO_L23P_T3_FOE_B_15" pad="J15"/>
<connect gate="B" pin="IO_L24N_T3_35" pad="K2"/>
<connect gate="B" pin="IO_L24N_T3_RS0_15" pad="G15"/>
<connect gate="B" pin="IO_L24P_T3_35" pad="K3"/>
<connect gate="B" pin="IO_L24P_T3_RS1_15" pad="H14"/>
<connect gate="B" pin="IO_L2N_T0_D03_14" pad="K16"/>
<connect gate="B" pin="IO_L2P_T0_D02_14" pad="K15"/>
<connect gate="B" pin="IO_L5P_T0_D06_14" pad="K13"/>
<connect gate="B" pin="IO_L6P_T0_FCS_B_14" pad="L12"/>
<connect gate="B" pin="PROGRAM_B_0" pad="L9"/>
<connect gate="B" pin="TCK_0" pad="L7"/>
<connect gate="B" pin="VCCADC_0" pad="G8"/>
<connect gate="B" pin="VCCAUX" pad="L10"/>
<connect gate="B" pin="VCCAUX_2" pad="G10"/>
<connect gate="B" pin="VCCAUX_3" pad="J10"/>
<connect gate="B" pin="VCCAUX_4" pad="K11"/>
<connect gate="B" pin="VCCBATT_0" pad="F8"/>
<connect gate="B" pin="VCCBRAM" pad="F11"/>
<connect gate="B" pin="VCCINT" pad="L8"/>
<connect gate="B" pin="VCCINT_2" pad="F7"/>
<connect gate="B" pin="VCCINT_3" pad="F9"/>
<connect gate="B" pin="VCCINT_4" pad="G6"/>
<connect gate="B" pin="VCCINT_5" pad="H9"/>
<connect gate="B" pin="VCCINT_6" pad="J6"/>
<connect gate="B" pin="VCCINT_7" pad="K9"/>
<connect gate="B" pin="VCCO_0" pad="L6"/>
<connect gate="B" pin="VCCO_15" pad="J12"/>
<connect gate="B" pin="VCCO_15_2" pad="H15"/>
<connect gate="B" pin="VCCO_35" pad="J2"/>
<connect gate="B" pin="VN_0" pad="J7"/>
<connect gate="B" pin="VP_0" pad="H8"/>
<connect gate="B" pin="VREFN_0" pad="H7"/>
<connect gate="B" pin="VREFP_0" pad="J8"/>
<connect gate="C" pin="GND" pad="T16"/>
<connect gate="C" pin="GND_2" pad="M8"/>
<connect gate="C" pin="GND_3" pad="N5"/>
<connect gate="C" pin="GND_4" pad="N15"/>
<connect gate="C" pin="GND_5" pad="P2"/>
<connect gate="C" pin="GND_6" pad="P12"/>
<connect gate="C" pin="GND_7" pad="R9"/>
<connect gate="C" pin="GND_8" pad="T6"/>
<connect gate="C" pin="IO_25_14" pad="P6"/>
<connect gate="C" pin="IO_L10N_T1_D15_14" pad="T15"/>
<connect gate="C" pin="IO_L10P_T1_34" pad="P5"/>
<connect gate="C" pin="IO_L10P_T1_D14_14" pad="T14"/>
<connect gate="C" pin="IO_L11N_T1_SRCC_14" pad="P13"/>
<connect gate="C" pin="IO_L11P_T1_SRCC_14" pad="N13"/>
<connect gate="C" pin="IO_L12N_T1_MRCC_14" pad="P14"/>
<connect gate="C" pin="IO_L12P_T1_MRCC_14" pad="N14"/>
<connect gate="C" pin="IO_L13N_T2_MRCC_14" pad="N12"/>
<connect gate="C" pin="IO_L13P_T2_MRCC_14" pad="N11"/>
<connect gate="C" pin="IO_L14N_T2_SRCC_14" pad="P11"/>
<connect gate="C" pin="IO_L14P_T2_SRCC_14" pad="P10"/>
<connect gate="C" pin="IO_L15N_T2_DQS_DOUT_CSO_B_14" pad="T12"/>
<connect gate="C" pin="IO_L15P_T2_DQS_RDWR_B_14" pad="R12"/>
<connect gate="C" pin="IO_L16N_T2_A15_D31_14" pad="T13"/>
<connect gate="C" pin="IO_L16P_T2_CSI_B_14" pad="R13"/>
<connect gate="C" pin="IO_L17N_T2_A13_D29_14" pad="R11"/>
<connect gate="C" pin="IO_L17P_T2_A14_D30_14" pad="R10"/>
<connect gate="C" pin="IO_L18N_T2_A11_D27_14" pad="P9"/>
<connect gate="C" pin="IO_L18P_T2_A12_D28_14" pad="N9"/>
<connect gate="C" pin="IO_L19N_T3_A09_D25_VREF_14" pad="N6"/>
<connect gate="C" pin="IO_L19P_T3_A10_D26_14" pad="M6"/>
<connect gate="C" pin="IO_L1N_T0_34" pad="M4"/>
<connect gate="C" pin="IO_L20N_T3_A07_D23_14" pad="R8"/>
<connect gate="C" pin="IO_L20P_T3_A08_D24_14" pad="P8"/>
<connect gate="C" pin="IO_L21N_T3_DQS_A06_D22_14" pad="T8"/>
<connect gate="C" pin="IO_L21P_T3_DQS_14" pad="T7"/>
<connect gate="C" pin="IO_L22N_T3_A04_D20_14" pad="T10"/>
<connect gate="C" pin="IO_L22P_T3_A05_D21_14" pad="T9"/>
<connect gate="C" pin="IO_L23N_T3_A02_D18_14" pad="T5"/>
<connect gate="C" pin="IO_L23P_T3_A03_D19_14" pad="R5"/>
<connect gate="C" pin="IO_L24N_T3_A00_D16_14" pad="R7"/>
<connect gate="C" pin="IO_L24P_T3_A01_D17_14" pad="R6"/>
<connect gate="C" pin="IO_L2N_T0_34" pad="M1"/>
<connect gate="C" pin="IO_L2P_T0_34" pad="M2"/>
<connect gate="C" pin="IO_L3N_T0_DQS_34" pad="N2"/>
<connect gate="C" pin="IO_L3N_T0_DQS_EMCCLK_14" pad="M15"/>
<connect gate="C" pin="IO_L3P_T0_DQS_34" pad="N3"/>
<connect gate="C" pin="IO_L3P_T0_DQS_PUDC_B_14" pad="L15"/>
<connect gate="C" pin="IO_L4N_T0_34" pad="P1"/>
<connect gate="C" pin="IO_L4N_T0_D05_14" pad="M14"/>
<connect gate="C" pin="IO_L4P_T0_34" pad="N1"/>
<connect gate="C" pin="IO_L4P_T0_D04_14" pad="L14"/>
<connect gate="C" pin="IO_L5N_T0_34" pad="P3"/>
<connect gate="C" pin="IO_L5N_T0_D07_14" pad="L13"/>
<connect gate="C" pin="IO_L5P_T0_34" pad="P4"/>
<connect gate="C" pin="IO_L6N_T0_D08_VREF_14" pad="M12"/>
<connect gate="C" pin="IO_L6N_T0_VREF_34" pad="N4"/>
<connect gate="C" pin="IO_L6P_T0_34" pad="M5"/>
<connect gate="C" pin="IO_L7N_T1_34" pad="R1"/>
<connect gate="C" pin="IO_L7N_T1_D10_14" pad="N16"/>
<connect gate="C" pin="IO_L7P_T1_34" pad="R2"/>
<connect gate="C" pin="IO_L7P_T1_D09_14" pad="M16"/>
<connect gate="C" pin="IO_L8N_T1_34" pad="T2"/>
<connect gate="C" pin="IO_L8N_T1_D12_14" pad="P16"/>
<connect gate="C" pin="IO_L8P_T1_34" pad="R3"/>
<connect gate="C" pin="IO_L8P_T1_D11_14" pad="P15"/>
<connect gate="C" pin="IO_L9N_T1_DQS_34" pad="T3"/>
<connect gate="C" pin="IO_L9N_T1_DQS_D13_14" pad="R16"/>
<connect gate="C" pin="IO_L9P_T1_DQS_14" pad="R15"/>
<connect gate="C" pin="IO_L9P_T1_DQS_34" pad="T4"/>
<connect gate="C" pin="M0_0" pad="M9"/>
<connect gate="C" pin="M1_0" pad="M10"/>
<connect gate="C" pin="M2_0" pad="M11"/>
<connect gate="C" pin="TDI_0" pad="N7"/>
<connect gate="C" pin="TDO_0" pad="N8"/>
<connect gate="C" pin="TMS_0" pad="M7"/>
<connect gate="C" pin="VCCO_14" pad="T11"/>
<connect gate="C" pin="VCCO_14_2" pad="L16"/>
<connect gate="C" pin="VCCO_14_3" pad="M13"/>
<connect gate="C" pin="VCCO_14_4" pad="N10"/>
<connect gate="C" pin="VCCO_14_5" pad="P7"/>
<connect gate="C" pin="VCCO_14_6" pad="R14"/>
<connect gate="C" pin="VCCO_34" pad="T1"/>
<connect gate="C" pin="VCCO_34_2" pad="M3"/>
<connect gate="C" pin="VCCO_34_3" pad="R4"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2025 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="XC7A100T-2FTG256I"/>
<attribute name="MFR_NAME" value="AMD"/>
<attribute name="TYPE" value="Embedded"/>
</technology>
</technologies>
</device>
<device name="FTG256_AMD-M" package="FTG256_AMD-M">
<connects>
<connect gate="A" pin="CCLK_0" pad="E8"/>
<connect gate="A" pin="CFGBVS_0" pad="E7"/>
<connect gate="A" pin="GND" pad="F6"/>
<connect gate="A" pin="GND_2" pad="A1"/>
<connect gate="A" pin="GND_3" pad="A11"/>
<connect gate="A" pin="GND_4" pad="B8"/>
<connect gate="A" pin="GND_5" pad="C5"/>
<connect gate="A" pin="GND_6" pad="C15"/>
<connect gate="A" pin="GND_7" pad="D2"/>
<connect gate="A" pin="GND_8" pad="D12"/>
<connect gate="A" pin="GND_9" pad="E9"/>
<connect gate="A" pin="IO_0_15" pad="D10"/>
<connect gate="A" pin="IO_0_35" pad="E6"/>
<connect gate="A" pin="IO_L10N_T1_AD11N_15" pad="B16"/>
<connect gate="A" pin="IO_L10N_T1_AD15N_35" pad="D1"/>
<connect gate="A" pin="IO_L10P_T1_AD11P_15" pad="C16"/>
<connect gate="A" pin="IO_L10P_T1_AD15P_35" pad="E2"/>
<connect gate="A" pin="IO_L11N_T1_SRCC_15" pad="C12"/>
<connect gate="A" pin="IO_L11N_T1_SRCC_35" pad="D3"/>
<connect gate="A" pin="IO_L11P_T1_SRCC_15" pad="C11"/>
<connect gate="A" pin="IO_L11P_T1_SRCC_35" pad="E3"/>
<connect gate="A" pin="IO_L12N_T1_MRCC_15" pad="C13"/>
<connect gate="A" pin="IO_L12N_T1_MRCC_35" pad="C4"/>
<connect gate="A" pin="IO_L12P_T1_MRCC_15" pad="D13"/>
<connect gate="A" pin="IO_L12P_T1_MRCC_35" pad="D4"/>
<connect gate="A" pin="IO_L13N_T2_MRCC_15" pad="E13"/>
<connect gate="A" pin="IO_L13N_T2_MRCC_35" pad="E5"/>
<connect gate="A" pin="IO_L13P_T2_MRCC_15" pad="E12"/>
<connect gate="A" pin="IO_L13P_T2_MRCC_35" pad="F5"/>
<connect gate="A" pin="IO_L14N_T2_SRCC_15" pad="D11"/>
<connect gate="A" pin="IO_L14N_T2_SRCC_35" pad="F3"/>
<connect gate="A" pin="IO_L14P_T2_SRCC_15" pad="E11"/>
<connect gate="A" pin="IO_L14P_T2_SRCC_35" pad="F4"/>
<connect gate="A" pin="IO_L15N_T2_DQS_35" pad="E1"/>
<connect gate="A" pin="IO_L15N_T2_DQS_ADV_B_15" pad="D15"/>
<connect gate="A" pin="IO_L15P_T2_DQS_15" pad="D14"/>
<connect gate="A" pin="IO_L15P_T2_DQS_35" pad="F2"/>
<connect gate="A" pin="IO_L17N_T2_A25_15" pad="D16"/>
<connect gate="A" pin="IO_L17P_T2_A26_15" pad="E16"/>
<connect gate="A" pin="IO_L18N_T2_A23_15" pad="E15"/>
<connect gate="A" pin="IO_L1N_T0_AD0N_15" pad="C9"/>
<connect gate="A" pin="IO_L1N_T0_AD4N_35" pad="A7"/>
<connect gate="A" pin="IO_L1P_T0_AD0P_15" pad="C8"/>
<connect gate="A" pin="IO_L1P_T0_AD4P_35" pad="B7"/>
<connect gate="A" pin="IO_L2N_T0_AD12N_35" pad="B5"/>
<connect gate="A" pin="IO_L2N_T0_AD8N_15" pad="A9"/>
<connect gate="A" pin="IO_L2P_T0_AD12P_35" pad="B6"/>
<connect gate="A" pin="IO_L2P_T0_AD8P_15" pad="A8"/>
<connect gate="A" pin="IO_L3N_T0_DQS_AD1N_15" pad="A10"/>
<connect gate="A" pin="IO_L3N_T0_DQS_AD5N_35" pad="A4"/>
<connect gate="A" pin="IO_L3P_T0_DQS_AD1P_15" pad="B9"/>
<connect gate="A" pin="IO_L3P_T0_DQS_AD5P_35" pad="A5"/>
<connect gate="A" pin="IO_L4N_T0_15" pad="B11"/>
<connect gate="A" pin="IO_L4N_T0_35" pad="A3"/>
<connect gate="A" pin="IO_L4P_T0_15" pad="B10"/>
<connect gate="A" pin="IO_L4P_T0_35" pad="B4"/>
<connect gate="A" pin="IO_L5N_T0_AD13N_35" pad="C6"/>
<connect gate="A" pin="IO_L5N_T0_AD9N_15" pad="A12"/>
<connect gate="A" pin="IO_L5P_T0_AD13P_35" pad="C7"/>
<connect gate="A" pin="IO_L5P_T0_AD9P_15" pad="B12"/>
<connect gate="A" pin="IO_L6N_T0_VREF_15" pad="D9"/>
<connect gate="A" pin="IO_L6N_T0_VREF_35" pad="D5"/>
<connect gate="A" pin="IO_L6P_T0_15" pad="D8"/>
<connect gate="A" pin="IO_L6P_T0_35" pad="D6"/>
<connect gate="A" pin="IO_L7N_T1_AD2N_15" pad="A14"/>
<connect gate="A" pin="IO_L7N_T1_AD6N_35" pad="C2"/>
<connect gate="A" pin="IO_L7P_T1_AD2P_15" pad="A13"/>
<connect gate="A" pin="IO_L7P_T1_AD6P_35" pad="C3"/>
<connect gate="A" pin="IO_L8N_T1_AD10N_15" pad="B14"/>
<connect gate="A" pin="IO_L8N_T1_AD14N_35" pad="A2"/>
<connect gate="A" pin="IO_L8P_T1_AD10P_15" pad="C14"/>
<connect gate="A" pin="IO_L8P_T1_AD14P_35" pad="B2"/>
<connect gate="A" pin="IO_L9N_T1_DQS_AD3N_15" pad="A15"/>
<connect gate="A" pin="IO_L9N_T1_DQS_AD7N_35" pad="B1"/>
<connect gate="A" pin="IO_L9P_T1_DQS_AD3P_15" pad="B15"/>
<connect gate="A" pin="IO_L9P_T1_DQS_AD7P_35" pad="C1"/>
<connect gate="A" pin="VCCBRAM" pad="E10"/>
<connect gate="A" pin="VCCO_15" pad="E14"/>
<connect gate="A" pin="VCCO_15_2" pad="A16"/>
<connect gate="A" pin="VCCO_15_3" pad="B13"/>
<connect gate="A" pin="VCCO_15_4" pad="C10"/>
<connect gate="A" pin="VCCO_35" pad="F1"/>
<connect gate="A" pin="VCCO_35_2" pad="A6"/>
<connect gate="A" pin="VCCO_35_3" pad="B3"/>
<connect gate="A" pin="VCCO_35_4" pad="D7"/>
<connect gate="A" pin="VCCO_35_5" pad="E4"/>
<connect gate="B" pin="DONE_0" pad="H10"/>
<connect gate="B" pin="DXN_0" pad="K7"/>
<connect gate="B" pin="DXP_0" pad="K8"/>
<connect gate="B" pin="GND" pad="L11"/>
<connect gate="B" pin="GNDADC_0" pad="G7"/>
<connect gate="B" pin="GND_10" pad="K4"/>
<connect gate="B" pin="GND_11" pad="K6"/>
<connect gate="B" pin="GND_12" pad="K14"/>
<connect gate="B" pin="GND_13" pad="L1"/>
<connect gate="B" pin="GND_2" pad="F10"/>
<connect gate="B" pin="GND_3" pad="F16"/>
<connect gate="B" pin="GND_4" pad="G3"/>
<connect gate="B" pin="GND_5" pad="G9"/>
<connect gate="B" pin="GND_6" pad="G13"/>
<connect gate="B" pin="GND_7" pad="H6"/>
<connect gate="B" pin="GND_8" pad="J9"/>
<connect gate="B" pin="GND_9" pad="J11"/>
<connect gate="B" pin="INIT_B_0" pad="K10"/>
<connect gate="B" pin="IO_0_14" pad="K12"/>
<connect gate="B" pin="IO_0_34" pad="L5"/>
<connect gate="B" pin="IO_25_15" pad="G11"/>
<connect gate="B" pin="IO_25_35" pad="K5"/>
<connect gate="B" pin="IO_L16N_T2_35" pad="G4"/>
<connect gate="B" pin="IO_L16N_T2_A27_15" pad="F13"/>
<connect gate="B" pin="IO_L16P_T2_35" pad="G5"/>
<connect gate="B" pin="IO_L16P_T2_A28_15" pad="F12"/>
<connect gate="B" pin="IO_L17N_T2_35" pad="G1"/>
<connect gate="B" pin="IO_L17P_T2_35" pad="G2"/>
<connect gate="B" pin="IO_L18N_T2_35" pad="H4"/>
<connect gate="B" pin="IO_L18P_T2_35" pad="H5"/>
<connect gate="B" pin="IO_L18P_T2_A24_15" pad="F15"/>
<connect gate="B" pin="IO_L19N_T3_A21_VREF_15" pad="G12"/>
<connect gate="B" pin="IO_L19N_T3_VREF_35" pad="J4"/>
<connect gate="B" pin="IO_L19P_T3_35" pad="J5"/>
<connect gate="B" pin="IO_L19P_T3_A22_15" pad="H11"/>
<connect gate="B" pin="IO_L1N_T0_D01_DIN_14" pad="J14"/>
<connect gate="B" pin="IO_L1P_T0_34" pad="L4"/>
<connect gate="B" pin="IO_L1P_T0_D00_MOSI_14" pad="J13"/>
<connect gate="B" pin="IO_L20N_T3_35" pad="H1"/>
<connect gate="B" pin="IO_L20N_T3_A19_15" pad="H13"/>
<connect gate="B" pin="IO_L20P_T3_35" pad="H2"/>
<connect gate="B" pin="IO_L20P_T3_A20_15" pad="H12"/>
<connect gate="B" pin="IO_L21N_T3_DQS_35" pad="H3"/>
<connect gate="B" pin="IO_L21N_T3_DQS_A18_15" pad="F14"/>
<connect gate="B" pin="IO_L21P_T3_DQS_15" pad="G14"/>
<connect gate="B" pin="IO_L21P_T3_DQS_35" pad="J3"/>
<connect gate="B" pin="IO_L22N_T3_35" pad="J1"/>
<connect gate="B" pin="IO_L22N_T3_A16_15" pad="G16"/>
<connect gate="B" pin="IO_L22P_T3_35" pad="K1"/>
<connect gate="B" pin="IO_L22P_T3_A17_15" pad="H16"/>
<connect gate="B" pin="IO_L23N_T3_35" pad="L2"/>
<connect gate="B" pin="IO_L23N_T3_FWE_B_15" pad="J16"/>
<connect gate="B" pin="IO_L23P_T3_35" pad="L3"/>
<connect gate="B" pin="IO_L23P_T3_FOE_B_15" pad="J15"/>
<connect gate="B" pin="IO_L24N_T3_35" pad="K2"/>
<connect gate="B" pin="IO_L24N_T3_RS0_15" pad="G15"/>
<connect gate="B" pin="IO_L24P_T3_35" pad="K3"/>
<connect gate="B" pin="IO_L24P_T3_RS1_15" pad="H14"/>
<connect gate="B" pin="IO_L2N_T0_D03_14" pad="K16"/>
<connect gate="B" pin="IO_L2P_T0_D02_14" pad="K15"/>
<connect gate="B" pin="IO_L5P_T0_D06_14" pad="K13"/>
<connect gate="B" pin="IO_L6P_T0_FCS_B_14" pad="L12"/>
<connect gate="B" pin="PROGRAM_B_0" pad="L9"/>
<connect gate="B" pin="TCK_0" pad="L7"/>
<connect gate="B" pin="VCCADC_0" pad="G8"/>
<connect gate="B" pin="VCCAUX" pad="L10"/>
<connect gate="B" pin="VCCAUX_2" pad="G10"/>
<connect gate="B" pin="VCCAUX_3" pad="J10"/>
<connect gate="B" pin="VCCAUX_4" pad="K11"/>
<connect gate="B" pin="VCCBATT_0" pad="F8"/>
<connect gate="B" pin="VCCBRAM" pad="F11"/>
<connect gate="B" pin="VCCINT" pad="L8"/>
<connect gate="B" pin="VCCINT_2" pad="F7"/>
<connect gate="B" pin="VCCINT_3" pad="F9"/>
<connect gate="B" pin="VCCINT_4" pad="G6"/>
<connect gate="B" pin="VCCINT_5" pad="H9"/>
<connect gate="B" pin="VCCINT_6" pad="J6"/>
<connect gate="B" pin="VCCINT_7" pad="K9"/>
<connect gate="B" pin="VCCO_0" pad="L6"/>
<connect gate="B" pin="VCCO_15" pad="J12"/>
<connect gate="B" pin="VCCO_15_2" pad="H15"/>
<connect gate="B" pin="VCCO_35" pad="J2"/>
<connect gate="B" pin="VN_0" pad="J7"/>
<connect gate="B" pin="VP_0" pad="H8"/>
<connect gate="B" pin="VREFN_0" pad="H7"/>
<connect gate="B" pin="VREFP_0" pad="J8"/>
<connect gate="C" pin="GND" pad="T16"/>
<connect gate="C" pin="GND_2" pad="M8"/>
<connect gate="C" pin="GND_3" pad="N5"/>
<connect gate="C" pin="GND_4" pad="N15"/>
<connect gate="C" pin="GND_5" pad="P2"/>
<connect gate="C" pin="GND_6" pad="P12"/>
<connect gate="C" pin="GND_7" pad="R9"/>
<connect gate="C" pin="GND_8" pad="T6"/>
<connect gate="C" pin="IO_25_14" pad="P6"/>
<connect gate="C" pin="IO_L10N_T1_D15_14" pad="T15"/>
<connect gate="C" pin="IO_L10P_T1_34" pad="P5"/>
<connect gate="C" pin="IO_L10P_T1_D14_14" pad="T14"/>
<connect gate="C" pin="IO_L11N_T1_SRCC_14" pad="P13"/>
<connect gate="C" pin="IO_L11P_T1_SRCC_14" pad="N13"/>
<connect gate="C" pin="IO_L12N_T1_MRCC_14" pad="P14"/>
<connect gate="C" pin="IO_L12P_T1_MRCC_14" pad="N14"/>
<connect gate="C" pin="IO_L13N_T2_MRCC_14" pad="N12"/>
<connect gate="C" pin="IO_L13P_T2_MRCC_14" pad="N11"/>
<connect gate="C" pin="IO_L14N_T2_SRCC_14" pad="P11"/>
<connect gate="C" pin="IO_L14P_T2_SRCC_14" pad="P10"/>
<connect gate="C" pin="IO_L15N_T2_DQS_DOUT_CSO_B_14" pad="T12"/>
<connect gate="C" pin="IO_L15P_T2_DQS_RDWR_B_14" pad="R12"/>
<connect gate="C" pin="IO_L16N_T2_A15_D31_14" pad="T13"/>
<connect gate="C" pin="IO_L16P_T2_CSI_B_14" pad="R13"/>
<connect gate="C" pin="IO_L17N_T2_A13_D29_14" pad="R11"/>
<connect gate="C" pin="IO_L17P_T2_A14_D30_14" pad="R10"/>
<connect gate="C" pin="IO_L18N_T2_A11_D27_14" pad="P9"/>
<connect gate="C" pin="IO_L18P_T2_A12_D28_14" pad="N9"/>
<connect gate="C" pin="IO_L19N_T3_A09_D25_VREF_14" pad="N6"/>
<connect gate="C" pin="IO_L19P_T3_A10_D26_14" pad="M6"/>
<connect gate="C" pin="IO_L1N_T0_34" pad="M4"/>
<connect gate="C" pin="IO_L20N_T3_A07_D23_14" pad="R8"/>
<connect gate="C" pin="IO_L20P_T3_A08_D24_14" pad="P8"/>
<connect gate="C" pin="IO_L21N_T3_DQS_A06_D22_14" pad="T8"/>
<connect gate="C" pin="IO_L21P_T3_DQS_14" pad="T7"/>
<connect gate="C" pin="IO_L22N_T3_A04_D20_14" pad="T10"/>
<connect gate="C" pin="IO_L22P_T3_A05_D21_14" pad="T9"/>
<connect gate="C" pin="IO_L23N_T3_A02_D18_14" pad="T5"/>
<connect gate="C" pin="IO_L23P_T3_A03_D19_14" pad="R5"/>
<connect gate="C" pin="IO_L24N_T3_A00_D16_14" pad="R7"/>
<connect gate="C" pin="IO_L24P_T3_A01_D17_14" pad="R6"/>
<connect gate="C" pin="IO_L2N_T0_34" pad="M1"/>
<connect gate="C" pin="IO_L2P_T0_34" pad="M2"/>
<connect gate="C" pin="IO_L3N_T0_DQS_34" pad="N2"/>
<connect gate="C" pin="IO_L3N_T0_DQS_EMCCLK_14" pad="M15"/>
<connect gate="C" pin="IO_L3P_T0_DQS_34" pad="N3"/>
<connect gate="C" pin="IO_L3P_T0_DQS_PUDC_B_14" pad="L15"/>
<connect gate="C" pin="IO_L4N_T0_34" pad="P1"/>
<connect gate="C" pin="IO_L4N_T0_D05_14" pad="M14"/>
<connect gate="C" pin="IO_L4P_T0_34" pad="N1"/>
<connect gate="C" pin="IO_L4P_T0_D04_14" pad="L14"/>
<connect gate="C" pin="IO_L5N_T0_34" pad="P3"/>
<connect gate="C" pin="IO_L5N_T0_D07_14" pad="L13"/>
<connect gate="C" pin="IO_L5P_T0_34" pad="P4"/>
<connect gate="C" pin="IO_L6N_T0_D08_VREF_14" pad="M12"/>
<connect gate="C" pin="IO_L6N_T0_VREF_34" pad="N4"/>
<connect gate="C" pin="IO_L6P_T0_34" pad="M5"/>
<connect gate="C" pin="IO_L7N_T1_34" pad="R1"/>
<connect gate="C" pin="IO_L7N_T1_D10_14" pad="N16"/>
<connect gate="C" pin="IO_L7P_T1_34" pad="R2"/>
<connect gate="C" pin="IO_L7P_T1_D09_14" pad="M16"/>
<connect gate="C" pin="IO_L8N_T1_34" pad="T2"/>
<connect gate="C" pin="IO_L8N_T1_D12_14" pad="P16"/>
<connect gate="C" pin="IO_L8P_T1_34" pad="R3"/>
<connect gate="C" pin="IO_L8P_T1_D11_14" pad="P15"/>
<connect gate="C" pin="IO_L9N_T1_DQS_34" pad="T3"/>
<connect gate="C" pin="IO_L9N_T1_DQS_D13_14" pad="R16"/>
<connect gate="C" pin="IO_L9P_T1_DQS_14" pad="R15"/>
<connect gate="C" pin="IO_L9P_T1_DQS_34" pad="T4"/>
<connect gate="C" pin="M0_0" pad="M9"/>
<connect gate="C" pin="M1_0" pad="M10"/>
<connect gate="C" pin="M2_0" pad="M11"/>
<connect gate="C" pin="TDI_0" pad="N7"/>
<connect gate="C" pin="TDO_0" pad="N8"/>
<connect gate="C" pin="TMS_0" pad="M7"/>
<connect gate="C" pin="VCCO_14" pad="T11"/>
<connect gate="C" pin="VCCO_14_2" pad="L16"/>
<connect gate="C" pin="VCCO_14_3" pad="M13"/>
<connect gate="C" pin="VCCO_14_4" pad="N10"/>
<connect gate="C" pin="VCCO_14_5" pad="P7"/>
<connect gate="C" pin="VCCO_14_6" pad="R14"/>
<connect gate="C" pin="VCCO_34" pad="T1"/>
<connect gate="C" pin="VCCO_34_2" pad="M3"/>
<connect gate="C" pin="VCCO_34_3" pad="R4"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2025 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="XC7A100T-2FTG256I"/>
<attribute name="MFR_NAME" value="AMD"/>
<attribute name="TYPE" value="Embedded"/>
</technology>
</technologies>
</device>
<device name="FTG256_AMD-L" package="FTG256_AMD-L">
<connects>
<connect gate="A" pin="CCLK_0" pad="E8"/>
<connect gate="A" pin="CFGBVS_0" pad="E7"/>
<connect gate="A" pin="GND" pad="F6"/>
<connect gate="A" pin="GND_2" pad="A1"/>
<connect gate="A" pin="GND_3" pad="A11"/>
<connect gate="A" pin="GND_4" pad="B8"/>
<connect gate="A" pin="GND_5" pad="C5"/>
<connect gate="A" pin="GND_6" pad="C15"/>
<connect gate="A" pin="GND_7" pad="D2"/>
<connect gate="A" pin="GND_8" pad="D12"/>
<connect gate="A" pin="GND_9" pad="E9"/>
<connect gate="A" pin="IO_0_15" pad="D10"/>
<connect gate="A" pin="IO_0_35" pad="E6"/>
<connect gate="A" pin="IO_L10N_T1_AD11N_15" pad="B16"/>
<connect gate="A" pin="IO_L10N_T1_AD15N_35" pad="D1"/>
<connect gate="A" pin="IO_L10P_T1_AD11P_15" pad="C16"/>
<connect gate="A" pin="IO_L10P_T1_AD15P_35" pad="E2"/>
<connect gate="A" pin="IO_L11N_T1_SRCC_15" pad="C12"/>
<connect gate="A" pin="IO_L11N_T1_SRCC_35" pad="D3"/>
<connect gate="A" pin="IO_L11P_T1_SRCC_15" pad="C11"/>
<connect gate="A" pin="IO_L11P_T1_SRCC_35" pad="E3"/>
<connect gate="A" pin="IO_L12N_T1_MRCC_15" pad="C13"/>
<connect gate="A" pin="IO_L12N_T1_MRCC_35" pad="C4"/>
<connect gate="A" pin="IO_L12P_T1_MRCC_15" pad="D13"/>
<connect gate="A" pin="IO_L12P_T1_MRCC_35" pad="D4"/>
<connect gate="A" pin="IO_L13N_T2_MRCC_15" pad="E13"/>
<connect gate="A" pin="IO_L13N_T2_MRCC_35" pad="E5"/>
<connect gate="A" pin="IO_L13P_T2_MRCC_15" pad="E12"/>
<connect gate="A" pin="IO_L13P_T2_MRCC_35" pad="F5"/>
<connect gate="A" pin="IO_L14N_T2_SRCC_15" pad="D11"/>
<connect gate="A" pin="IO_L14N_T2_SRCC_35" pad="F3"/>
<connect gate="A" pin="IO_L14P_T2_SRCC_15" pad="E11"/>
<connect gate="A" pin="IO_L14P_T2_SRCC_35" pad="F4"/>
<connect gate="A" pin="IO_L15N_T2_DQS_35" pad="E1"/>
<connect gate="A" pin="IO_L15N_T2_DQS_ADV_B_15" pad="D15"/>
<connect gate="A" pin="IO_L15P_T2_DQS_15" pad="D14"/>
<connect gate="A" pin="IO_L15P_T2_DQS_35" pad="F2"/>
<connect gate="A" pin="IO_L17N_T2_A25_15" pad="D16"/>
<connect gate="A" pin="IO_L17P_T2_A26_15" pad="E16"/>
<connect gate="A" pin="IO_L18N_T2_A23_15" pad="E15"/>
<connect gate="A" pin="IO_L1N_T0_AD0N_15" pad="C9"/>
<connect gate="A" pin="IO_L1N_T0_AD4N_35" pad="A7"/>
<connect gate="A" pin="IO_L1P_T0_AD0P_15" pad="C8"/>
<connect gate="A" pin="IO_L1P_T0_AD4P_35" pad="B7"/>
<connect gate="A" pin="IO_L2N_T0_AD12N_35" pad="B5"/>
<connect gate="A" pin="IO_L2N_T0_AD8N_15" pad="A9"/>
<connect gate="A" pin="IO_L2P_T0_AD12P_35" pad="B6"/>
<connect gate="A" pin="IO_L2P_T0_AD8P_15" pad="A8"/>
<connect gate="A" pin="IO_L3N_T0_DQS_AD1N_15" pad="A10"/>
<connect gate="A" pin="IO_L3N_T0_DQS_AD5N_35" pad="A4"/>
<connect gate="A" pin="IO_L3P_T0_DQS_AD1P_15" pad="B9"/>
<connect gate="A" pin="IO_L3P_T0_DQS_AD5P_35" pad="A5"/>
<connect gate="A" pin="IO_L4N_T0_15" pad="B11"/>
<connect gate="A" pin="IO_L4N_T0_35" pad="A3"/>
<connect gate="A" pin="IO_L4P_T0_15" pad="B10"/>
<connect gate="A" pin="IO_L4P_T0_35" pad="B4"/>
<connect gate="A" pin="IO_L5N_T0_AD13N_35" pad="C6"/>
<connect gate="A" pin="IO_L5N_T0_AD9N_15" pad="A12"/>
<connect gate="A" pin="IO_L5P_T0_AD13P_35" pad="C7"/>
<connect gate="A" pin="IO_L5P_T0_AD9P_15" pad="B12"/>
<connect gate="A" pin="IO_L6N_T0_VREF_15" pad="D9"/>
<connect gate="A" pin="IO_L6N_T0_VREF_35" pad="D5"/>
<connect gate="A" pin="IO_L6P_T0_15" pad="D8"/>
<connect gate="A" pin="IO_L6P_T0_35" pad="D6"/>
<connect gate="A" pin="IO_L7N_T1_AD2N_15" pad="A14"/>
<connect gate="A" pin="IO_L7N_T1_AD6N_35" pad="C2"/>
<connect gate="A" pin="IO_L7P_T1_AD2P_15" pad="A13"/>
<connect gate="A" pin="IO_L7P_T1_AD6P_35" pad="C3"/>
<connect gate="A" pin="IO_L8N_T1_AD10N_15" pad="B14"/>
<connect gate="A" pin="IO_L8N_T1_AD14N_35" pad="A2"/>
<connect gate="A" pin="IO_L8P_T1_AD10P_15" pad="C14"/>
<connect gate="A" pin="IO_L8P_T1_AD14P_35" pad="B2"/>
<connect gate="A" pin="IO_L9N_T1_DQS_AD3N_15" pad="A15"/>
<connect gate="A" pin="IO_L9N_T1_DQS_AD7N_35" pad="B1"/>
<connect gate="A" pin="IO_L9P_T1_DQS_AD3P_15" pad="B15"/>
<connect gate="A" pin="IO_L9P_T1_DQS_AD7P_35" pad="C1"/>
<connect gate="A" pin="VCCBRAM" pad="E10"/>
<connect gate="A" pin="VCCO_15" pad="E14"/>
<connect gate="A" pin="VCCO_15_2" pad="A16"/>
<connect gate="A" pin="VCCO_15_3" pad="B13"/>
<connect gate="A" pin="VCCO_15_4" pad="C10"/>
<connect gate="A" pin="VCCO_35" pad="F1"/>
<connect gate="A" pin="VCCO_35_2" pad="A6"/>
<connect gate="A" pin="VCCO_35_3" pad="B3"/>
<connect gate="A" pin="VCCO_35_4" pad="D7"/>
<connect gate="A" pin="VCCO_35_5" pad="E4"/>
<connect gate="B" pin="DONE_0" pad="H10"/>
<connect gate="B" pin="DXN_0" pad="K7"/>
<connect gate="B" pin="DXP_0" pad="K8"/>
<connect gate="B" pin="GND" pad="L11"/>
<connect gate="B" pin="GNDADC_0" pad="G7"/>
<connect gate="B" pin="GND_10" pad="K4"/>
<connect gate="B" pin="GND_11" pad="K6"/>
<connect gate="B" pin="GND_12" pad="K14"/>
<connect gate="B" pin="GND_13" pad="L1"/>
<connect gate="B" pin="GND_2" pad="F10"/>
<connect gate="B" pin="GND_3" pad="F16"/>
<connect gate="B" pin="GND_4" pad="G3"/>
<connect gate="B" pin="GND_5" pad="G9"/>
<connect gate="B" pin="GND_6" pad="G13"/>
<connect gate="B" pin="GND_7" pad="H6"/>
<connect gate="B" pin="GND_8" pad="J9"/>
<connect gate="B" pin="GND_9" pad="J11"/>
<connect gate="B" pin="INIT_B_0" pad="K10"/>
<connect gate="B" pin="IO_0_14" pad="K12"/>
<connect gate="B" pin="IO_0_34" pad="L5"/>
<connect gate="B" pin="IO_25_15" pad="G11"/>
<connect gate="B" pin="IO_25_35" pad="K5"/>
<connect gate="B" pin="IO_L16N_T2_35" pad="G4"/>
<connect gate="B" pin="IO_L16N_T2_A27_15" pad="F13"/>
<connect gate="B" pin="IO_L16P_T2_35" pad="G5"/>
<connect gate="B" pin="IO_L16P_T2_A28_15" pad="F12"/>
<connect gate="B" pin="IO_L17N_T2_35" pad="G1"/>
<connect gate="B" pin="IO_L17P_T2_35" pad="G2"/>
<connect gate="B" pin="IO_L18N_T2_35" pad="H4"/>
<connect gate="B" pin="IO_L18P_T2_35" pad="H5"/>
<connect gate="B" pin="IO_L18P_T2_A24_15" pad="F15"/>
<connect gate="B" pin="IO_L19N_T3_A21_VREF_15" pad="G12"/>
<connect gate="B" pin="IO_L19N_T3_VREF_35" pad="J4"/>
<connect gate="B" pin="IO_L19P_T3_35" pad="J5"/>
<connect gate="B" pin="IO_L19P_T3_A22_15" pad="H11"/>
<connect gate="B" pin="IO_L1N_T0_D01_DIN_14" pad="J14"/>
<connect gate="B" pin="IO_L1P_T0_34" pad="L4"/>
<connect gate="B" pin="IO_L1P_T0_D00_MOSI_14" pad="J13"/>
<connect gate="B" pin="IO_L20N_T3_35" pad="H1"/>
<connect gate="B" pin="IO_L20N_T3_A19_15" pad="H13"/>
<connect gate="B" pin="IO_L20P_T3_35" pad="H2"/>
<connect gate="B" pin="IO_L20P_T3_A20_15" pad="H12"/>
<connect gate="B" pin="IO_L21N_T3_DQS_35" pad="H3"/>
<connect gate="B" pin="IO_L21N_T3_DQS_A18_15" pad="F14"/>
<connect gate="B" pin="IO_L21P_T3_DQS_15" pad="G14"/>
<connect gate="B" pin="IO_L21P_T3_DQS_35" pad="J3"/>
<connect gate="B" pin="IO_L22N_T3_35" pad="J1"/>
<connect gate="B" pin="IO_L22N_T3_A16_15" pad="G16"/>
<connect gate="B" pin="IO_L22P_T3_35" pad="K1"/>
<connect gate="B" pin="IO_L22P_T3_A17_15" pad="H16"/>
<connect gate="B" pin="IO_L23N_T3_35" pad="L2"/>
<connect gate="B" pin="IO_L23N_T3_FWE_B_15" pad="J16"/>
<connect gate="B" pin="IO_L23P_T3_35" pad="L3"/>
<connect gate="B" pin="IO_L23P_T3_FOE_B_15" pad="J15"/>
<connect gate="B" pin="IO_L24N_T3_35" pad="K2"/>
<connect gate="B" pin="IO_L24N_T3_RS0_15" pad="G15"/>
<connect gate="B" pin="IO_L24P_T3_35" pad="K3"/>
<connect gate="B" pin="IO_L24P_T3_RS1_15" pad="H14"/>
<connect gate="B" pin="IO_L2N_T0_D03_14" pad="K16"/>
<connect gate="B" pin="IO_L2P_T0_D02_14" pad="K15"/>
<connect gate="B" pin="IO_L5P_T0_D06_14" pad="K13"/>
<connect gate="B" pin="IO_L6P_T0_FCS_B_14" pad="L12"/>
<connect gate="B" pin="PROGRAM_B_0" pad="L9"/>
<connect gate="B" pin="TCK_0" pad="L7"/>
<connect gate="B" pin="VCCADC_0" pad="G8"/>
<connect gate="B" pin="VCCAUX" pad="L10"/>
<connect gate="B" pin="VCCAUX_2" pad="G10"/>
<connect gate="B" pin="VCCAUX_3" pad="J10"/>
<connect gate="B" pin="VCCAUX_4" pad="K11"/>
<connect gate="B" pin="VCCBATT_0" pad="F8"/>
<connect gate="B" pin="VCCBRAM" pad="F11"/>
<connect gate="B" pin="VCCINT" pad="L8"/>
<connect gate="B" pin="VCCINT_2" pad="F7"/>
<connect gate="B" pin="VCCINT_3" pad="F9"/>
<connect gate="B" pin="VCCINT_4" pad="G6"/>
<connect gate="B" pin="VCCINT_5" pad="H9"/>
<connect gate="B" pin="VCCINT_6" pad="J6"/>
<connect gate="B" pin="VCCINT_7" pad="K9"/>
<connect gate="B" pin="VCCO_0" pad="L6"/>
<connect gate="B" pin="VCCO_15" pad="J12"/>
<connect gate="B" pin="VCCO_15_2" pad="H15"/>
<connect gate="B" pin="VCCO_35" pad="J2"/>
<connect gate="B" pin="VN_0" pad="J7"/>
<connect gate="B" pin="VP_0" pad="H8"/>
<connect gate="B" pin="VREFN_0" pad="H7"/>
<connect gate="B" pin="VREFP_0" pad="J8"/>
<connect gate="C" pin="GND" pad="T16"/>
<connect gate="C" pin="GND_2" pad="M8"/>
<connect gate="C" pin="GND_3" pad="N5"/>
<connect gate="C" pin="GND_4" pad="N15"/>
<connect gate="C" pin="GND_5" pad="P2"/>
<connect gate="C" pin="GND_6" pad="P12"/>
<connect gate="C" pin="GND_7" pad="R9"/>
<connect gate="C" pin="GND_8" pad="T6"/>
<connect gate="C" pin="IO_25_14" pad="P6"/>
<connect gate="C" pin="IO_L10N_T1_D15_14" pad="T15"/>
<connect gate="C" pin="IO_L10P_T1_34" pad="P5"/>
<connect gate="C" pin="IO_L10P_T1_D14_14" pad="T14"/>
<connect gate="C" pin="IO_L11N_T1_SRCC_14" pad="P13"/>
<connect gate="C" pin="IO_L11P_T1_SRCC_14" pad="N13"/>
<connect gate="C" pin="IO_L12N_T1_MRCC_14" pad="P14"/>
<connect gate="C" pin="IO_L12P_T1_MRCC_14" pad="N14"/>
<connect gate="C" pin="IO_L13N_T2_MRCC_14" pad="N12"/>
<connect gate="C" pin="IO_L13P_T2_MRCC_14" pad="N11"/>
<connect gate="C" pin="IO_L14N_T2_SRCC_14" pad="P11"/>
<connect gate="C" pin="IO_L14P_T2_SRCC_14" pad="P10"/>
<connect gate="C" pin="IO_L15N_T2_DQS_DOUT_CSO_B_14" pad="T12"/>
<connect gate="C" pin="IO_L15P_T2_DQS_RDWR_B_14" pad="R12"/>
<connect gate="C" pin="IO_L16N_T2_A15_D31_14" pad="T13"/>
<connect gate="C" pin="IO_L16P_T2_CSI_B_14" pad="R13"/>
<connect gate="C" pin="IO_L17N_T2_A13_D29_14" pad="R11"/>
<connect gate="C" pin="IO_L17P_T2_A14_D30_14" pad="R10"/>
<connect gate="C" pin="IO_L18N_T2_A11_D27_14" pad="P9"/>
<connect gate="C" pin="IO_L18P_T2_A12_D28_14" pad="N9"/>
<connect gate="C" pin="IO_L19N_T3_A09_D25_VREF_14" pad="N6"/>
<connect gate="C" pin="IO_L19P_T3_A10_D26_14" pad="M6"/>
<connect gate="C" pin="IO_L1N_T0_34" pad="M4"/>
<connect gate="C" pin="IO_L20N_T3_A07_D23_14" pad="R8"/>
<connect gate="C" pin="IO_L20P_T3_A08_D24_14" pad="P8"/>
<connect gate="C" pin="IO_L21N_T3_DQS_A06_D22_14" pad="T8"/>
<connect gate="C" pin="IO_L21P_T3_DQS_14" pad="T7"/>
<connect gate="C" pin="IO_L22N_T3_A04_D20_14" pad="T10"/>
<connect gate="C" pin="IO_L22P_T3_A05_D21_14" pad="T9"/>
<connect gate="C" pin="IO_L23N_T3_A02_D18_14" pad="T5"/>
<connect gate="C" pin="IO_L23P_T3_A03_D19_14" pad="R5"/>
<connect gate="C" pin="IO_L24N_T3_A00_D16_14" pad="R7"/>
<connect gate="C" pin="IO_L24P_T3_A01_D17_14" pad="R6"/>
<connect gate="C" pin="IO_L2N_T0_34" pad="M1"/>
<connect gate="C" pin="IO_L2P_T0_34" pad="M2"/>
<connect gate="C" pin="IO_L3N_T0_DQS_34" pad="N2"/>
<connect gate="C" pin="IO_L3N_T0_DQS_EMCCLK_14" pad="M15"/>
<connect gate="C" pin="IO_L3P_T0_DQS_34" pad="N3"/>
<connect gate="C" pin="IO_L3P_T0_DQS_PUDC_B_14" pad="L15"/>
<connect gate="C" pin="IO_L4N_T0_34" pad="P1"/>
<connect gate="C" pin="IO_L4N_T0_D05_14" pad="M14"/>
<connect gate="C" pin="IO_L4P_T0_34" pad="N1"/>
<connect gate="C" pin="IO_L4P_T0_D04_14" pad="L14"/>
<connect gate="C" pin="IO_L5N_T0_34" pad="P3"/>
<connect gate="C" pin="IO_L5N_T0_D07_14" pad="L13"/>
<connect gate="C" pin="IO_L5P_T0_34" pad="P4"/>
<connect gate="C" pin="IO_L6N_T0_D08_VREF_14" pad="M12"/>
<connect gate="C" pin="IO_L6N_T0_VREF_34" pad="N4"/>
<connect gate="C" pin="IO_L6P_T0_34" pad="M5"/>
<connect gate="C" pin="IO_L7N_T1_34" pad="R1"/>
<connect gate="C" pin="IO_L7N_T1_D10_14" pad="N16"/>
<connect gate="C" pin="IO_L7P_T1_34" pad="R2"/>
<connect gate="C" pin="IO_L7P_T1_D09_14" pad="M16"/>
<connect gate="C" pin="IO_L8N_T1_34" pad="T2"/>
<connect gate="C" pin="IO_L8N_T1_D12_14" pad="P16"/>
<connect gate="C" pin="IO_L8P_T1_34" pad="R3"/>
<connect gate="C" pin="IO_L8P_T1_D11_14" pad="P15"/>
<connect gate="C" pin="IO_L9N_T1_DQS_34" pad="T3"/>
<connect gate="C" pin="IO_L9N_T1_DQS_D13_14" pad="R16"/>
<connect gate="C" pin="IO_L9P_T1_DQS_14" pad="R15"/>
<connect gate="C" pin="IO_L9P_T1_DQS_34" pad="T4"/>
<connect gate="C" pin="M0_0" pad="M9"/>
<connect gate="C" pin="M1_0" pad="M10"/>
<connect gate="C" pin="M2_0" pad="M11"/>
<connect gate="C" pin="TDI_0" pad="N7"/>
<connect gate="C" pin="TDO_0" pad="N8"/>
<connect gate="C" pin="TMS_0" pad="M7"/>
<connect gate="C" pin="VCCO_14" pad="T11"/>
<connect gate="C" pin="VCCO_14_2" pad="L16"/>
<connect gate="C" pin="VCCO_14_3" pad="M13"/>
<connect gate="C" pin="VCCO_14_4" pad="N10"/>
<connect gate="C" pin="VCCO_14_5" pad="P7"/>
<connect gate="C" pin="VCCO_14_6" pad="R14"/>
<connect gate="C" pin="VCCO_34" pad="T1"/>
<connect gate="C" pin="VCCO_34_2" pad="M3"/>
<connect gate="C" pin="VCCO_34_3" pad="R4"/>
</connects>
<technologies>
<technology name="">
<attribute name="COPYRIGHT" value="Copyright (C) 2025 Ultra Librarian. All rights reserved."/>
<attribute name="MANUFACTURER_PART_NUMBER" value="XC7A100T-2FTG256I"/>
<attribute name="MFR_NAME" value="AMD"/>
<attribute name="TYPE" value="Embedded"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
</devicesets>
</library>
</drawing>
</eagle>
