<?xml version="1.0" encoding="utf-8"?>
<!--/420630/1593508/2.50/73/0/Integrated Circuit/-->
<!DOCTYPE curve SYSTEM "eagle.dtd">
<eagle version="7.7.0">
<drawing>
<library>
<description>&lt;AD9523BCPZ, PLL Clock Driver Dual, 72-Pin LFCSP VQ&lt;/b&gt;&lt;p&gt;
&lt;author&gt;Created by SamacSys&lt;/author&gt;</description>
<packages>
<package name="QFN50P1000X1000X100-73N">
<description>&lt;b&gt;QFN50P1000X1000X100-73N&lt;/b&gt;&lt;br&gt;
</description>
</package>
</packages>
<symbols>
<symbol name="AD9523BCPZ">
<pin name="LDO_PLL1" direction="io"/>
<pin name="VDD3_PLL1" direction="io"/>
<pin name="REFA" direction="io"/>
<pin name="~REFA" direction="io"/>
<pin name="REFB" direction="io"/>
<pin name="~REFB" direction="io"/>
<pin name="LF1_EXT_CAP" direction="io"/>
<pin name="OSC_CTRL" direction="io"/>
<pin name="OSC_IN" direction="io"/>
<pin name="~OSC_IN" direction="io"/>
<pin name="LF2_EXT_CAP" direction="io"/>
<pin name="LDO_PLL2" direction="io"/>
<pin name="VDD3_PLL2" direction="io"/>
<pin name="LDO_VCO" direction="io"/>
<pin name="~PD" direction="io"/>
<pin name="REF_SEL" direction="io"/>
<pin name="~SYNC" direction="io"/>
<pin name="VDD3_REF" direction="io"/>
<pin name="~RESET" direction="io"/>
<pin name="~CS" direction="io"/>
<pin name="SCLK/SCL" direction="io"/>
<pin name="SDIO/SDA" direction="io"/>
<pin name="SDO" direction="io"/>
<pin name="REF_TEST" direction="io"/>
<pin name="~OUT13" direction="io"/>
<pin name="OUT13" direction="io"/>
<pin name="VDD3_OUT[12:13]" direction="io"/>
<pin name="~OUT12" direction="io"/>
<pin name="OUT12" direction="io"/>
<pin name="VDD1.8_OUT[12:13]" direction="io"/>
<pin name="~OUT11" direction="io"/>
<pin name="OUT11" direction="io"/>
<pin name="VDD3_OUT[10:11]" direction="io"/>
<pin name="~OUT10" direction="io"/>
<pin name="OUT10" direction="io"/>
<pin name="VDD1.8_OUT[10:11]" direction="io"/>
<pin name="~OUT9" direction="io"/>
<pin name="OUT9" direction="io"/>
<pin name="VDD3_OUT[8:9]" direction="io"/>
<pin name="~OUT8" direction="io"/>
<pin name="OUT8" direction="io"/>
<pin name="VDD1.8_OUT[8:9]" direction="io"/>
<pin name="~OUT7" direction="io"/>
<pin name="OUT7" direction="io"/>
<pin name="VDD3_OUT[6:7]" direction="io"/>
<pin name="~OUT6" direction="io"/>
<pin name="OUT6" direction="io"/>
<pin name="VDD1.8_OUT[6:7]" direction="io"/>
<pin name="~OUT5" direction="io"/>
<pin name="OUT5" direction="io"/>
<pin name="VDD3_OUT[4:5]" direction="io"/>
<pin name="~OUT4" direction="io"/>
<pin name="OUT4" direction="io"/>
<pin name="VDD1.8_OUT[4:5]" direction="io"/>
<pin name="STATUS1/SPI" direction="io"/>
<pin name="STATUS0/SP0" direction="io"/>
<pin name="EEPROM_SEL" direction="io"/>
<pin name="~OUT3" direction="io"/>
<pin name="OUT3" direction="io"/>
<pin name="VDD3_OUT[2:3]" direction="io"/>
<pin name="~OUT2" direction="io"/>
<pin name="OUT2" direction="io"/>
<pin name="VDD1.8_OUT[0:3]" direction="io"/>
<pin name="~OUT1" direction="io"/>
<pin name="OUT1" direction="io"/>
<pin name="VDD3_OUT[0:1]" direction="io"/>
<pin name="~OUT0" direction="io"/>
<pin name="OUT0" direction="io"/>
<pin name="VDD1.8_PLL2" direction="io"/>
<pin name="ZD_IN" direction="io"/>
<pin name="~ZD_IN" direction="io"/>
<pin name="~PLL_OUT" direction="io"/>
<pin name="EP" direction="io"/>
</symbol>
</symbols>
<devicesets>
<deviceset name="AD9523BCPZ" prefix="IC">
<description>&lt;b&gt;AD9523BCPZ, PLL Clock Driver Dual, 72-Pin LFCSP VQ&lt;/b&gt;&lt;p&gt;
Source: &lt;a href="https://componentsearchengine.com/Datasheets/1/AD9523BCPZ.pdf"&gt; Datasheet &lt;/a&gt;</description>
<gates>
<gate name="G$1" symbol="AD9523BCPZ"/>
</gates>
<devices>
<device name="" package="QFN50P1000X1000X100-73N">
<connects>
<connect gate="G$1" pin="LDO_PLL1" pad="1"/>
<connect gate="G$1" pin="VDD3_PLL1" pad="2"/>
<connect gate="G$1" pin="REFA" pad="3"/>
<connect gate="G$1" pin="~REFA" pad="4"/>
<connect gate="G$1" pin="REFB" pad="5"/>
<connect gate="G$1" pin="~REFB" pad="6"/>
<connect gate="G$1" pin="LF1_EXT_CAP" pad="7"/>
<connect gate="G$1" pin="OSC_CTRL" pad="8"/>
<connect gate="G$1" pin="OSC_IN" pad="9"/>
<connect gate="G$1" pin="~OSC_IN" pad="10"/>
<connect gate="G$1" pin="LF2_EXT_CAP" pad="11"/>
<connect gate="G$1" pin="LDO_PLL2" pad="12"/>
<connect gate="G$1" pin="VDD3_PLL2" pad="13"/>
<connect gate="G$1" pin="LDO_VCO" pad="14"/>
<connect gate="G$1" pin="~PD" pad="15"/>
<connect gate="G$1" pin="REF_SEL" pad="16"/>
<connect gate="G$1" pin="~SYNC" pad="17"/>
<connect gate="G$1" pin="VDD3_REF" pad="18"/>
<connect gate="G$1" pin="~RESET" pad="19"/>
<connect gate="G$1" pin="~CS" pad="20"/>
<connect gate="G$1" pin="SCLK/SCL" pad="21"/>
<connect gate="G$1" pin="SDIO/SDA" pad="22"/>
<connect gate="G$1" pin="SDO" pad="23"/>
<connect gate="G$1" pin="REF_TEST" pad="24"/>
<connect gate="G$1" pin="~OUT13" pad="25"/>
<connect gate="G$1" pin="OUT13" pad="26"/>
<connect gate="G$1" pin="VDD3_OUT[12:13]" pad="27"/>
<connect gate="G$1" pin="~OUT12" pad="28"/>
<connect gate="G$1" pin="OUT12" pad="29"/>
<connect gate="G$1" pin="VDD1.8_OUT[12:13]" pad="30"/>
<connect gate="G$1" pin="~OUT11" pad="31"/>
<connect gate="G$1" pin="OUT11" pad="32"/>
<connect gate="G$1" pin="VDD3_OUT[10:11]" pad="33"/>
<connect gate="G$1" pin="~OUT10" pad="34"/>
<connect gate="G$1" pin="OUT10" pad="35"/>
<connect gate="G$1" pin="VDD1.8_OUT[10:11]" pad="36"/>
<connect gate="G$1" pin="~OUT9" pad="37"/>
<connect gate="G$1" pin="OUT9" pad="38"/>
<connect gate="G$1" pin="VDD3_OUT[8:9]" pad="39"/>
<connect gate="G$1" pin="~OUT8" pad="40"/>
<connect gate="G$1" pin="OUT8" pad="41"/>
<connect gate="G$1" pin="VDD1.8_OUT[8:9]" pad="42"/>
<connect gate="G$1" pin="~OUT7" pad="43"/>
<connect gate="G$1" pin="OUT7" pad="44"/>
<connect gate="G$1" pin="VDD3_OUT[6:7]" pad="45"/>
<connect gate="G$1" pin="~OUT6" pad="46"/>
<connect gate="G$1" pin="OUT6" pad="47"/>
<connect gate="G$1" pin="VDD1.8_OUT[6:7]" pad="48"/>
<connect gate="G$1" pin="~OUT5" pad="49"/>
<connect gate="G$1" pin="OUT5" pad="50"/>
<connect gate="G$1" pin="VDD3_OUT[4:5]" pad="51"/>
<connect gate="G$1" pin="~OUT4" pad="52"/>
<connect gate="G$1" pin="OUT4" pad="53"/>
<connect gate="G$1" pin="VDD1.8_OUT[4:5]" pad="54"/>
<connect gate="G$1" pin="STATUS1/SPI" pad="55"/>
<connect gate="G$1" pin="STATUS0/SP0" pad="56"/>
<connect gate="G$1" pin="EEPROM_SEL" pad="57"/>
<connect gate="G$1" pin="~OUT3" pad="58"/>
<connect gate="G$1" pin="OUT3" pad="59"/>
<connect gate="G$1" pin="VDD3_OUT[2:3]" pad="60"/>
<connect gate="G$1" pin="~OUT2" pad="61"/>
<connect gate="G$1" pin="OUT2" pad="62"/>
<connect gate="G$1" pin="VDD1.8_OUT[0:3]" pad="63"/>
<connect gate="G$1" pin="~OUT1" pad="64"/>
<connect gate="G$1" pin="OUT1" pad="65"/>
<connect gate="G$1" pin="VDD3_OUT[0:1]" pad="66"/>
<connect gate="G$1" pin="~OUT0" pad="67"/>
<connect gate="G$1" pin="OUT0" pad="68"/>
<connect gate="G$1" pin="VDD1.8_PLL2" pad="69"/>
<connect gate="G$1" pin="ZD_IN" pad="70"/>
<connect gate="G$1" pin="~ZD_IN" pad="71"/>
<connect gate="G$1" pin="~PLL_OUT" pad="72"/>
<connect gate="G$1" pin="EP" pad="73"/>
</connects>
<technologies>
<technology name="">
<attribute name="Mouser_Part_Number" value="584-AD9523BCPZ"/>
<attribute name="Mouser_Price-Stock" value="https://www.mouser.com/Search/Refine.aspx?Keyword=584-AD9523BCPZ"/>
<attribute name="Manufacturer_Name" value="Analog Devices"/>
<attribute name="Manufacturer_Part_Number" value="AD9523BCPZ"/>
<attribute name="Description" value="AD9523BCPZ, PLL Clock Driver Dual, 72-Pin LFCSP VQ"/>
<attribute name="Height" value="mm"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
</devicesets>
</library>
</drawing>
</eagle>
