<!--This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License (CC BY-SA) with Design Exception 1.0-->
<eagle version="7.1.0">
<drawing>
<library>
<packages>
<package name="BGA256C100P16X16_1700X1700X155">
</package>
</packages>
<symbols>
<symbol name="XC7A50T-2FTG256I_SECTION1">
<pin name="DONE_0"/>
<pin name="DXP_0"/>
<pin name="GNDADC_0" direction="pwr"/>
<pin name="VCCADC_0" direction="pwr"/>
<pin name="VREFP_0"/>
<pin name="VN_0" direction="in"/>
<pin name="VCCBATT_0" direction="pwr"/>
<pin name="TCK_0" direction="in" function="clk"/>
<pin name="DXN_0"/>
<pin name="VREFN_0"/>
<pin name="VP_0" direction="in"/>
<pin name="CCLK_0" function="clk"/>
<pin name="M0_0" direction="in"/>
<pin name="M1_0" direction="in"/>
<pin name="INIT_B_0"/>
<pin name="TDI_0" direction="in"/>
<pin name="TDO_0" direction="out"/>
<pin name="M2_0" direction="in"/>
<pin name="CFGBVS_0" direction="in"/>
<pin name="PROGRAM_B_0" direction="in"/>
<pin name="TMS_0" direction="in"/>
<pin name="VCCO_0" direction="pwr"/>
<pin name="GND" direction="pwr"/>
<pin name="VCCBRAM" direction="pwr"/>
<pin name="VCCINT" direction="pwr"/>
<pin name="VCCAUX" direction="pwr"/>
</symbol>
<symbol name="XC7A50T-2FTG256I_SECTION2">
<pin name="IO_0_14"/>
<pin name="IO_L1P_T0_D00_MOSI_14"/>
<pin name="IO_L1N_T0_D01_DIN_14"/>
<pin name="IO_L2P_T0_D02_14"/>
<pin name="IO_L2N_T0_D03_14"/>
<pin name="IO_L3P_T0_DQS_PUDC_B_14"/>
<pin name="IO_L3N_T0_DQS_EMCCLK_14"/>
<pin name="IO_L4P_T0_D04_14"/>
<pin name="IO_L4N_T0_D05_14"/>
<pin name="IO_L5P_T0_D06_14"/>
<pin name="IO_L5N_T0_D07_14"/>
<pin name="IO_L6P_T0_FCS_B_14"/>
<pin name="IO_L6N_T0_D08_VREF_14"/>
<pin name="IO_L7P_T1_D09_14"/>
<pin name="IO_L7N_T1_D10_14"/>
<pin name="IO_L8P_T1_D11_14"/>
<pin name="IO_L8N_T1_D12_14"/>
<pin name="IO_L9P_T1_DQS_14"/>
<pin name="IO_L9N_T1_DQS_D13_14"/>
<pin name="IO_L10P_T1_D14_14"/>
<pin name="IO_L10N_T1_D15_14"/>
<pin name="IO_L11P_T1_SRCC_14"/>
<pin name="IO_L11N_T1_SRCC_14"/>
<pin name="IO_L12P_T1_MRCC_14"/>
<pin name="IO_L12N_T1_MRCC_14"/>
<pin name="IO_L13P_T2_MRCC_14"/>
<pin name="IO_L13N_T2_MRCC_14"/>
<pin name="IO_L14P_T2_SRCC_14"/>
<pin name="IO_L14N_T2_SRCC_14"/>
<pin name="IO_L15P_T2_DQS_RDWR_B_14"/>
<pin name="IO_L15N_T2_DQS_DOUT_CSO_B_14"/>
<pin name="IO_L16P_T2_CSI_B_14"/>
<pin name="IO_L16N_T2_A15_D31_14"/>
<pin name="IO_L17P_T2_A14_D30_14"/>
<pin name="IO_L17N_T2_A13_D29_14"/>
<pin name="IO_L18P_T2_A12_D28_14"/>
<pin name="IO_L18N_T2_A11_D27_14"/>
<pin name="IO_L19P_T3_A10_D26_14"/>
<pin name="IO_L19N_T3_A09_D25_VREF_14"/>
<pin name="IO_L20P_T3_A08_D24_14"/>
<pin name="IO_L20N_T3_A07_D23_14"/>
<pin name="IO_L21P_T3_DQS_14"/>
<pin name="IO_L21N_T3_DQS_A06_D22_14"/>
<pin name="IO_L22P_T3_A05_D21_14"/>
<pin name="IO_L22N_T3_A04_D20_14"/>
<pin name="IO_L23P_T3_A03_D19_14"/>
<pin name="IO_L23N_T3_A02_D18_14"/>
<pin name="IO_L24P_T3_A01_D17_14"/>
<pin name="IO_L24N_T3_A00_D16_14"/>
<pin name="IO_25_14"/>
<pin name="VCCO_14" direction="pwr"/>
</symbol>
<symbol name="XC7A50T-2FTG256I_SECTION3">
<pin name="IO_L2P_T0_AD8P_15"/>
<pin name="IO_L2N_T0_AD8N_15"/>
<pin name="IO_L3N_T0_DQS_AD1N_15"/>
<pin name="IO_L5N_T0_AD9N_15"/>
<pin name="IO_L7P_T1_AD2P_15"/>
<pin name="IO_L7N_T1_AD2N_15"/>
<pin name="IO_L9N_T1_DQS_AD3N_15"/>
<pin name="VCCO_15" direction="pwr"/>
<pin name="IO_L3P_T0_DQS_AD1P_15"/>
<pin name="IO_L4P_T0_15"/>
<pin name="IO_L4N_T0_15"/>
<pin name="IO_L5P_T0_AD9P_15"/>
<pin name="IO_L8N_T1_AD10N_15"/>
<pin name="IO_L9P_T1_DQS_AD3P_15"/>
<pin name="IO_L10N_T1_AD11N_15"/>
<pin name="IO_L1P_T0_AD0P_15"/>
<pin name="IO_L1N_T0_AD0N_15"/>
<pin name="IO_L11P_T1_SRCC_15"/>
<pin name="IO_L11N_T1_SRCC_15"/>
<pin name="IO_L12N_T1_MRCC_15"/>
<pin name="IO_L8P_T1_AD10P_15"/>
<pin name="IO_L10P_T1_AD11P_15"/>
<pin name="IO_L6P_T0_15"/>
<pin name="IO_L6N_T0_VREF_15"/>
<pin name="IO_0_15"/>
<pin name="IO_L14N_T2_SRCC_15"/>
<pin name="IO_L12P_T1_MRCC_15"/>
<pin name="IO_L15P_T2_DQS_15"/>
<pin name="IO_L15N_T2_DQS_ADV_B_15"/>
<pin name="IO_L17N_T2_A25_15"/>
<pin name="IO_L14P_T2_SRCC_15"/>
<pin name="IO_L13P_T2_MRCC_15"/>
<pin name="IO_L13N_T2_MRCC_15"/>
<pin name="IO_L18N_T2_A23_15"/>
<pin name="IO_L17P_T2_A26_15"/>
<pin name="IO_L16P_T2_A28_15"/>
<pin name="IO_L16N_T2_A27_15"/>
<pin name="IO_L21N_T3_DQS_A18_15"/>
<pin name="IO_L18P_T2_A24_15"/>
<pin name="IO_25_15"/>
<pin name="IO_L19N_T3_A21_VREF_15"/>
<pin name="IO_L21P_T3_DQS_15"/>
<pin name="IO_L24N_T3_RS0_15"/>
<pin name="IO_L22N_T3_A16_15"/>
<pin name="IO_L19P_T3_A22_15"/>
<pin name="IO_L20P_T3_A20_15"/>
<pin name="IO_L20N_T3_A19_15"/>
<pin name="IO_L24P_T3_RS1_15"/>
<pin name="IO_L22P_T3_A17_15"/>
<pin name="IO_L23P_T3_FOE_B_15"/>
<pin name="IO_L23N_T3_FWE_B_15"/>
</symbol>
<symbol name="XC7A50T-2FTG256I_SECTION4">
<pin name="IO_L1P_T0_34"/>
<pin name="IO_0_34"/>
<pin name="IO_L2N_T0_34"/>
<pin name="IO_L2P_T0_34"/>
<pin name="VCCO_34" direction="pwr"/>
<pin name="IO_L1N_T0_34"/>
<pin name="IO_L6P_T0_34"/>
<pin name="IO_L4P_T0_34"/>
<pin name="IO_L3N_T0_DQS_34"/>
<pin name="IO_L3P_T0_DQS_34"/>
<pin name="IO_L6N_T0_VREF_34"/>
<pin name="IO_L4N_T0_34"/>
<pin name="IO_L5N_T0_34"/>
<pin name="IO_L5P_T0_34"/>
<pin name="IO_L10P_T1_34"/>
<pin name="IO_L7N_T1_34"/>
<pin name="IO_L7P_T1_34"/>
<pin name="IO_L8P_T1_34"/>
<pin name="IO_L8N_T1_34"/>
<pin name="IO_L9N_T1_DQS_34"/>
<pin name="IO_L9P_T1_DQS_34"/>
</symbol>
<symbol name="XC7A50T-2FTG256I_SECTION5">
<pin name="IO_L8N_T1_AD14N_35"/>
<pin name="IO_L4N_T0_35"/>
<pin name="IO_L3N_T0_DQS_AD5N_35"/>
<pin name="IO_L3P_T0_DQS_AD5P_35"/>
<pin name="VCCO_35" direction="pwr"/>
<pin name="IO_L1N_T0_AD4N_35"/>
<pin name="IO_L9N_T1_DQS_AD7N_35"/>
<pin name="IO_L8P_T1_AD14P_35"/>
<pin name="IO_L4P_T0_35"/>
<pin name="IO_L2N_T0_AD12N_35"/>
<pin name="IO_L2P_T0_AD12P_35"/>
<pin name="IO_L1P_T0_AD4P_35"/>
<pin name="IO_L9P_T1_DQS_AD7P_35"/>
<pin name="IO_L7N_T1_AD6N_35"/>
<pin name="IO_L7P_T1_AD6P_35"/>
<pin name="IO_L12N_T1_MRCC_35"/>
<pin name="IO_L5N_T0_AD13N_35"/>
<pin name="IO_L5P_T0_AD13P_35"/>
<pin name="IO_L10N_T1_AD15N_35"/>
<pin name="IO_L11N_T1_SRCC_35"/>
<pin name="IO_L12P_T1_MRCC_35"/>
<pin name="IO_L6N_T0_VREF_35"/>
<pin name="IO_L6P_T0_35"/>
<pin name="IO_L15N_T2_DQS_35"/>
<pin name="IO_L10P_T1_AD15P_35"/>
<pin name="IO_L11P_T1_SRCC_35"/>
<pin name="IO_L13N_T2_MRCC_35"/>
<pin name="IO_0_35"/>
<pin name="IO_L15P_T2_DQS_35"/>
<pin name="IO_L14N_T2_SRCC_35"/>
<pin name="IO_L14P_T2_SRCC_35"/>
<pin name="IO_L13P_T2_MRCC_35"/>
<pin name="IO_L17N_T2_35"/>
<pin name="IO_L17P_T2_35"/>
<pin name="IO_L16N_T2_35"/>
<pin name="IO_L16P_T2_35"/>
<pin name="IO_L20N_T3_35"/>
<pin name="IO_L20P_T3_35"/>
<pin name="IO_L21N_T3_DQS_35"/>
<pin name="IO_L18N_T2_35"/>
<pin name="IO_L18P_T2_35"/>
<pin name="IO_L22N_T3_35"/>
<pin name="IO_L21P_T3_DQS_35"/>
<pin name="IO_L19N_T3_VREF_35"/>
<pin name="IO_L19P_T3_35"/>
<pin name="IO_L22P_T3_35"/>
<pin name="IO_L24N_T3_35"/>
<pin name="IO_L24P_T3_35"/>
<pin name="IO_25_35"/>
<pin name="IO_L23N_T3_35"/>
<pin name="IO_L23P_T3_35"/>
</symbol>
</symbols>
<devicesets>
<deviceset name="XC7A50T-2FTG256I" prefix="U">
<description>Artix-7 Field Programmable Gate Array (FPGA) IC 170 2764800 52160 256-LBGA  &lt;a href="https://pricing.snapeda.com/parts/XC7A50T-2FTG256I/Xilinx%20Inc./view-part?ref=eda"&gt;Check availability&lt;/a&gt;</description>
<gates>
<gate name="G$1" symbol="XC7A50T-2FTG256I_SECTION1"/>
<gate name="G$2" symbol="XC7A50T-2FTG256I_SECTION2"/>
<gate name="G$3" symbol="XC7A50T-2FTG256I_SECTION3"/>
<gate name="G$4" symbol="XC7A50T-2FTG256I_SECTION4"/>
<gate name="G$5" symbol="XC7A50T-2FTG256I_SECTION5"/>
</gates>
<devices>
<device name="" package="BGA256C100P16X16_1700X1700X155">
<connects>
<connect gate="G$1" pin="CCLK_0" pad="E8"/>
<connect gate="G$1" pin="CFGBVS_0" pad="E7"/>
<connect gate="G$1" pin="DONE_0" pad="H10"/>
<connect gate="G$1" pin="DXN_0" pad="K7"/>
<connect gate="G$1" pin="DXP_0" pad="K8"/>
<connect gate="G$1" pin="GND" pad="A1 A11 B8 C5 C15 D2 D12 E9 F6 F10 F16 G3 G9 G13 H6 J9 J11 K4 K6 K14 L1 L11 M8 N5 N15 P2 P12 R9 T6 T16"/>
<connect gate="G$1" pin="GNDADC_0" pad="G7"/>
<connect gate="G$1" pin="INIT_B_0" pad="K10"/>
<connect gate="G$1" pin="M0_0" pad="M9"/>
<connect gate="G$1" pin="M1_0" pad="M10"/>
<connect gate="G$1" pin="M2_0" pad="M11"/>
<connect gate="G$1" pin="PROGRAM_B_0" pad="L9"/>
<connect gate="G$1" pin="TCK_0" pad="L7"/>
<connect gate="G$1" pin="TDI_0" pad="N7"/>
<connect gate="G$1" pin="TDO_0" pad="N8"/>
<connect gate="G$1" pin="TMS_0" pad="M7"/>
<connect gate="G$1" pin="VCCADC_0" pad="G8"/>
<connect gate="G$1" pin="VCCAUX" pad="G10 J10 K11 L10"/>
<connect gate="G$1" pin="VCCBATT_0" pad="F8"/>
<connect gate="G$1" pin="VCCBRAM" pad="E10 F11"/>
<connect gate="G$1" pin="VCCINT" pad="F7 F9 G6 H9 J6 K9 L8"/>
<connect gate="G$1" pin="VCCO_0" pad="L6"/>
<connect gate="G$1" pin="VN_0" pad="J7"/>
<connect gate="G$1" pin="VP_0" pad="H8"/>
<connect gate="G$1" pin="VREFN_0" pad="H7"/>
<connect gate="G$1" pin="VREFP_0" pad="J8"/>
<connect gate="G$2" pin="IO_0_14" pad="K12"/>
<connect gate="G$2" pin="IO_25_14" pad="P6"/>
<connect gate="G$2" pin="IO_L10N_T1_D15_14" pad="T15"/>
<connect gate="G$2" pin="IO_L10P_T1_D14_14" pad="T14"/>
<connect gate="G$2" pin="IO_L11N_T1_SRCC_14" pad="P13"/>
<connect gate="G$2" pin="IO_L11P_T1_SRCC_14" pad="N13"/>
<connect gate="G$2" pin="IO_L12N_T1_MRCC_14" pad="P14"/>
<connect gate="G$2" pin="IO_L12P_T1_MRCC_14" pad="N14"/>
<connect gate="G$2" pin="IO_L13N_T2_MRCC_14" pad="N12"/>
<connect gate="G$2" pin="IO_L13P_T2_MRCC_14" pad="N11"/>
<connect gate="G$2" pin="IO_L14N_T2_SRCC_14" pad="P11"/>
<connect gate="G$2" pin="IO_L14P_T2_SRCC_14" pad="P10"/>
<connect gate="G$2" pin="IO_L15N_T2_DQS_DOUT_CSO_B_14" pad="T12"/>
<connect gate="G$2" pin="IO_L15P_T2_DQS_RDWR_B_14" pad="R12"/>
<connect gate="G$2" pin="IO_L16N_T2_A15_D31_14" pad="T13"/>
<connect gate="G$2" pin="IO_L16P_T2_CSI_B_14" pad="R13"/>
<connect gate="G$2" pin="IO_L17N_T2_A13_D29_14" pad="R11"/>
<connect gate="G$2" pin="IO_L17P_T2_A14_D30_14" pad="R10"/>
<connect gate="G$2" pin="IO_L18N_T2_A11_D27_14" pad="P9"/>
<connect gate="G$2" pin="IO_L18P_T2_A12_D28_14" pad="N9"/>
<connect gate="G$2" pin="IO_L19N_T3_A09_D25_VREF_14" pad="N6"/>
<connect gate="G$2" pin="IO_L19P_T3_A10_D26_14" pad="M6"/>
<connect gate="G$2" pin="IO_L1N_T0_D01_DIN_14" pad="J14"/>
<connect gate="G$2" pin="IO_L1P_T0_D00_MOSI_14" pad="J13"/>
<connect gate="G$2" pin="IO_L20N_T3_A07_D23_14" pad="R8"/>
<connect gate="G$2" pin="IO_L20P_T3_A08_D24_14" pad="P8"/>
<connect gate="G$2" pin="IO_L21N_T3_DQS_A06_D22_14" pad="T8"/>
<connect gate="G$2" pin="IO_L21P_T3_DQS_14" pad="T7"/>
<connect gate="G$2" pin="IO_L22N_T3_A04_D20_14" pad="T10"/>
<connect gate="G$2" pin="IO_L22P_T3_A05_D21_14" pad="T9"/>
<connect gate="G$2" pin="IO_L23N_T3_A02_D18_14" pad="T5"/>
<connect gate="G$2" pin="IO_L23P_T3_A03_D19_14" pad="R5"/>
<connect gate="G$2" pin="IO_L24N_T3_A00_D16_14" pad="R7"/>
<connect gate="G$2" pin="IO_L24P_T3_A01_D17_14" pad="R6"/>
<connect gate="G$2" pin="IO_L2N_T0_D03_14" pad="K16"/>
<connect gate="G$2" pin="IO_L2P_T0_D02_14" pad="K15"/>
<connect gate="G$2" pin="IO_L3N_T0_DQS_EMCCLK_14" pad="M15"/>
<connect gate="G$2" pin="IO_L3P_T0_DQS_PUDC_B_14" pad="L15"/>
<connect gate="G$2" pin="IO_L4N_T0_D05_14" pad="M14"/>
<connect gate="G$2" pin="IO_L4P_T0_D04_14" pad="L14"/>
<connect gate="G$2" pin="IO_L5N_T0_D07_14" pad="L13"/>
<connect gate="G$2" pin="IO_L5P_T0_D06_14" pad="K13"/>
<connect gate="G$2" pin="IO_L6N_T0_D08_VREF_14" pad="M12"/>
<connect gate="G$2" pin="IO_L6P_T0_FCS_B_14" pad="L12"/>
<connect gate="G$2" pin="IO_L7N_T1_D10_14" pad="N16"/>
<connect gate="G$2" pin="IO_L7P_T1_D09_14" pad="M16"/>
<connect gate="G$2" pin="IO_L8N_T1_D12_14" pad="P16"/>
<connect gate="G$2" pin="IO_L8P_T1_D11_14" pad="P15"/>
<connect gate="G$2" pin="IO_L9N_T1_DQS_D13_14" pad="R16"/>
<connect gate="G$2" pin="IO_L9P_T1_DQS_14" pad="R15"/>
<connect gate="G$2" pin="VCCO_14" pad="L16 M13 N10 P7 R14 T11"/>
<connect gate="G$3" pin="IO_0_15" pad="D10"/>
<connect gate="G$3" pin="IO_25_15" pad="G11"/>
<connect gate="G$3" pin="IO_L10N_T1_AD11N_15" pad="B16"/>
<connect gate="G$3" pin="IO_L10P_T1_AD11P_15" pad="C16"/>
<connect gate="G$3" pin="IO_L11N_T1_SRCC_15" pad="C12"/>
<connect gate="G$3" pin="IO_L11P_T1_SRCC_15" pad="C11"/>
<connect gate="G$3" pin="IO_L12N_T1_MRCC_15" pad="C13"/>
<connect gate="G$3" pin="IO_L12P_T1_MRCC_15" pad="D13"/>
<connect gate="G$3" pin="IO_L13N_T2_MRCC_15" pad="E13"/>
<connect gate="G$3" pin="IO_L13P_T2_MRCC_15" pad="E12"/>
<connect gate="G$3" pin="IO_L14N_T2_SRCC_15" pad="D11"/>
<connect gate="G$3" pin="IO_L14P_T2_SRCC_15" pad="E11"/>
<connect gate="G$3" pin="IO_L15N_T2_DQS_ADV_B_15" pad="D15"/>
<connect gate="G$3" pin="IO_L15P_T2_DQS_15" pad="D14"/>
<connect gate="G$3" pin="IO_L16N_T2_A27_15" pad="F13"/>
<connect gate="G$3" pin="IO_L16P_T2_A28_15" pad="F12"/>
<connect gate="G$3" pin="IO_L17N_T2_A25_15" pad="D16"/>
<connect gate="G$3" pin="IO_L17P_T2_A26_15" pad="E16"/>
<connect gate="G$3" pin="IO_L18N_T2_A23_15" pad="E15"/>
<connect gate="G$3" pin="IO_L18P_T2_A24_15" pad="F15"/>
<connect gate="G$3" pin="IO_L19N_T3_A21_VREF_15" pad="G12"/>
<connect gate="G$3" pin="IO_L19P_T3_A22_15" pad="H11"/>
<connect gate="G$3" pin="IO_L1N_T0_AD0N_15" pad="C9"/>
<connect gate="G$3" pin="IO_L1P_T0_AD0P_15" pad="C8"/>
<connect gate="G$3" pin="IO_L20N_T3_A19_15" pad="H13"/>
<connect gate="G$3" pin="IO_L20P_T3_A20_15" pad="H12"/>
<connect gate="G$3" pin="IO_L21N_T3_DQS_A18_15" pad="F14"/>
<connect gate="G$3" pin="IO_L21P_T3_DQS_15" pad="G14"/>
<connect gate="G$3" pin="IO_L22N_T3_A16_15" pad="G16"/>
<connect gate="G$3" pin="IO_L22P_T3_A17_15" pad="H16"/>
<connect gate="G$3" pin="IO_L23N_T3_FWE_B_15" pad="J16"/>
<connect gate="G$3" pin="IO_L23P_T3_FOE_B_15" pad="J15"/>
<connect gate="G$3" pin="IO_L24N_T3_RS0_15" pad="G15"/>
<connect gate="G$3" pin="IO_L24P_T3_RS1_15" pad="H14"/>
<connect gate="G$3" pin="IO_L2N_T0_AD8N_15" pad="A9"/>
<connect gate="G$3" pin="IO_L2P_T0_AD8P_15" pad="A8"/>
<connect gate="G$3" pin="IO_L3N_T0_DQS_AD1N_15" pad="A10"/>
<connect gate="G$3" pin="IO_L3P_T0_DQS_AD1P_15" pad="B9"/>
<connect gate="G$3" pin="IO_L4N_T0_15" pad="B11"/>
<connect gate="G$3" pin="IO_L4P_T0_15" pad="B10"/>
<connect gate="G$3" pin="IO_L5N_T0_AD9N_15" pad="A12"/>
<connect gate="G$3" pin="IO_L5P_T0_AD9P_15" pad="B12"/>
<connect gate="G$3" pin="IO_L6N_T0_VREF_15" pad="D9"/>
<connect gate="G$3" pin="IO_L6P_T0_15" pad="D8"/>
<connect gate="G$3" pin="IO_L7N_T1_AD2N_15" pad="A14"/>
<connect gate="G$3" pin="IO_L7P_T1_AD2P_15" pad="A13"/>
<connect gate="G$3" pin="IO_L8N_T1_AD10N_15" pad="B14"/>
<connect gate="G$3" pin="IO_L8P_T1_AD10P_15" pad="C14"/>
<connect gate="G$3" pin="IO_L9N_T1_DQS_AD3N_15" pad="A15"/>
<connect gate="G$3" pin="IO_L9P_T1_DQS_AD3P_15" pad="B15"/>
<connect gate="G$3" pin="VCCO_15" pad="A16 B13 C10 E14 H15 J12"/>
<connect gate="G$4" pin="IO_0_34" pad="L5"/>
<connect gate="G$4" pin="IO_L10P_T1_34" pad="P5"/>
<connect gate="G$4" pin="IO_L1N_T0_34" pad="M4"/>
<connect gate="G$4" pin="IO_L1P_T0_34" pad="L4"/>
<connect gate="G$4" pin="IO_L2N_T0_34" pad="M1"/>
<connect gate="G$4" pin="IO_L2P_T0_34" pad="M2"/>
<connect gate="G$4" pin="IO_L3N_T0_DQS_34" pad="N2"/>
<connect gate="G$4" pin="IO_L3P_T0_DQS_34" pad="N3"/>
<connect gate="G$4" pin="IO_L4N_T0_34" pad="P1"/>
<connect gate="G$4" pin="IO_L4P_T0_34" pad="N1"/>
<connect gate="G$4" pin="IO_L5N_T0_34" pad="P3"/>
<connect gate="G$4" pin="IO_L5P_T0_34" pad="P4"/>
<connect gate="G$4" pin="IO_L6N_T0_VREF_34" pad="N4"/>
<connect gate="G$4" pin="IO_L6P_T0_34" pad="M5"/>
<connect gate="G$4" pin="IO_L7N_T1_34" pad="R1"/>
<connect gate="G$4" pin="IO_L7P_T1_34" pad="R2"/>
<connect gate="G$4" pin="IO_L8N_T1_34" pad="T2"/>
<connect gate="G$4" pin="IO_L8P_T1_34" pad="R3"/>
<connect gate="G$4" pin="IO_L9N_T1_DQS_34" pad="T3"/>
<connect gate="G$4" pin="IO_L9P_T1_DQS_34" pad="T4"/>
<connect gate="G$4" pin="VCCO_34" pad="M3 R4 T1"/>
<connect gate="G$5" pin="IO_0_35" pad="E6"/>
<connect gate="G$5" pin="IO_25_35" pad="K5"/>
<connect gate="G$5" pin="IO_L10N_T1_AD15N_35" pad="D1"/>
<connect gate="G$5" pin="IO_L10P_T1_AD15P_35" pad="E2"/>
<connect gate="G$5" pin="IO_L11N_T1_SRCC_35" pad="D3"/>
<connect gate="G$5" pin="IO_L11P_T1_SRCC_35" pad="E3"/>
<connect gate="G$5" pin="IO_L12N_T1_MRCC_35" pad="C4"/>
<connect gate="G$5" pin="IO_L12P_T1_MRCC_35" pad="D4"/>
<connect gate="G$5" pin="IO_L13N_T2_MRCC_35" pad="E5"/>
<connect gate="G$5" pin="IO_L13P_T2_MRCC_35" pad="F5"/>
<connect gate="G$5" pin="IO_L14N_T2_SRCC_35" pad="F3"/>
<connect gate="G$5" pin="IO_L14P_T2_SRCC_35" pad="F4"/>
<connect gate="G$5" pin="IO_L15N_T2_DQS_35" pad="E1"/>
<connect gate="G$5" pin="IO_L15P_T2_DQS_35" pad="F2"/>
<connect gate="G$5" pin="IO_L16N_T2_35" pad="G4"/>
<connect gate="G$5" pin="IO_L16P_T2_35" pad="G5"/>
<connect gate="G$5" pin="IO_L17N_T2_35" pad="G1"/>
<connect gate="G$5" pin="IO_L17P_T2_35" pad="G2"/>
<connect gate="G$5" pin="IO_L18N_T2_35" pad="H4"/>
<connect gate="G$5" pin="IO_L18P_T2_35" pad="H5"/>
<connect gate="G$5" pin="IO_L19N_T3_VREF_35" pad="J4"/>
<connect gate="G$5" pin="IO_L19P_T3_35" pad="J5"/>
<connect gate="G$5" pin="IO_L1N_T0_AD4N_35" pad="A7"/>
<connect gate="G$5" pin="IO_L1P_T0_AD4P_35" pad="B7"/>
<connect gate="G$5" pin="IO_L20N_T3_35" pad="H1"/>
<connect gate="G$5" pin="IO_L20P_T3_35" pad="H2"/>
<connect gate="G$5" pin="IO_L21N_T3_DQS_35" pad="H3"/>
<connect gate="G$5" pin="IO_L21P_T3_DQS_35" pad="J3"/>
<connect gate="G$5" pin="IO_L22N_T3_35" pad="J1"/>
<connect gate="G$5" pin="IO_L22P_T3_35" pad="K1"/>
<connect gate="G$5" pin="IO_L23N_T3_35" pad="L2"/>
<connect gate="G$5" pin="IO_L23P_T3_35" pad="L3"/>
<connect gate="G$5" pin="IO_L24N_T3_35" pad="K2"/>
<connect gate="G$5" pin="IO_L24P_T3_35" pad="K3"/>
<connect gate="G$5" pin="IO_L2N_T0_AD12N_35" pad="B5"/>
<connect gate="G$5" pin="IO_L2P_T0_AD12P_35" pad="B6"/>
<connect gate="G$5" pin="IO_L3N_T0_DQS_AD5N_35" pad="A4"/>
<connect gate="G$5" pin="IO_L3P_T0_DQS_AD5P_35" pad="A5"/>
<connect gate="G$5" pin="IO_L4N_T0_35" pad="A3"/>
<connect gate="G$5" pin="IO_L4P_T0_35" pad="B4"/>
<connect gate="G$5" pin="IO_L5N_T0_AD13N_35" pad="C6"/>
<connect gate="G$5" pin="IO_L5P_T0_AD13P_35" pad="C7"/>
<connect gate="G$5" pin="IO_L6N_T0_VREF_35" pad="D5"/>
<connect gate="G$5" pin="IO_L6P_T0_35" pad="D6"/>
<connect gate="G$5" pin="IO_L7N_T1_AD6N_35" pad="C2"/>
<connect gate="G$5" pin="IO_L7P_T1_AD6P_35" pad="C3"/>
<connect gate="G$5" pin="IO_L8N_T1_AD14N_35" pad="A2"/>
<connect gate="G$5" pin="IO_L8P_T1_AD14P_35" pad="B2"/>
<connect gate="G$5" pin="IO_L9N_T1_DQS_AD7N_35" pad="B1"/>
<connect gate="G$5" pin="IO_L9P_T1_DQS_AD7P_35" pad="C1"/>
<connect gate="G$5" pin="VCCO_35" pad="A6 B3 D7 E4 F1 J2"/>
</connects>
<technologies>
<technology name="">
<attribute name="MF" value="Xilinx Inc."/>
<attribute name="Description" value="
                        
                            Artix-7 Field Programmable Gate Array (FPGA) IC 170 2764800 52160 256-LBGA
                        
                    "/>
<attribute name="Package" value="LBGA-256 Xilinx Inc."/>
<attribute name="Price" value="None"/>
<attribute name="SnapEDA_Link" value="https://www.snapeda.com/parts/XC7A50T-2FTG256I/Xilinx/view-part/?ref=snap"/>
<attribute name="MP" value="XC7A50T-2FTG256I"/>
<attribute name="Availability" value="In Stock"/>
<attribute name="Check_prices" value="https://www.snapeda.com/parts/XC7A50T-2FTG256I/Xilinx/view-part/?ref=eda"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
</devicesets>
</library>
</drawing>
</eagle>
