<!--This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License (CC BY-SA) with Design Exception 1.0-->
<eagle version="7.1.0">
<drawing>
<library>
<packages>
<package name="BGA236C50P19X19_1000X1000X138N">
</package>
</packages>
<symbols>
<symbol name="XC7A50T-2CPG236I_SECTION1">
<pin name="DONE_0"/>
<pin name="DXP_0"/>
<pin name="GNDADC_0" direction="pwr"/>
<pin name="VCCADC_0" direction="pwr"/>
<pin name="VREFP_0"/>
<pin name="VN_0" direction="in"/>
<pin name="VCCBATT_0" direction="pwr"/>
<pin name="TCK_0" direction="in" function="clk"/>
<pin name="DXN_0"/>
<pin name="VREFN_0"/>
<pin name="VP_0" direction="in"/>
<pin name="CCLK_0" function="clk"/>
<pin name="M0_0" direction="in"/>
<pin name="M1_0" direction="in"/>
<pin name="INIT_B_0"/>
<pin name="TDI_0" direction="in"/>
<pin name="TDO_0" direction="out"/>
<pin name="M2_0" direction="in"/>
<pin name="CFGBVS_0" direction="in"/>
<pin name="PROGRAM_B_0" direction="in"/>
<pin name="TMS_0" direction="in"/>
<pin name="VCCO_0" direction="pwr"/>
</symbol>
<symbol name="XC7A50T-2CPG236I_SECTION2">
<pin name="IO_0_14"/>
<pin name="IO_L1P_T0_D00_MOSI_14"/>
<pin name="IO_L1N_T0_D01_DIN_14"/>
<pin name="IO_L2P_T0_D02_14"/>
<pin name="IO_L2N_T0_D03_14"/>
<pin name="IO_L3P_T0_DQS_PUDC_B_14"/>
<pin name="IO_L3N_T0_DQS_EMCCLK_14"/>
<pin name="IO_L4P_T0_D04_14"/>
<pin name="IO_L4N_T0_D05_14"/>
<pin name="IO_L5P_T0_D06_14"/>
<pin name="IO_L5N_T0_D07_14"/>
<pin name="IO_L6P_T0_FCS_B_14"/>
<pin name="IO_L6N_T0_D08_VREF_14"/>
<pin name="IO_L7P_T1_D09_14"/>
<pin name="IO_L7N_T1_D10_14"/>
<pin name="IO_L8P_T1_D11_14"/>
<pin name="IO_L8N_T1_D12_14"/>
<pin name="IO_L9P_T1_DQS_14"/>
<pin name="IO_L9N_T1_DQS_D13_14"/>
<pin name="IO_L10P_T1_D14_14"/>
<pin name="IO_L10N_T1_D15_14"/>
<pin name="IO_L11P_T1_SRCC_14"/>
<pin name="IO_L11N_T1_SRCC_14"/>
<pin name="IO_L12P_T1_MRCC_14"/>
<pin name="IO_L12N_T1_MRCC_14"/>
<pin name="IO_L13P_T2_MRCC_14"/>
<pin name="IO_L13N_T2_MRCC_14"/>
<pin name="IO_L14P_T2_SRCC_14"/>
<pin name="IO_L14N_T2_SRCC_14"/>
<pin name="IO_L15P_T2_DQS_RDWR_B_14"/>
<pin name="IO_L15N_T2_DQS_DOUT_CSO_B_14"/>
<pin name="IO_L16P_T2_CSI_B_14"/>
<pin name="IO_L16N_T2_A15_D31_14"/>
<pin name="IO_L17P_T2_A14_D30_14"/>
<pin name="IO_L17N_T2_A13_D29_14"/>
<pin name="IO_L18P_T2_A12_D28_14"/>
<pin name="IO_L18N_T2_A11_D27_14"/>
<pin name="IO_L19P_T3_A10_D26_14"/>
<pin name="IO_L19N_T3_A09_D25_VREF_14"/>
<pin name="IO_L20P_T3_A08_D24_14"/>
<pin name="IO_L20N_T3_A07_D23_14"/>
<pin name="IO_L21P_T3_DQS_14"/>
<pin name="IO_L21N_T3_DQS_A06_D22_14"/>
<pin name="IO_L22P_T3_A05_D21_14"/>
<pin name="IO_L22N_T3_A04_D20_14"/>
<pin name="IO_L23P_T3_A03_D19_14"/>
<pin name="IO_L23N_T3_A02_D18_14"/>
<pin name="IO_L24P_T3_A01_D17_14"/>
<pin name="IO_L24N_T3_A00_D16_14"/>
<pin name="IO_25_14"/>
<pin name="VCCO_14" direction="pwr"/>
</symbol>
<symbol name="XC7A50T-2CPG236I_SECTION3">
<pin name="IO_L1P_T0_34"/>
<pin name="IO_L1N_T0_34"/>
<pin name="IO_L2P_T0_34"/>
<pin name="IO_L2N_T0_34"/>
<pin name="IO_L3P_T0_DQS_34"/>
<pin name="IO_L3N_T0_DQS_34"/>
<pin name="IO_L5P_T0_34"/>
<pin name="IO_L5N_T0_34"/>
<pin name="IO_L6P_T0_34"/>
<pin name="IO_L6N_T0_VREF_34"/>
<pin name="IO_L9P_T1_DQS_34"/>
<pin name="IO_L9N_T1_DQS_34"/>
<pin name="IO_L11P_T1_SRCC_34"/>
<pin name="IO_L11N_T1_SRCC_34"/>
<pin name="IO_L12P_T1_MRCC_34"/>
<pin name="IO_L12N_T1_MRCC_34"/>
<pin name="IO_L13P_T2_MRCC_34"/>
<pin name="IO_L13N_T2_MRCC_34"/>
<pin name="IO_L14P_T2_SRCC_34"/>
<pin name="IO_L14N_T2_SRCC_34"/>
<pin name="IO_L16P_T2_34"/>
<pin name="IO_L16N_T2_34"/>
<pin name="IO_L19P_T3_34"/>
<pin name="IO_L19N_T3_VREF_34"/>
<pin name="VCCO_34" direction="pwr"/>
</symbol>
<symbol name="XC7A50T-2CPG236I_SECTION4">
<pin name="IO_L1P_T0_AD4P_35"/>
<pin name="IO_L1N_T0_AD4N_35"/>
<pin name="IO_L2P_T0_AD12P_35"/>
<pin name="IO_L2N_T0_AD12N_35"/>
<pin name="IO_L3P_T0_DQS_AD5P_35"/>
<pin name="IO_L3N_T0_DQS_AD5N_35"/>
<pin name="IO_L5P_T0_AD13P_35"/>
<pin name="IO_L5N_T0_AD13N_35"/>
<pin name="IO_L6N_T0_VREF_35"/>
<pin name="IO_L7P_T1_AD6P_35"/>
<pin name="IO_L7N_T1_AD6N_35"/>
<pin name="IO_L8P_T1_AD14P_35"/>
<pin name="IO_L8N_T1_AD14N_35"/>
<pin name="IO_L9P_T1_DQS_AD7P_35"/>
<pin name="IO_L9N_T1_DQS_AD7N_35"/>
<pin name="IO_L10P_T1_AD15P_35"/>
<pin name="IO_L10N_T1_AD15N_35"/>
<pin name="IO_L12P_T1_MRCC_35"/>
<pin name="IO_L12N_T1_MRCC_35"/>
<pin name="IO_L19N_T3_VREF_35"/>
<pin name="VCCO_35" direction="pwr"/>
</symbol>
<symbol name="XC7A50T-2CPG236I_SECTION5">
<pin name="IO_L6P_T0_16"/>
<pin name="IO_L6N_T0_VREF_16"/>
<pin name="IO_L11P_T1_SRCC_16"/>
<pin name="IO_L11N_T1_SRCC_16"/>
<pin name="IO_L12P_T1_MRCC_16"/>
<pin name="IO_L12N_T1_MRCC_16"/>
<pin name="IO_L13P_T2_MRCC_16"/>
<pin name="IO_L13N_T2_MRCC_16"/>
<pin name="IO_L14P_T2_SRCC_16"/>
<pin name="IO_L14N_T2_SRCC_16"/>
<pin name="IO_L19P_T3_16"/>
<pin name="IO_L19N_T3_VREF_16"/>
<pin name="VCCO_16" direction="pwr"/>
</symbol>
<symbol name="XC7A50T-2CPG236I_SECTION6">
<pin name="MGTRREF_216"/>
<pin name="MGTREFCLK0N_216"/>
<pin name="MGTREFCLK0P_216"/>
<pin name="MGTPRXP1_216"/>
<pin name="MGTPRXP0_216"/>
<pin name="MGTREFCLK1P_216"/>
<pin name="MGTREFCLK1N_216"/>
<pin name="MGTPRXN1_216"/>
<pin name="MGTPRXN0_216"/>
<pin name="MGTPTXP1_216"/>
<pin name="MGTPTXN1_216"/>
<pin name="MGTPTXP0_216"/>
<pin name="MGTPTXN0_216"/>
</symbol>
<symbol name="XC7A50T-2CPG236I_SECTION7">
<pin name="VCCBRAM" direction="pwr"/>
<pin name="VCCINT" direction="pwr"/>
<pin name="MGTAVCC" direction="pwr"/>
<pin name="VCCAUX" direction="pwr"/>
<pin name="MGTAVTT" direction="pwr"/>
<pin name="GND" direction="pwr"/>
</symbol>
</symbols>
<devicesets>
<deviceset name="XC7A50T-2CPG236I" prefix="U">
<description>FPGA Artix-7 Family 52160 Cells 28nm Technology 1V 236-Pin CSBGA &lt;a href="https://pricing.snapeda.com/parts/XC7A50T-2CPG236I/Xilinx%20Inc./view-part?ref=eda"&gt;Check availability&lt;/a&gt;</description>
<gates>
<gate name="G$1" symbol="XC7A50T-2CPG236I_SECTION1"/>
<gate name="G$2" symbol="XC7A50T-2CPG236I_SECTION2"/>
<gate name="G$3" symbol="XC7A50T-2CPG236I_SECTION3"/>
<gate name="G$4" symbol="XC7A50T-2CPG236I_SECTION4"/>
<gate name="G$5" symbol="XC7A50T-2CPG236I_SECTION5"/>
<gate name="G$6" symbol="XC7A50T-2CPG236I_SECTION6"/>
<gate name="G$7" symbol="XC7A50T-2CPG236I_SECTION7"/>
</gates>
<devices>
<device name="" package="BGA236C50P19X19_1000X1000X138N">
<connects>
<connect gate="G$1" pin="CCLK_0" pad="C11"/>
<connect gate="G$1" pin="CFGBVS_0" pad="V11"/>
<connect gate="G$1" pin="DONE_0" pad="U12"/>
<connect gate="G$1" pin="DXN_0" pad="B11"/>
<connect gate="G$1" pin="DXP_0" pad="A11"/>
<connect gate="G$1" pin="GNDADC_0" pad="C12"/>
<connect gate="G$1" pin="INIT_B_0" pad="U11"/>
<connect gate="G$1" pin="M0_0" pad="V12"/>
<connect gate="G$1" pin="M1_0" pad="W11"/>
<connect gate="G$1" pin="M2_0" pad="U10"/>
<connect gate="G$1" pin="PROGRAM_B_0" pad="V10"/>
<connect gate="G$1" pin="TCK_0" pad="C8"/>
<connect gate="G$1" pin="TDI_0" pad="W10"/>
<connect gate="G$1" pin="TDO_0" pad="W8"/>
<connect gate="G$1" pin="TMS_0" pad="W9"/>
<connect gate="G$1" pin="VCCADC_0" pad="C13"/>
<connect gate="G$1" pin="VCCBATT_0" pad="C9"/>
<connect gate="G$1" pin="VCCO_0" pad="G12 V9"/>
<connect gate="G$1" pin="VN_0" pad="B13"/>
<connect gate="G$1" pin="VP_0" pad="A12"/>
<connect gate="G$1" pin="VREFN_0" pad="A13"/>
<connect gate="G$1" pin="VREFP_0" pad="B12"/>
<connect gate="G$2" pin="IO_0_14" pad="D17"/>
<connect gate="G$2" pin="IO_25_14" pad="U14"/>
<connect gate="G$2" pin="IO_L10N_T1_D15_14" pad="R19"/>
<connect gate="G$2" pin="IO_L10P_T1_D14_14" pad="P19"/>
<connect gate="G$2" pin="IO_L11N_T1_SRCC_14" pad="M19"/>
<connect gate="G$2" pin="IO_L11P_T1_SRCC_14" pad="M18"/>
<connect gate="G$2" pin="IO_L12N_T1_MRCC_14" pad="K17"/>
<connect gate="G$2" pin="IO_L12P_T1_MRCC_14" pad="L17"/>
<connect gate="G$2" pin="IO_L13N_T2_MRCC_14" pad="P17"/>
<connect gate="G$2" pin="IO_L13P_T2_MRCC_14" pad="N17"/>
<connect gate="G$2" pin="IO_L14N_T2_SRCC_14" pad="R18"/>
<connect gate="G$2" pin="IO_L14P_T2_SRCC_14" pad="P18"/>
<connect gate="G$2" pin="IO_L15N_T2_DQS_DOUT_CSO_B_14" pad="V19"/>
<connect gate="G$2" pin="IO_L15P_T2_DQS_RDWR_B_14" pad="U19"/>
<connect gate="G$2" pin="IO_L16N_T2_A15_D31_14" pad="W19"/>
<connect gate="G$2" pin="IO_L16P_T2_CSI_B_14" pad="W18"/>
<connect gate="G$2" pin="IO_L17N_T2_A13_D29_14" pad="T18"/>
<connect gate="G$2" pin="IO_L17P_T2_A14_D30_14" pad="T17"/>
<connect gate="G$2" pin="IO_L18N_T2_A11_D27_14" pad="U18"/>
<connect gate="G$2" pin="IO_L18P_T2_A12_D28_14" pad="U17"/>
<connect gate="G$2" pin="IO_L19N_T3_A09_D25_VREF_14" pad="V17"/>
<connect gate="G$2" pin="IO_L19P_T3_A10_D26_14" pad="V16"/>
<connect gate="G$2" pin="IO_L1N_T0_D01_DIN_14" pad="D19"/>
<connect gate="G$2" pin="IO_L1P_T0_D00_MOSI_14" pad="D18"/>
<connect gate="G$2" pin="IO_L20N_T3_A07_D23_14" pad="W17"/>
<connect gate="G$2" pin="IO_L20P_T3_A08_D24_14" pad="W16"/>
<connect gate="G$2" pin="IO_L21N_T3_DQS_A06_D22_14" pad="W15"/>
<connect gate="G$2" pin="IO_L21P_T3_DQS_14" pad="V15"/>
<connect gate="G$2" pin="IO_L22N_T3_A04_D20_14" pad="W14"/>
<connect gate="G$2" pin="IO_L22P_T3_A05_D21_14" pad="W13"/>
<connect gate="G$2" pin="IO_L23N_T3_A02_D18_14" pad="U16"/>
<connect gate="G$2" pin="IO_L23P_T3_A03_D19_14" pad="U15"/>
<connect gate="G$2" pin="IO_L24N_T3_A00_D16_14" pad="V14"/>
<connect gate="G$2" pin="IO_L24P_T3_A01_D17_14" pad="V13"/>
<connect gate="G$2" pin="IO_L2N_T0_D03_14" pad="F18"/>
<connect gate="G$2" pin="IO_L2P_T0_D02_14" pad="G18"/>
<connect gate="G$2" pin="IO_L3N_T0_DQS_EMCCLK_14" pad="E19"/>
<connect gate="G$2" pin="IO_L3P_T0_DQS_PUDC_B_14" pad="E18"/>
<connect gate="G$2" pin="IO_L4N_T0_D05_14" pad="G19"/>
<connect gate="G$2" pin="IO_L4P_T0_D04_14" pad="H19"/>
<connect gate="G$2" pin="IO_L5N_T0_D07_14" pad="G17"/>
<connect gate="G$2" pin="IO_L5P_T0_D06_14" pad="H17"/>
<connect gate="G$2" pin="IO_L6N_T0_D08_VREF_14" pad="J19"/>
<connect gate="G$2" pin="IO_L6P_T0_FCS_B_14" pad="K19"/>
<connect gate="G$2" pin="IO_L7N_T1_D10_14" pad="J18"/>
<connect gate="G$2" pin="IO_L7P_T1_D09_14" pad="J17"/>
<connect gate="G$2" pin="IO_L8N_T1_D12_14" pad="K18"/>
<connect gate="G$2" pin="IO_L8P_T1_D11_14" pad="L18"/>
<connect gate="G$2" pin="IO_L9N_T1_DQS_D13_14" pad="N19"/>
<connect gate="G$2" pin="IO_L9P_T1_DQS_14" pad="N18"/>
<connect gate="G$2" pin="VCCO_14" pad="F17 K12 K13 L12 L13 M12 M17 R17 U13"/>
<connect gate="G$3" pin="IO_L11N_T1_SRCC_34" pad="V4"/>
<connect gate="G$3" pin="IO_L11P_T1_SRCC_34" pad="U4"/>
<connect gate="G$3" pin="IO_L12N_T1_MRCC_34" pad="W4"/>
<connect gate="G$3" pin="IO_L12P_T1_MRCC_34" pad="W5"/>
<connect gate="G$3" pin="IO_L13N_T2_MRCC_34" pad="W6"/>
<connect gate="G$3" pin="IO_L13P_T2_MRCC_34" pad="W7"/>
<connect gate="G$3" pin="IO_L14N_T2_SRCC_34" pad="V8"/>
<connect gate="G$3" pin="IO_L14P_T2_SRCC_34" pad="U8"/>
<connect gate="G$3" pin="IO_L16N_T2_34" pad="V5"/>
<connect gate="G$3" pin="IO_L16P_T2_34" pad="U5"/>
<connect gate="G$3" pin="IO_L19N_T3_VREF_34" pad="V7"/>
<connect gate="G$3" pin="IO_L19P_T3_34" pad="U7"/>
<connect gate="G$3" pin="IO_L1N_T0_34" pad="T2"/>
<connect gate="G$3" pin="IO_L1P_T0_34" pad="R2"/>
<connect gate="G$3" pin="IO_L2N_T0_34" pad="T3"/>
<connect gate="G$3" pin="IO_L2P_T0_34" pad="R3"/>
<connect gate="G$3" pin="IO_L3N_T0_DQS_34" pad="U1"/>
<connect gate="G$3" pin="IO_L3P_T0_DQS_34" pad="T1"/>
<connect gate="G$3" pin="IO_L5N_T0_34" pad="W2"/>
<connect gate="G$3" pin="IO_L5P_T0_34" pad="V2"/>
<connect gate="G$3" pin="IO_L6N_T0_VREF_34" pad="W3"/>
<connect gate="G$3" pin="IO_L6P_T0_34" pad="V3"/>
<connect gate="G$3" pin="IO_L9N_T1_DQS_34" pad="U2"/>
<connect gate="G$3" pin="IO_L9P_T1_DQS_34" pad="U3"/>
<connect gate="G$3" pin="VCCO_34" pad="M8 N7 N8 R1 V1 V6"/>
<connect gate="G$4" pin="IO_L10N_T1_AD15N_35" pad="N1"/>
<connect gate="G$4" pin="IO_L10P_T1_AD15P_35" pad="N2"/>
<connect gate="G$4" pin="IO_L12N_T1_MRCC_35" pad="P3"/>
<connect gate="G$4" pin="IO_L12P_T1_MRCC_35" pad="N3"/>
<connect gate="G$4" pin="IO_L19N_T3_VREF_35" pad="P1"/>
<connect gate="G$4" pin="IO_L1N_T0_AD4N_35" pad="G2"/>
<connect gate="G$4" pin="IO_L1P_T0_AD4P_35" pad="G3"/>
<connect gate="G$4" pin="IO_L2N_T0_AD12N_35" pad="J2"/>
<connect gate="G$4" pin="IO_L2P_T0_AD12P_35" pad="H2"/>
<connect gate="G$4" pin="IO_L3N_T0_DQS_AD5N_35" pad="J1"/>
<connect gate="G$4" pin="IO_L3P_T0_DQS_AD5P_35" pad="H1"/>
<connect gate="G$4" pin="IO_L5N_T0_AD13N_35" pad="L2"/>
<connect gate="G$4" pin="IO_L5P_T0_AD13P_35" pad="K2"/>
<connect gate="G$4" pin="IO_L6N_T0_VREF_35" pad="L1"/>
<connect gate="G$4" pin="IO_L7N_T1_AD6N_35" pad="K3"/>
<connect gate="G$4" pin="IO_L7P_T1_AD6P_35" pad="J3"/>
<connect gate="G$4" pin="IO_L8N_T1_AD14N_35" pad="M3"/>
<connect gate="G$4" pin="IO_L8P_T1_AD14P_35" pad="L3"/>
<connect gate="G$4" pin="IO_L9N_T1_DQS_AD7N_35" pad="M1"/>
<connect gate="G$4" pin="IO_L9P_T1_DQS_AD7P_35" pad="M2"/>
<connect gate="G$4" pin="VCCO_35" pad="H3 J7 K1 K7 L7 M7"/>
<connect gate="G$5" pin="IO_L11N_T1_SRCC_16" pad="B15"/>
<connect gate="G$5" pin="IO_L11P_T1_SRCC_16" pad="C15"/>
<connect gate="G$5" pin="IO_L12N_T1_MRCC_16" pad="A17"/>
<connect gate="G$5" pin="IO_L12P_T1_MRCC_16" pad="A16"/>
<connect gate="G$5" pin="IO_L13N_T2_MRCC_16" pad="B16"/>
<connect gate="G$5" pin="IO_L13P_T2_MRCC_16" pad="C16"/>
<connect gate="G$5" pin="IO_L14N_T2_SRCC_16" pad="B17"/>
<connect gate="G$5" pin="IO_L14P_T2_SRCC_16" pad="C17"/>
<connect gate="G$5" pin="IO_L19N_T3_VREF_16" pad="A18"/>
<connect gate="G$5" pin="IO_L19P_T3_16" pad="B18"/>
<connect gate="G$5" pin="IO_L6N_T0_VREF_16" pad="A15"/>
<connect gate="G$5" pin="IO_L6P_T0_16" pad="A14"/>
<connect gate="G$5" pin="VCCO_16" pad="B19 C14 C18 G13"/>
<connect gate="G$6" pin="MGTPRXN0_216" pad="A4"/>
<connect gate="G$6" pin="MGTPRXN1_216" pad="A6"/>
<connect gate="G$6" pin="MGTPRXP0_216" pad="B4"/>
<connect gate="G$6" pin="MGTPRXP1_216" pad="B6"/>
<connect gate="G$6" pin="MGTPTXN0_216" pad="D1"/>
<connect gate="G$6" pin="MGTPTXN1_216" pad="A2"/>
<connect gate="G$6" pin="MGTPTXP0_216" pad="D2"/>
<connect gate="G$6" pin="MGTPTXP1_216" pad="B2"/>
<connect gate="G$6" pin="MGTREFCLK0N_216" pad="A8"/>
<connect gate="G$6" pin="MGTREFCLK0P_216" pad="B8"/>
<connect gate="G$6" pin="MGTREFCLK1N_216" pad="A10"/>
<connect gate="G$6" pin="MGTREFCLK1P_216" pad="B10"/>
<connect gate="G$6" pin="MGTRREF_216" pad="C7"/>
<connect gate="G$7" pin="GND" pad="A1 A3 A5 A7 A9 A19 B3 B5 B7 B9 B14 C2 C3 C4 C6 C10 C19 D3 E3 E17 F1 F2 F19 G1 G8 G11 H7 H8 H11 H12 H18 J8 J9 J11 J12 K8 L8 L9 L11 L19 M9 M13 N9 N12 N13 P2 T19 U6 U9 V18 W1 W12"/>
<connect gate="G$7" pin="MGTAVCC" pad="C1 E1 F3 G9 H9"/>
<connect gate="G$7" pin="MGTAVTT" pad="B1 C5 E2 G7"/>
<connect gate="G$7" pin="VCCAUX" pad="H13 J13"/>
<connect gate="G$7" pin="VCCBRAM" pad="M11 N11"/>
<connect gate="G$7" pin="VCCINT" pad="G10 H10 J10 L10 M10 N10"/>
</connects>
<technologies>
<technology name="">
<attribute name="MF" value="Xilinx Inc."/>
<attribute name="Description" value="
                        
                            Artix-7 Field Programmable Gate Array (FPGA) IC 106 2764800 52160 238-LFBGA, CSPBGA
                        
                    "/>
<attribute name="Package" value="CSBGA-236 Xilinx"/>
<attribute name="Price" value="None"/>
<attribute name="SnapEDA_Link" value="https://www.snapeda.com/parts/XC7A50T-2CPG236I/Xilinx+Inc./view-part/?ref=snap"/>
<attribute name="MP" value="XC7A50T-2CPG236I"/>
<attribute name="Availability" value="In Stock"/>
<attribute name="Check_prices" value="https://www.snapeda.com/parts/XC7A50T-2CPG236I/Xilinx+Inc./view-part/?ref=eda"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
</devicesets>
</library>
</drawing>
</eagle>
