<!--This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License (CC BY-SA) with Design Exception 1.0-->
<eagle version="7.1.0">
<drawing>
<library>
<packages>
<package name="BGA484C100P22X22_2300X2300X260N">
</package>
</packages>
<symbols>
<symbol name="XC7A100T-1FGG484C_SECTION1">
<pin name="IO_0_13"/>
<pin name="IO_L1N_T0_13"/>
<pin name="IO_L2P_T0_13"/>
<pin name="IO_L2N_T0_13"/>
<pin name="IO_L3P_T0_DQS_13"/>
<pin name="IO_L3N_T0_DQS_13"/>
<pin name="IO_L4P_T0_13"/>
<pin name="IO_L4N_T0_13"/>
<pin name="IO_L5P_T0_13"/>
<pin name="IO_L5N_T0_13"/>
<pin name="IO_L6P_T0_13"/>
<pin name="IO_L6N_T0_VREF_13"/>
<pin name="IO_L7P_T1_13"/>
<pin name="IO_L7N_T1_13"/>
<pin name="IO_L8P_T1_13"/>
<pin name="IO_L8N_T1_13"/>
<pin name="IO_L9P_T1_DQS_13"/>
<pin name="IO_L9N_T1_DQS_13"/>
<pin name="IO_L10P_T1_13"/>
<pin name="IO_L10N_T1_13"/>
<pin name="IO_L11P_T1_SRCC_13"/>
<pin name="IO_L11N_T1_SRCC_13"/>
<pin name="IO_L12P_T1_MRCC_13"/>
<pin name="IO_L12N_T1_MRCC_13"/>
<pin name="IO_L13P_T2_MRCC_13"/>
<pin name="IO_L13N_T2_MRCC_13"/>
<pin name="IO_L14P_T2_SRCC_13"/>
<pin name="IO_L14N_T2_SRCC_13"/>
<pin name="IO_L15P_T2_DQS_13"/>
<pin name="IO_L15N_T2_DQS_13"/>
<pin name="IO_L16P_T2_13"/>
<pin name="IO_L16N_T2_13"/>
<pin name="IO_L17P_T2_13"/>
<pin name="IO_L17N_T2_13"/>
<pin name="VCCO_13" direction="pwr"/>
<pin name="IO_L1P_T0_13"/>
</symbol>
<symbol name="XC7A100T-1FGG484C_SECTION2">
<pin name="IO_L1P_T0_D00_MOSI_14"/>
<pin name="IO_L1N_T0_D01_DIN_14"/>
<pin name="IO_L2P_T0_D02_14"/>
<pin name="IO_L2N_T0_D03_14"/>
<pin name="IO_L3P_T0_DQS_PUDC_B_14"/>
<pin name="IO_0_14"/>
<pin name="IO_L3N_T0_DQS_EMCCLK_14"/>
<pin name="IO_L4P_T0_D04_14"/>
<pin name="IO_L4N_T0_D05_14"/>
<pin name="IO_L5P_T0_D06_14"/>
<pin name="IO_L5N_T0_D07_14"/>
<pin name="IO_L6P_T0_FCS_B_14"/>
<pin name="IO_L6N_T0_D08_VREF_14"/>
<pin name="IO_L7P_T1_D09_14"/>
<pin name="IO_L7N_T1_D10_14"/>
<pin name="IO_L8P_T1_D11_14"/>
<pin name="IO_L8N_T1_D12_14"/>
<pin name="IO_L9P_T1_DQS_14"/>
<pin name="IO_L9N_T1_DQS_D13_14"/>
<pin name="IO_L10P_T1_D14_14"/>
<pin name="IO_L10N_T1_D15_14"/>
<pin name="IO_L11P_T1_SRCC_14"/>
<pin name="IO_L11N_T1_SRCC_14"/>
<pin name="IO_L12P_T1_MRCC_14"/>
<pin name="IO_L12N_T1_MRCC_14"/>
<pin name="IO_L13P_T2_MRCC_14"/>
<pin name="IO_L13N_T2_MRCC_14"/>
<pin name="IO_L14P_T2_SRCC_14"/>
<pin name="IO_L14N_T2_SRCC_14"/>
<pin name="IO_L15P_T2_DQS_RDWR_B_14"/>
<pin name="IO_L15N_T2_DQS_DOUT_CSO_B_14"/>
<pin name="IO_L16P_T2_CSI_B_14"/>
<pin name="IO_L16N_T2_A15_D31_14"/>
<pin name="IO_L17P_T2_A14_D30_14"/>
<pin name="IO_L17N_T2_A13_D29_14"/>
<pin name="IO_L18P_T2_A12_D28_14"/>
<pin name="IO_L18N_T2_A11_D27_14"/>
<pin name="IO_L19P_T3_A10_D26_14"/>
<pin name="IO_L19N_T3_A09_D25_VREF_14"/>
<pin name="IO_L20P_T3_A08_D24_14"/>
<pin name="IO_L20N_T3_A07_D23_14"/>
<pin name="IO_L21P_T3_DQS_14"/>
<pin name="IO_L21N_T3_DQS_A06_D22_14"/>
<pin name="IO_L22P_T3_A05_D21_14"/>
<pin name="IO_L22N_T3_A04_D20_14"/>
<pin name="IO_L23P_T3_A03_D19_14"/>
<pin name="IO_L23N_T3_A02_D18_14"/>
<pin name="IO_L24P_T3_A01_D17_14"/>
<pin name="IO_L24N_T3_A00_D16_14"/>
<pin name="IO_25_14"/>
<pin name="VCCO_14" direction="pwr"/>
</symbol>
<symbol name="XC7A100T-1FGG484C_SECTION3">
<pin name="IO_0_15"/>
<pin name="IO_L1P_T0_AD0P_15"/>
<pin name="IO_L1N_T0_AD0N_15"/>
<pin name="IO_L2P_T0_AD8P_15"/>
<pin name="IO_L2N_T0_AD8N_15"/>
<pin name="IO_L3P_T0_DQS_AD1P_15"/>
<pin name="IO_L3N_T0_DQS_AD1N_15"/>
<pin name="IO_L4P_T0_15"/>
<pin name="IO_L4N_T0_15"/>
<pin name="IO_L5P_T0_AD9P_15"/>
<pin name="IO_L5N_T0_AD9N_15"/>
<pin name="IO_L6P_T0_15"/>
<pin name="IO_L6N_T0_VREF_15"/>
<pin name="IO_L7P_T1_AD2P_15"/>
<pin name="IO_L7N_T1_AD2N_15"/>
<pin name="IO_L8P_T1_AD10P_15"/>
<pin name="IO_L8N_T1_AD10N_15"/>
<pin name="IO_L9P_T1_DQS_AD3P_15"/>
<pin name="IO_L9N_T1_DQS_AD3N_15"/>
<pin name="IO_L10P_T1_AD11P_15"/>
<pin name="IO_L10N_T1_AD11N_15"/>
<pin name="IO_L11P_T1_SRCC_15"/>
<pin name="IO_L11N_T1_SRCC_15"/>
<pin name="IO_L12P_T1_MRCC_15"/>
<pin name="IO_L12N_T1_MRCC_15"/>
<pin name="IO_L13P_T2_MRCC_15"/>
<pin name="IO_L13N_T2_MRCC_15"/>
<pin name="IO_L14P_T2_SRCC_15"/>
<pin name="IO_L14N_T2_SRCC_15"/>
<pin name="IO_L15P_T2_DQS_15"/>
<pin name="IO_L15N_T2_DQS_ADV_B_15"/>
<pin name="IO_L16P_T2_A28_15"/>
<pin name="IO_L16N_T2_A27_15"/>
<pin name="IO_L17P_T2_A26_15"/>
<pin name="IO_L17N_T2_A25_15"/>
<pin name="IO_L18P_T2_A24_15"/>
<pin name="IO_L18N_T2_A23_15"/>
<pin name="IO_L19P_T3_A22_15"/>
<pin name="IO_L19N_T3_A21_VREF_15"/>
<pin name="IO_L20P_T3_A20_15"/>
<pin name="IO_L20N_T3_A19_15"/>
<pin name="IO_L21P_T3_DQS_15"/>
<pin name="IO_L21N_T3_DQS_A18_15"/>
<pin name="IO_L22P_T3_A17_15"/>
<pin name="IO_L22N_T3_A16_15"/>
<pin name="IO_L23P_T3_FOE_B_15"/>
<pin name="IO_L23N_T3_FWE_B_15"/>
<pin name="IO_L24P_T3_RS1_15"/>
<pin name="IO_L24N_T3_RS0_15"/>
<pin name="IO_25_15"/>
<pin name="VCCO_15" direction="pwr"/>
</symbol>
<symbol name="XC7A100T-1FGG484C_SECTION4">
<pin name="IO_0_16"/>
<pin name="IO_L1P_T0_16"/>
<pin name="IO_L1N_T0_16"/>
<pin name="IO_L2P_T0_16"/>
<pin name="IO_L2N_T0_16"/>
<pin name="IO_L3P_T0_DQS_16"/>
<pin name="IO_L3N_T0_DQS_16"/>
<pin name="IO_L4P_T0_16"/>
<pin name="IO_L4N_T0_16"/>
<pin name="IO_L5P_T0_16"/>
<pin name="IO_L5N_T0_16"/>
<pin name="IO_L6P_T0_16"/>
<pin name="IO_L6N_T0_VREF_16"/>
<pin name="IO_L7P_T1_16"/>
<pin name="IO_L7N_T1_16"/>
<pin name="IO_L8P_T1_16"/>
<pin name="IO_L8N_T1_16"/>
<pin name="IO_L9P_T1_DQS_16"/>
<pin name="IO_L9N_T1_DQS_16"/>
<pin name="IO_L10P_T1_16"/>
<pin name="IO_L10N_T1_16"/>
<pin name="IO_L11P_T1_SRCC_16"/>
<pin name="IO_L11N_T1_SRCC_16"/>
<pin name="IO_L12P_T1_MRCC_16"/>
<pin name="IO_L12N_T1_MRCC_16"/>
<pin name="IO_L13P_T2_MRCC_16"/>
<pin name="IO_L13N_T2_MRCC_16"/>
<pin name="IO_L14P_T2_SRCC_16"/>
<pin name="IO_L14N_T2_SRCC_16"/>
<pin name="IO_L15P_T2_DQS_16"/>
<pin name="IO_L15N_T2_DQS_16"/>
<pin name="IO_L16P_T2_16"/>
<pin name="IO_L16N_T2_16"/>
<pin name="IO_L17P_T2_16"/>
<pin name="IO_L17N_T2_16"/>
<pin name="IO_L18P_T2_16"/>
<pin name="IO_L18N_T2_16"/>
<pin name="IO_L19P_T3_16"/>
<pin name="IO_L19N_T3_VREF_16"/>
<pin name="IO_L20P_T3_16"/>
<pin name="IO_L20N_T3_16"/>
<pin name="IO_L21P_T3_DQS_16"/>
<pin name="IO_L21N_T3_DQS_16"/>
<pin name="IO_L22P_T3_16"/>
<pin name="IO_L22N_T3_16"/>
<pin name="IO_L23P_T3_16"/>
<pin name="IO_L23N_T3_16"/>
<pin name="IO_L24P_T3_16"/>
<pin name="IO_L24N_T3_16"/>
<pin name="IO_25_16"/>
<pin name="VCCO_16" direction="pwr"/>
</symbol>
<symbol name="XC7A100T-1FGG484C_SECTION5">
<pin name="IO_0_34"/>
<pin name="IO_L1P_T0_34"/>
<pin name="IO_L1N_T0_34"/>
<pin name="IO_L2P_T0_34"/>
<pin name="IO_L2N_T0_34"/>
<pin name="IO_L3P_T0_DQS_34"/>
<pin name="IO_L3N_T0_DQS_34"/>
<pin name="IO_L4P_T0_34"/>
<pin name="IO_L4N_T0_34"/>
<pin name="IO_L5P_T0_34"/>
<pin name="IO_L5N_T0_34"/>
<pin name="IO_L6P_T0_34"/>
<pin name="IO_L6N_T0_VREF_34"/>
<pin name="IO_L7P_T1_34"/>
<pin name="IO_L7N_T1_34"/>
<pin name="IO_L8P_T1_34"/>
<pin name="IO_L8N_T1_34"/>
<pin name="IO_L9P_T1_DQS_34"/>
<pin name="IO_L9N_T1_DQS_34"/>
<pin name="IO_L10P_T1_34"/>
<pin name="IO_L10N_T1_34"/>
<pin name="IO_L11P_T1_SRCC_34"/>
<pin name="IO_L11N_T1_SRCC_34"/>
<pin name="IO_L12P_T1_MRCC_34"/>
<pin name="IO_L12N_T1_MRCC_34"/>
<pin name="IO_L13P_T2_MRCC_34"/>
<pin name="IO_L13N_T2_MRCC_34"/>
<pin name="IO_L14P_T2_SRCC_34"/>
<pin name="IO_L14N_T2_SRCC_34"/>
<pin name="IO_L15P_T2_DQS_34"/>
<pin name="IO_L15N_T2_DQS_34"/>
<pin name="IO_L16P_T2_34"/>
<pin name="IO_L16N_T2_34"/>
<pin name="IO_L17P_T2_34"/>
<pin name="IO_L17N_T2_34"/>
<pin name="IO_L18P_T2_34"/>
<pin name="IO_L18N_T2_34"/>
<pin name="IO_L19P_T3_34"/>
<pin name="IO_L19N_T3_VREF_34"/>
<pin name="IO_L20P_T3_34"/>
<pin name="IO_L20N_T3_34"/>
<pin name="IO_L21P_T3_DQS_34"/>
<pin name="IO_L21N_T3_DQS_34"/>
<pin name="IO_L22P_T3_34"/>
<pin name="IO_L22N_T3_34"/>
<pin name="IO_L23P_T3_34"/>
<pin name="IO_L23N_T3_34"/>
<pin name="IO_L24P_T3_34"/>
<pin name="IO_L24N_T3_34"/>
<pin name="IO_25_34"/>
<pin name="VCCO_34" direction="pwr"/>
</symbol>
<symbol name="XC7A100T-1FGG484C_SECTION6">
<pin name="IO_0_35"/>
<pin name="IO_L1P_T0_AD4P_35"/>
<pin name="IO_L1N_T0_AD4N_35"/>
<pin name="IO_L2P_T0_AD12P_35"/>
<pin name="IO_L2N_T0_AD12N_35"/>
<pin name="IO_L3P_T0_DQS_AD5P_35"/>
<pin name="IO_L3N_T0_DQS_AD5N_35"/>
<pin name="IO_L4P_T0_35"/>
<pin name="IO_L4N_T0_35"/>
<pin name="IO_L5P_T0_AD13P_35"/>
<pin name="IO_L5N_T0_AD13N_35"/>
<pin name="IO_L6P_T0_35"/>
<pin name="IO_L6N_T0_VREF_35"/>
<pin name="IO_L7P_T1_AD6P_35"/>
<pin name="IO_L7N_T1_AD6N_35"/>
<pin name="IO_L8P_T1_AD14P_35"/>
<pin name="IO_L8N_T1_AD14N_35"/>
<pin name="IO_L9P_T1_DQS_AD7P_35"/>
<pin name="IO_L9N_T1_DQS_AD7N_35"/>
<pin name="IO_L10P_T1_AD15P_35"/>
<pin name="IO_L10N_T1_AD15N_35"/>
<pin name="IO_L11P_T1_SRCC_35"/>
<pin name="IO_L11N_T1_SRCC_35"/>
<pin name="IO_L12P_T1_MRCC_35"/>
<pin name="IO_L12N_T1_MRCC_35"/>
<pin name="IO_L13P_T2_MRCC_35"/>
<pin name="IO_L13N_T2_MRCC_35"/>
<pin name="IO_L14P_T2_SRCC_35"/>
<pin name="IO_L14N_T2_SRCC_35"/>
<pin name="IO_L15P_T2_DQS_35"/>
<pin name="IO_L15N_T2_DQS_35"/>
<pin name="IO_L16P_T2_35"/>
<pin name="IO_L16N_T2_35"/>
<pin name="IO_L17P_T2_35"/>
<pin name="IO_L17N_T2_35"/>
<pin name="IO_L18P_T2_35"/>
<pin name="IO_L18N_T2_35"/>
<pin name="IO_L19P_T3_35"/>
<pin name="IO_L19N_T3_VREF_35"/>
<pin name="IO_L20P_T3_35"/>
<pin name="IO_L20N_T3_35"/>
<pin name="IO_L21P_T3_DQS_35"/>
<pin name="IO_L21N_T3_DQS_35"/>
<pin name="IO_L22P_T3_35"/>
<pin name="IO_L22N_T3_35"/>
<pin name="IO_L23P_T3_35"/>
<pin name="IO_L23N_T3_35"/>
<pin name="IO_L24P_T3_35"/>
<pin name="IO_L24N_T3_35"/>
<pin name="IO_25_35"/>
<pin name="VCCO_35"/>
</symbol>
<symbol name="XC7A100T-1FGG484C_SECTION7">
<pin name="MGTPTXP2_216"/>
<pin name="MGTPTXP3_216"/>
<pin name="MGTPRXP0_216"/>
<pin name="MGTPRXP3_216"/>
<pin name="MGTPRXP2_216"/>
<pin name="MGTPRXP1_216"/>
<pin name="MGTREFCLK0P_216"/>
<pin name="MGTREFCLK0N_216"/>
<pin name="MGTRREF_216"/>
<pin name="MGTPTXN2_216"/>
<pin name="MGTPTXN3_216"/>
<pin name="MGTPRXN0_216"/>
<pin name="MGTPRXN3_216"/>
<pin name="MGTPRXN2_216"/>
<pin name="MGTPRXN1_216"/>
<pin name="MGTREFCLK1N_216"/>
<pin name="MGTREFCLK1P_216"/>
<pin name="MGTPTXP1_216"/>
<pin name="MGTPTXN1_216"/>
<pin name="MGTPTXP0_216"/>
<pin name="MGTPTXN0_216"/>
</symbol>
<symbol name="XC7A100T-1FGG484C_SECTION8">
<pin name="DONE_0"/>
<pin name="TCK_0" direction="in" function="clk"/>
<pin name="VCCBATT_0" direction="pwr"/>
<pin name="VN_0" direction="pwr"/>
<pin name="VREFP_0" direction="pwr"/>
<pin name="GNDADC_0" direction="pwr"/>
<pin name="VCCADC_0" direction="pwr"/>
<pin name="DXP_0"/>
<pin name="CCLK_0"/>
<pin name="VP_0" direction="pwr"/>
<pin name="VREFN_0" direction="pwr"/>
<pin name="DXN_0"/>
<pin name="TDO_0" direction="out"/>
<pin name="TDI_0" direction="in"/>
<pin name="INIT_B_0" direction="in"/>
<pin name="M1_0"/>
<pin name="M0_0"/>
<pin name="TMS_0" direction="in"/>
<pin name="PROGRAM_B_0"/>
<pin name="CFGBVS_0"/>
<pin name="M2_0"/>
<pin name="VCCO_0" direction="pwr"/>
</symbol>
<symbol name="XC7A100T-1FGG484C_SECTION9">
<pin name="MGTAVCC" direction="pwr"/>
<pin name="MGTAVTT" direction="pwr"/>
<pin name="GND" direction="pwr"/>
<pin name="VCCINT" direction="pwr"/>
<pin name="VCCAUX" direction="pwr"/>
<pin name="VCCBRAM" direction="pwr"/>
</symbol>
</symbols>
<devicesets>
<deviceset name="XC7A100T-1FGG484C" prefix="U">
<description>FPGA Artix-7 Family 101440 Cells 28nm Technology 1V 484-Pin BGA &lt;a href="https://pricing.snapeda.com/parts/XC7A100T-1FGG484C/Xilinx%20Inc./view-part?ref=eda"&gt;Check availability&lt;/a&gt;</description>
<gates>
<gate name="G$1" symbol="XC7A100T-1FGG484C_SECTION1"/>
<gate name="G$2" symbol="XC7A100T-1FGG484C_SECTION2"/>
<gate name="G$3" symbol="XC7A100T-1FGG484C_SECTION3"/>
<gate name="G$4" symbol="XC7A100T-1FGG484C_SECTION4"/>
<gate name="G$5" symbol="XC7A100T-1FGG484C_SECTION5"/>
<gate name="G$6" symbol="XC7A100T-1FGG484C_SECTION6"/>
<gate name="G$7" symbol="XC7A100T-1FGG484C_SECTION7"/>
<gate name="G$8" symbol="XC7A100T-1FGG484C_SECTION8"/>
<gate name="G$9" symbol="XC7A100T-1FGG484C_SECTION9"/>
</gates>
<devices>
<device name="" package="BGA484C100P22X22_2300X2300X260N">
<connects>
<connect gate="G$1" pin="IO_0_13" pad="Y17"/>
<connect gate="G$1" pin="IO_L10N_T1_13" pad="W10"/>
<connect gate="G$1" pin="IO_L10P_T1_13" pad="V10"/>
<connect gate="G$1" pin="IO_L11N_T1_SRCC_13" pad="Y12"/>
<connect gate="G$1" pin="IO_L11P_T1_SRCC_13" pad="Y11"/>
<connect gate="G$1" pin="IO_L12N_T1_MRCC_13" pad="W12"/>
<connect gate="G$1" pin="IO_L12P_T1_MRCC_13" pad="W11"/>
<connect gate="G$1" pin="IO_L13N_T2_MRCC_13" pad="V14"/>
<connect gate="G$1" pin="IO_L13P_T2_MRCC_13" pad="V13"/>
<connect gate="G$1" pin="IO_L14N_T2_SRCC_13" pad="V15"/>
<connect gate="G$1" pin="IO_L14P_T2_SRCC_13" pad="U15"/>
<connect gate="G$1" pin="IO_L15N_T2_DQS_13" pad="T15"/>
<connect gate="G$1" pin="IO_L15P_T2_DQS_13" pad="T14"/>
<connect gate="G$1" pin="IO_L16N_T2_13" pad="W16"/>
<connect gate="G$1" pin="IO_L16P_T2_13" pad="W15"/>
<connect gate="G$1" pin="IO_L17N_T2_13" pad="U16"/>
<connect gate="G$1" pin="IO_L17P_T2_13" pad="T16"/>
<connect gate="G$1" pin="IO_L1N_T0_13" pad="AA16"/>
<connect gate="G$1" pin="IO_L1P_T0_13" pad="Y16"/>
<connect gate="G$1" pin="IO_L2N_T0_13" pad="AB17"/>
<connect gate="G$1" pin="IO_L2P_T0_13" pad="AB16"/>
<connect gate="G$1" pin="IO_L3N_T0_DQS_13" pad="AB13"/>
<connect gate="G$1" pin="IO_L3P_T0_DQS_13" pad="AA13"/>
<connect gate="G$1" pin="IO_L4N_T0_13" pad="AB15"/>
<connect gate="G$1" pin="IO_L4P_T0_13" pad="AA15"/>
<connect gate="G$1" pin="IO_L5N_T0_13" pad="AA14"/>
<connect gate="G$1" pin="IO_L5P_T0_13" pad="Y13"/>
<connect gate="G$1" pin="IO_L6N_T0_VREF_13" pad="Y14"/>
<connect gate="G$1" pin="IO_L6P_T0_13" pad="W14"/>
<connect gate="G$1" pin="IO_L7N_T1_13" pad="AB12"/>
<connect gate="G$1" pin="IO_L7P_T1_13" pad="AB11"/>
<connect gate="G$1" pin="IO_L8N_T1_13" pad="AB10"/>
<connect gate="G$1" pin="IO_L8P_T1_13" pad="AA9"/>
<connect gate="G$1" pin="IO_L9N_T1_DQS_13" pad="AA11"/>
<connect gate="G$1" pin="IO_L9P_T1_DQS_13" pad="AA10"/>
<connect gate="G$1" pin="VCCO_13" pad="AA17 AB14 V16 W13 Y10"/>
<connect gate="G$2" pin="IO_0_14" pad="P20"/>
<connect gate="G$2" pin="IO_25_14" pad="N15"/>
<connect gate="G$2" pin="IO_L10N_T1_D15_14" pad="AB22"/>
<connect gate="G$2" pin="IO_L10P_T1_D14_14" pad="AB21"/>
<connect gate="G$2" pin="IO_L11N_T1_SRCC_14" pad="V20"/>
<connect gate="G$2" pin="IO_L11P_T1_SRCC_14" pad="U20"/>
<connect gate="G$2" pin="IO_L12N_T1_MRCC_14" pad="W20"/>
<connect gate="G$2" pin="IO_L12P_T1_MRCC_14" pad="W19"/>
<connect gate="G$2" pin="IO_L13N_T2_MRCC_14" pad="Y19"/>
<connect gate="G$2" pin="IO_L13P_T2_MRCC_14" pad="Y18"/>
<connect gate="G$2" pin="IO_L14N_T2_SRCC_14" pad="V19"/>
<connect gate="G$2" pin="IO_L14P_T2_SRCC_14" pad="V18"/>
<connect gate="G$2" pin="IO_L15N_T2_DQS_DOUT_CSO_B_14" pad="AB20"/>
<connect gate="G$2" pin="IO_L15P_T2_DQS_RDWR_B_14" pad="AA19"/>
<connect gate="G$2" pin="IO_L16N_T2_A15_D31_14" pad="W17"/>
<connect gate="G$2" pin="IO_L16P_T2_CSI_B_14" pad="V17"/>
<connect gate="G$2" pin="IO_L17N_T2_A13_D29_14" pad="AB18"/>
<connect gate="G$2" pin="IO_L17P_T2_A14_D30_14" pad="AA18"/>
<connect gate="G$2" pin="IO_L18N_T2_A11_D27_14" pad="U18"/>
<connect gate="G$2" pin="IO_L18P_T2_A12_D28_14" pad="U17"/>
<connect gate="G$2" pin="IO_L19N_T3_A09_D25_VREF_14" pad="R14"/>
<connect gate="G$2" pin="IO_L19P_T3_A10_D26_14" pad="P14"/>
<connect gate="G$2" pin="IO_L1N_T0_D01_DIN_14" pad="R22"/>
<connect gate="G$2" pin="IO_L1P_T0_D00_MOSI_14" pad="P22"/>
<connect gate="G$2" pin="IO_L20N_T3_A07_D23_14" pad="T18"/>
<connect gate="G$2" pin="IO_L20P_T3_A08_D24_14" pad="R18"/>
<connect gate="G$2" pin="IO_L21N_T3_DQS_A06_D22_14" pad="P17"/>
<connect gate="G$2" pin="IO_L21P_T3_DQS_14" pad="N17"/>
<connect gate="G$2" pin="IO_L22N_T3_A04_D20_14" pad="R16"/>
<connect gate="G$2" pin="IO_L22P_T3_A05_D21_14" pad="P15"/>
<connect gate="G$2" pin="IO_L23N_T3_A02_D18_14" pad="N14"/>
<connect gate="G$2" pin="IO_L23P_T3_A03_D19_14" pad="N13"/>
<connect gate="G$2" pin="IO_L24N_T3_A00_D16_14" pad="R17"/>
<connect gate="G$2" pin="IO_L24P_T3_A01_D17_14" pad="P16"/>
<connect gate="G$2" pin="IO_L2N_T0_D03_14" pad="R21"/>
<connect gate="G$2" pin="IO_L2P_T0_D02_14" pad="P21"/>
<connect gate="G$2" pin="IO_L3N_T0_DQS_EMCCLK_14" pad="V22"/>
<connect gate="G$2" pin="IO_L3P_T0_DQS_PUDC_B_14" pad="U22"/>
<connect gate="G$2" pin="IO_L4N_T0_D05_14" pad="U21"/>
<connect gate="G$2" pin="IO_L4P_T0_D04_14" pad="T21"/>
<connect gate="G$2" pin="IO_L5N_T0_D07_14" pad="R19"/>
<connect gate="G$2" pin="IO_L5P_T0_D06_14" pad="P19"/>
<connect gate="G$2" pin="IO_L6N_T0_D08_VREF_14" pad="T20"/>
<connect gate="G$2" pin="IO_L6P_T0_FCS_B_14" pad="T19"/>
<connect gate="G$2" pin="IO_L7N_T1_D10_14" pad="W22"/>
<connect gate="G$2" pin="IO_L7P_T1_D09_14" pad="W21"/>
<connect gate="G$2" pin="IO_L8N_T1_D12_14" pad="AA21"/>
<connect gate="G$2" pin="IO_L8P_T1_D11_14" pad="AA20"/>
<connect gate="G$2" pin="IO_L9N_T1_DQS_D13_14" pad="Y22"/>
<connect gate="G$2" pin="IO_L9P_T1_DQS_14" pad="Y21"/>
<connect gate="G$2" pin="VCCO_14" pad="M14 P18 R15 T22 U19 Y20"/>
<connect gate="G$3" pin="IO_0_15" pad="J16"/>
<connect gate="G$3" pin="IO_25_15" pad="M17"/>
<connect gate="G$3" pin="IO_L10N_T1_AD11N_15" pad="L21"/>
<connect gate="G$3" pin="IO_L10P_T1_AD11P_15" pad="M21"/>
<connect gate="G$3" pin="IO_L11N_T1_SRCC_15" pad="J21"/>
<connect gate="G$3" pin="IO_L11P_T1_SRCC_15" pad="J20"/>
<connect gate="G$3" pin="IO_L12N_T1_MRCC_15" pad="H19"/>
<connect gate="G$3" pin="IO_L12P_T1_MRCC_15" pad="J19"/>
<connect gate="G$3" pin="IO_L13N_T2_MRCC_15" pad="K19"/>
<connect gate="G$3" pin="IO_L13P_T2_MRCC_15" pad="K18"/>
<connect gate="G$3" pin="IO_L14N_T2_SRCC_15" pad="L20"/>
<connect gate="G$3" pin="IO_L14P_T2_SRCC_15" pad="L19"/>
<connect gate="G$3" pin="IO_L15N_T2_DQS_ADV_B_15" pad="M22"/>
<connect gate="G$3" pin="IO_L15P_T2_DQS_15" pad="N22"/>
<connect gate="G$3" pin="IO_L16N_T2_A27_15" pad="L18"/>
<connect gate="G$3" pin="IO_L16P_T2_A28_15" pad="M18"/>
<connect gate="G$3" pin="IO_L17N_T2_A25_15" pad="N19"/>
<connect gate="G$3" pin="IO_L17P_T2_A26_15" pad="N18"/>
<connect gate="G$3" pin="IO_L18N_T2_A23_15" pad="M20"/>
<connect gate="G$3" pin="IO_L18P_T2_A24_15" pad="N20"/>
<connect gate="G$3" pin="IO_L19N_T3_A21_VREF_15" pad="K14"/>
<connect gate="G$3" pin="IO_L19P_T3_A22_15" pad="K13"/>
<connect gate="G$3" pin="IO_L1N_T0_AD0N_15" pad="G13"/>
<connect gate="G$3" pin="IO_L1P_T0_AD0P_15" pad="H13"/>
<connect gate="G$3" pin="IO_L20N_T3_A19_15" pad="L13"/>
<connect gate="G$3" pin="IO_L20P_T3_A20_15" pad="M13"/>
<connect gate="G$3" pin="IO_L21N_T3_DQS_A18_15" pad="J17"/>
<connect gate="G$3" pin="IO_L21P_T3_DQS_15" pad="K17"/>
<connect gate="G$3" pin="IO_L22N_T3_A16_15" pad="L15"/>
<connect gate="G$3" pin="IO_L22P_T3_A17_15" pad="L14"/>
<connect gate="G$3" pin="IO_L23N_T3_FWE_B_15" pad="K16"/>
<connect gate="G$3" pin="IO_L23P_T3_FOE_B_15" pad="L16"/>
<connect gate="G$3" pin="IO_L24N_T3_RS0_15" pad="M16"/>
<connect gate="G$3" pin="IO_L24P_T3_RS1_15" pad="M15"/>
<connect gate="G$3" pin="IO_L2N_T0_AD8N_15" pad="G16"/>
<connect gate="G$3" pin="IO_L2P_T0_AD8P_15" pad="G15"/>
<connect gate="G$3" pin="IO_L3N_T0_DQS_AD1N_15" pad="H14"/>
<connect gate="G$3" pin="IO_L3P_T0_DQS_AD1P_15" pad="J14"/>
<connect gate="G$3" pin="IO_L4N_T0_15" pad="G18"/>
<connect gate="G$3" pin="IO_L4P_T0_15" pad="G17"/>
<connect gate="G$3" pin="IO_L5N_T0_AD9N_15" pad="H15"/>
<connect gate="G$3" pin="IO_L5P_T0_AD9P_15" pad="J15"/>
<connect gate="G$3" pin="IO_L6N_T0_VREF_15" pad="H18"/>
<connect gate="G$3" pin="IO_L6P_T0_15" pad="H17"/>
<connect gate="G$3" pin="IO_L7N_T1_AD2N_15" pad="H22"/>
<connect gate="G$3" pin="IO_L7P_T1_AD2P_15" pad="J22"/>
<connect gate="G$3" pin="IO_L8N_T1_AD10N_15" pad="G20"/>
<connect gate="G$3" pin="IO_L8P_T1_AD10P_15" pad="H20"/>
<connect gate="G$3" pin="IO_L9N_T1_DQS_AD3N_15" pad="K22"/>
<connect gate="G$3" pin="IO_L9P_T1_DQS_AD3P_15" pad="K21"/>
<connect gate="G$3" pin="VCCO_15" pad="G19 H16 J13 K20 L17 N21"/>
<connect gate="G$4" pin="IO_0_16" pad="F15"/>
<connect gate="G$4" pin="IO_25_16" pad="F21"/>
<connect gate="G$4" pin="IO_L10N_T1_16" pad="A14"/>
<connect gate="G$4" pin="IO_L10P_T1_16" pad="A13"/>
<connect gate="G$4" pin="IO_L11N_T1_SRCC_16" pad="B18"/>
<connect gate="G$4" pin="IO_L11P_T1_SRCC_16" pad="B17"/>
<connect gate="G$4" pin="IO_L12N_T1_MRCC_16" pad="C17"/>
<connect gate="G$4" pin="IO_L12P_T1_MRCC_16" pad="D17"/>
<connect gate="G$4" pin="IO_L13N_T2_MRCC_16" pad="C19"/>
<connect gate="G$4" pin="IO_L13P_T2_MRCC_16" pad="C18"/>
<connect gate="G$4" pin="IO_L14N_T2_SRCC_16" pad="D19"/>
<connect gate="G$4" pin="IO_L14P_T2_SRCC_16" pad="E19"/>
<connect gate="G$4" pin="IO_L15N_T2_DQS_16" pad="E18"/>
<connect gate="G$4" pin="IO_L15P_T2_DQS_16" pad="F18"/>
<connect gate="G$4" pin="IO_L16N_T2_16" pad="A20"/>
<connect gate="G$4" pin="IO_L16P_T2_16" pad="B20"/>
<connect gate="G$4" pin="IO_L17N_T2_16" pad="A19"/>
<connect gate="G$4" pin="IO_L17P_T2_16" pad="A18"/>
<connect gate="G$4" pin="IO_L18N_T2_16" pad="F20"/>
<connect gate="G$4" pin="IO_L18P_T2_16" pad="F19"/>
<connect gate="G$4" pin="IO_L19N_T3_VREF_16" pad="C20"/>
<connect gate="G$4" pin="IO_L19P_T3_16" pad="D20"/>
<connect gate="G$4" pin="IO_L1N_T0_16" pad="F14"/>
<connect gate="G$4" pin="IO_L1P_T0_16" pad="F13"/>
<connect gate="G$4" pin="IO_L20N_T3_16" pad="B22"/>
<connect gate="G$4" pin="IO_L20P_T3_16" pad="C22"/>
<connect gate="G$4" pin="IO_L21N_T3_DQS_16" pad="A21"/>
<connect gate="G$4" pin="IO_L21P_T3_DQS_16" pad="B21"/>
<connect gate="G$4" pin="IO_L22N_T3_16" pad="D22"/>
<connect gate="G$4" pin="IO_L22P_T3_16" pad="E22"/>
<connect gate="G$4" pin="IO_L23N_T3_16" pad="D21"/>
<connect gate="G$4" pin="IO_L23P_T3_16" pad="E21"/>
<connect gate="G$4" pin="IO_L24N_T3_16" pad="G22"/>
<connect gate="G$4" pin="IO_L24P_T3_16" pad="G21"/>
<connect gate="G$4" pin="IO_L2N_T0_16" pad="E17"/>
<connect gate="G$4" pin="IO_L2P_T0_16" pad="F16"/>
<connect gate="G$4" pin="IO_L3N_T0_DQS_16" pad="C15"/>
<connect gate="G$4" pin="IO_L3P_T0_DQS_16" pad="C14"/>
<connect gate="G$4" pin="IO_L4N_T0_16" pad="E14"/>
<connect gate="G$4" pin="IO_L4P_T0_16" pad="E13"/>
<connect gate="G$4" pin="IO_L5N_T0_16" pad="D16"/>
<connect gate="G$4" pin="IO_L5P_T0_16" pad="E16"/>
<connect gate="G$4" pin="IO_L6N_T0_VREF_16" pad="D15"/>
<connect gate="G$4" pin="IO_L6P_T0_16" pad="D14"/>
<connect gate="G$4" pin="IO_L7N_T1_16" pad="B16"/>
<connect gate="G$4" pin="IO_L7P_T1_16" pad="B15"/>
<connect gate="G$4" pin="IO_L8N_T1_16" pad="B13"/>
<connect gate="G$4" pin="IO_L8P_T1_16" pad="C13"/>
<connect gate="G$4" pin="IO_L9N_T1_DQS_16" pad="A16"/>
<connect gate="G$4" pin="IO_L9P_T1_DQS_16" pad="A15"/>
<connect gate="G$4" pin="VCCO_16" pad="A17 B14 C21 D18 E15 F22"/>
<connect gate="G$5" pin="IO_0_34" pad="T3"/>
<connect gate="G$5" pin="IO_25_34" pad="U7"/>
<connect gate="G$5" pin="IO_L10N_T1_34" pad="AB5"/>
<connect gate="G$5" pin="IO_L10P_T1_34" pad="AA5"/>
<connect gate="G$5" pin="IO_L11N_T1_SRCC_34" pad="AA4"/>
<connect gate="G$5" pin="IO_L11P_T1_SRCC_34" pad="Y4"/>
<connect gate="G$5" pin="IO_L12N_T1_MRCC_34" pad="W4"/>
<connect gate="G$5" pin="IO_L12P_T1_MRCC_34" pad="V4"/>
<connect gate="G$5" pin="IO_L13N_T2_MRCC_34" pad="T4"/>
<connect gate="G$5" pin="IO_L13P_T2_MRCC_34" pad="R4"/>
<connect gate="G$5" pin="IO_L14N_T2_SRCC_34" pad="U5"/>
<connect gate="G$5" pin="IO_L14P_T2_SRCC_34" pad="T5"/>
<connect gate="G$5" pin="IO_L15N_T2_DQS_34" pad="W5"/>
<connect gate="G$5" pin="IO_L15P_T2_DQS_34" pad="W6"/>
<connect gate="G$5" pin="IO_L16N_T2_34" pad="V5"/>
<connect gate="G$5" pin="IO_L16P_T2_34" pad="U6"/>
<connect gate="G$5" pin="IO_L17N_T2_34" pad="T6"/>
<connect gate="G$5" pin="IO_L17P_T2_34" pad="R6"/>
<connect gate="G$5" pin="IO_L18N_T2_34" pad="AA6"/>
<connect gate="G$5" pin="IO_L18P_T2_34" pad="Y6"/>
<connect gate="G$5" pin="IO_L19N_T3_VREF_34" pad="W7"/>
<connect gate="G$5" pin="IO_L19P_T3_34" pad="V7"/>
<connect gate="G$5" pin="IO_L1N_T0_34" pad="U1"/>
<connect gate="G$5" pin="IO_L1P_T0_34" pad="T1"/>
<connect gate="G$5" pin="IO_L20N_T3_34" pad="AB6"/>
<connect gate="G$5" pin="IO_L20P_T3_34" pad="AB7"/>
<connect gate="G$5" pin="IO_L21N_T3_DQS_34" pad="V8"/>
<connect gate="G$5" pin="IO_L21P_T3_DQS_34" pad="V9"/>
<connect gate="G$5" pin="IO_L22N_T3_34" pad="AB8"/>
<connect gate="G$5" pin="IO_L22P_T3_34" pad="AA8"/>
<connect gate="G$5" pin="IO_L23N_T3_34" pad="Y7"/>
<connect gate="G$5" pin="IO_L23P_T3_34" pad="Y8"/>
<connect gate="G$5" pin="IO_L24N_T3_34" pad="Y9"/>
<connect gate="G$5" pin="IO_L24P_T3_34" pad="W9"/>
<connect gate="G$5" pin="IO_L2N_T0_34" pad="V2"/>
<connect gate="G$5" pin="IO_L2P_T0_34" pad="U2"/>
<connect gate="G$5" pin="IO_L3N_T0_DQS_34" pad="R2"/>
<connect gate="G$5" pin="IO_L3P_T0_DQS_34" pad="R3"/>
<connect gate="G$5" pin="IO_L4N_T0_34" pad="Y2"/>
<connect gate="G$5" pin="IO_L4P_T0_34" pad="W2"/>
<connect gate="G$5" pin="IO_L5N_T0_34" pad="Y1"/>
<connect gate="G$5" pin="IO_L5P_T0_34" pad="W1"/>
<connect gate="G$5" pin="IO_L6N_T0_VREF_34" pad="V3"/>
<connect gate="G$5" pin="IO_L6P_T0_34" pad="U3"/>
<connect gate="G$5" pin="IO_L7N_T1_34" pad="AB1"/>
<connect gate="G$5" pin="IO_L7P_T1_34" pad="AA1"/>
<connect gate="G$5" pin="IO_L8N_T1_34" pad="AB2"/>
<connect gate="G$5" pin="IO_L8P_T1_34" pad="AB3"/>
<connect gate="G$5" pin="IO_L9N_T1_DQS_34" pad="AA3"/>
<connect gate="G$5" pin="IO_L9P_T1_DQS_34" pad="Y3"/>
<connect gate="G$5" pin="VCCO_34" pad="AA7 AB4 R5 T2 V6 W3"/>
<connect gate="G$6" pin="IO_0_35" pad="F4"/>
<connect gate="G$6" pin="IO_25_35" pad="L6"/>
<connect gate="G$6" pin="IO_L10N_T1_AD15N_35" pad="H5"/>
<connect gate="G$6" pin="IO_L10P_T1_AD15P_35" pad="J5"/>
<connect gate="G$6" pin="IO_L11N_T1_SRCC_35" pad="G3"/>
<connect gate="G$6" pin="IO_L11P_T1_SRCC_35" pad="H3"/>
<connect gate="G$6" pin="IO_L12N_T1_MRCC_35" pad="G4"/>
<connect gate="G$6" pin="IO_L12P_T1_MRCC_35" pad="H4"/>
<connect gate="G$6" pin="IO_L13N_T2_MRCC_35" pad="J4"/>
<connect gate="G$6" pin="IO_L13P_T2_MRCC_35" pad="K4"/>
<connect gate="G$6" pin="IO_L14N_T2_SRCC_35" pad="K3"/>
<connect gate="G$6" pin="IO_L14P_T2_SRCC_35" pad="L3"/>
<connect gate="G$6" pin="IO_L15N_T2_DQS_35" pad="L1"/>
<connect gate="G$6" pin="IO_L15P_T2_DQS_35" pad="M1"/>
<connect gate="G$6" pin="IO_L16N_T2_35" pad="M2"/>
<connect gate="G$6" pin="IO_L16P_T2_35" pad="M3"/>
<connect gate="G$6" pin="IO_L17N_T2_35" pad="J6"/>
<connect gate="G$6" pin="IO_L17P_T2_35" pad="K6"/>
<connect gate="G$6" pin="IO_L18N_T2_35" pad="L4"/>
<connect gate="G$6" pin="IO_L18P_T2_35" pad="L5"/>
<connect gate="G$6" pin="IO_L19N_T3_VREF_35" pad="N3"/>
<connect gate="G$6" pin="IO_L19P_T3_35" pad="N4"/>
<connect gate="G$6" pin="IO_L1N_T0_AD4N_35" pad="A1"/>
<connect gate="G$6" pin="IO_L1P_T0_AD4P_35" pad="B1"/>
<connect gate="G$6" pin="IO_L20N_T3_35" pad="P1"/>
<connect gate="G$6" pin="IO_L20P_T3_35" pad="R1"/>
<connect gate="G$6" pin="IO_L21N_T3_DQS_35" pad="P4"/>
<connect gate="G$6" pin="IO_L21P_T3_DQS_35" pad="P5"/>
<connect gate="G$6" pin="IO_L22N_T3_35" pad="N2"/>
<connect gate="G$6" pin="IO_L22P_T3_35" pad="P2"/>
<connect gate="G$6" pin="IO_L23N_T3_35" pad="M5"/>
<connect gate="G$6" pin="IO_L23P_T3_35" pad="M6"/>
<connect gate="G$6" pin="IO_L24N_T3_35" pad="N5"/>
<connect gate="G$6" pin="IO_L24P_T3_35" pad="P6"/>
<connect gate="G$6" pin="IO_L2N_T0_AD12N_35" pad="B2"/>
<connect gate="G$6" pin="IO_L2P_T0_AD12P_35" pad="C2"/>
<connect gate="G$6" pin="IO_L3N_T0_DQS_AD5N_35" pad="D1"/>
<connect gate="G$6" pin="IO_L3P_T0_DQS_AD5P_35" pad="E1"/>
<connect gate="G$6" pin="IO_L4N_T0_35" pad="D2"/>
<connect gate="G$6" pin="IO_L4P_T0_35" pad="E2"/>
<connect gate="G$6" pin="IO_L5N_T0_AD13N_35" pad="F1"/>
<connect gate="G$6" pin="IO_L5P_T0_AD13P_35" pad="G1"/>
<connect gate="G$6" pin="IO_L6N_T0_VREF_35" pad="E3"/>
<connect gate="G$6" pin="IO_L6P_T0_35" pad="F3"/>
<connect gate="G$6" pin="IO_L7N_T1_AD6N_35" pad="J1"/>
<connect gate="G$6" pin="IO_L7P_T1_AD6P_35" pad="K1"/>
<connect gate="G$6" pin="IO_L8N_T1_AD14N_35" pad="G2"/>
<connect gate="G$6" pin="IO_L8P_T1_AD14P_35" pad="H2"/>
<connect gate="G$6" pin="IO_L9N_T1_DQS_AD7N_35" pad="J2"/>
<connect gate="G$6" pin="IO_L9P_T1_DQS_AD7P_35" pad="K2"/>
<connect gate="G$6" pin="VCCO_35" pad="C1 F2 H6 J3 M4 N1"/>
<connect gate="G$7" pin="MGTPRXN0_216" pad="A8"/>
<connect gate="G$7" pin="MGTPRXN1_216" pad="C11"/>
<connect gate="G$7" pin="MGTPRXN2_216" pad="A10"/>
<connect gate="G$7" pin="MGTPRXN3_216" pad="C9"/>
<connect gate="G$7" pin="MGTPRXP0_216" pad="B8"/>
<connect gate="G$7" pin="MGTPRXP1_216" pad="D11"/>
<connect gate="G$7" pin="MGTPRXP2_216" pad="B10"/>
<connect gate="G$7" pin="MGTPRXP3_216" pad="D9"/>
<connect gate="G$7" pin="MGTPTXN0_216" pad="A4"/>
<connect gate="G$7" pin="MGTPTXN1_216" pad="C5"/>
<connect gate="G$7" pin="MGTPTXN2_216" pad="A6"/>
<connect gate="G$7" pin="MGTPTXN3_216" pad="C7"/>
<connect gate="G$7" pin="MGTPTXP0_216" pad="B4"/>
<connect gate="G$7" pin="MGTPTXP1_216" pad="D5"/>
<connect gate="G$7" pin="MGTPTXP2_216" pad="B6"/>
<connect gate="G$7" pin="MGTPTXP3_216" pad="D7"/>
<connect gate="G$7" pin="MGTREFCLK0N_216" pad="E6"/>
<connect gate="G$7" pin="MGTREFCLK0P_216" pad="F6"/>
<connect gate="G$7" pin="MGTREFCLK1N_216" pad="E10"/>
<connect gate="G$7" pin="MGTREFCLK1P_216" pad="F10"/>
<connect gate="G$7" pin="MGTRREF_216" pad="F8"/>
<connect gate="G$8" pin="CCLK_0" pad="L12"/>
<connect gate="G$8" pin="CFGBVS_0" pad="U8"/>
<connect gate="G$8" pin="DONE_0" pad="G11"/>
<connect gate="G$8" pin="DXN_0" pad="N9"/>
<connect gate="G$8" pin="DXP_0" pad="N10"/>
<connect gate="G$8" pin="GNDADC_0" pad="K9"/>
<connect gate="G$8" pin="INIT_B_0" pad="U12"/>
<connect gate="G$8" pin="M0_0" pad="U11"/>
<connect gate="G$8" pin="M1_0" pad="U10"/>
<connect gate="G$8" pin="M2_0" pad="U9"/>
<connect gate="G$8" pin="PROGRAM_B_0" pad="N12"/>
<connect gate="G$8" pin="TCK_0" pad="V12"/>
<connect gate="G$8" pin="TDI_0" pad="R13"/>
<connect gate="G$8" pin="TDO_0" pad="U13"/>
<connect gate="G$8" pin="TMS_0" pad="T13"/>
<connect gate="G$8" pin="VCCADC_0" pad="K10"/>
<connect gate="G$8" pin="VCCBATT_0" pad="E12"/>
<connect gate="G$8" pin="VCCO_0" pad="F12 T12"/>
<connect gate="G$8" pin="VN_0" pad="M9"/>
<connect gate="G$8" pin="VP_0" pad="L10"/>
<connect gate="G$8" pin="VREFN_0" pad="L9"/>
<connect gate="G$8" pin="VREFP_0" pad="M10"/>
<connect gate="G$9" pin="GND" pad="A2 A3 A5 A7 A9 A11 A12 A22 AA2 AA12 AA22 AB9 AB19 B3 B12 B19 C3 C6 C10 C12 C16 D3 D4 D8 D12 D13 E4 E5 E7 E9 E11 E20 F5 F11 F17 G5 G6 G7 G8 G9 G10 G12 G14 H1 H7 H9 H11 H21 J8 J10 J12 J18 K5 K7 K11 K15 L2 L8 L22 M7 M11 M19 N6 N8 N16 P3 P7 P9 P11 P13 R8 R10 R12 R20 T7 T9 T11 T17 U4 U14 V1 V11 V21 W8 W18 Y5 Y15"/>
<connect gate="G$9" pin="MGTAVCC" pad="D6 D10 E8 F7 F9"/>
<connect gate="G$9" pin="MGTAVTT" pad="B5 B7 B9 B11 C4 C8"/>
<connect gate="G$9" pin="VCCAUX" pad="H12 K12 M12 P12 R11"/>
<connect gate="G$9" pin="VCCBRAM" pad="J11 L11 N11"/>
<connect gate="G$9" pin="VCCINT" pad="H8 H10 J7 J9 K8 L7 M8 N7 P8 P10 R7 R9 T8 T10"/>
</connects>
<technologies>
<technology name="">
<attribute name="MF" value="Xilinx Inc."/>
<attribute name="Description" value="
Artix-7 Field Programmable Gate Array (FPGA) IC 285 4976640 101440 484-BBGA
"/>
<attribute name="Package" value="FBGA-484 Xilinx"/>
<attribute name="Price" value="None"/>
<attribute name="SnapEDA_Link" value="https://www.snapeda.com/parts/XC7A100T-1FGG484C/Xilinx+Inc./view-part/?ref=snap"/>
<attribute name="MP" value="XC7A100T-1FGG484C"/>
<attribute name="Availability" value="In Stock"/>
<attribute name="Check_prices" value="https://www.snapeda.com/parts/XC7A100T-1FGG484C/Xilinx+Inc./view-part/?ref=eda"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
</devicesets>
</library>
</drawing>
</eagle>
