2 Commits

Author	SHA1	Message	Date
Jason	340c6d628d	chirp-v2 PR-A: radar_params.vh additive macros for 3-ladder + escalation ... Establishes the macro vocabulary for the SHORT/MEDIUM/LONG waveform ladder, 3-subframe Doppler layout, track-mode dwell, and 2-class CFAR detection. PR-A is purely additive — no module references the new macros yet. Subsequent PRs (B–H) progressively replace the old chirp logic; this one puts the names in place so each follow-on PR is mechanical. Added: - Waveform identity: RP_WAVE_{SHORT,MEDIUM,LONG,RESERVED} (2-bit selector) - Sub-frame layout: RP_NUM_SUBFRAMES=3, RP_DOPPLER_BIN_WIDTH=6, RP_SUBFRAME_ID_WIDTH=2 - Track mode: RP_DOPPLER_FFT_SIZE_TRACK=64, RP_MODE_TRACK=2'b11, RP_DEF_TRACK_CHIRP_COUNT=64, RP_DEF_TRACK_WATCHDOG_FRAMES=5 - Detection class: RP_DETECT_{NONE,CANDIDATE,CONFIRMED,RSVD} - 3-ladder timing defaults (V2 suffix to coexist with legacy in this PR): SHORT 100 cyc (1 µs), MEDIUM 500 cyc (5 µs), LONG 3000 cyc (30 µs) - Soft-CFAR alpha default: RP_DEF_CFAR_ALPHA_SOFT=0x18 (1.5 Q4.4, Pfa_soft ≈ 10⁻⁵; confirm Pfa ≈ 10⁻⁶ at α=3.0) - host_subframe_enable default: RP_DEF_SUBFRAME_ENABLE=3'b111 Marked LEGACY (deleted in the noted PR): - RP_CHIRPS_PER_FRAME=32, RP_NUM_DOPPLER_BINS=32 (PR-F) - RP_DEF_SHORT_CHIRP_CYCLES=50 (PR-E switches to 100) - RP_DEF_CHIRPS_PER_ELEV=32 (PR-F) Verified: iverilog preprocess clean. Sweep across 9_2_FPGA confirms no module references the new macros yet — the PR is fully isolated. Revert tag pre-chirp-v2 placed at 4f898ae for the chirp-v2 series.	2026-04-30 17:40:15 +05:45
Jason	60e49c7da6	feat(fpga): integrate 2048-pt FFT upgrade — non-conflicting RTL (wave 1/3) ... File-scoped cherry-pick from feat/fft-2048-upgrade (e9705e4) for modules that only the fft branch modified: RTL: cfar_ca.v 512-row CFAR chirp_memory_loader_param.v 2-segment × 2048-sample loader doppler_processor.v 16384-deep doppler memory fft_engine.v 2048-pt FFT matched_filter_multi_segment.v 2-seg overlap-save, BRAM overlap_cache matched_filter_processing_chain.v radar_mode_controller.v XOR edge detector radar_params.vh (new) single source of truth range_bin_decimator.v 2048 -> 512 output bins rx_gain_control.v Memory: fft_twiddle_2048.mem (new) 2048-pt FFT twiddles long_chirp_seg0_{i,q}.mem 2048-sample seg 0 (was 1024) long_chirp_seg1_{i,q}.mem 2048-sample seg 1 (was 1024) long_chirp_seg{2,3}_{i,q}.mem deleted (4-seg -> 2-seg collapse) Gen: tb/cosim/gen_chirp_mem.py regen script for mem files above Waves 2 and 3 follow: manual merge for dual-modified files (radar_system_top, usb_data_interface_ft2232h, mti_canceller, radar_receiver_final), and CFAR pipeline from 2401f5f keeping p0's CIC/DDC reset strategy.	2026-04-21 01:52:32 +05:45