4 Commits

Author	SHA1	Message	Date
Jason	6af79f9c74	fix(fpga): TX range-mode awareness + clamp reserved host codes ... C-1: plfm_chirp_controller was not range_mode-aware; it always ran LONG_CHIRP for CHIRP_MAX/2 chirps even when the host selected 3 km mode, where the ~4.5 km blind zone exceeds the 3 km max range and pollutes the RX window. IDLE now branches straight to SHORT_CHIRP when range_mode == RP_RANGE_MODE_3KM. host_range_mode is passed from radar_system_top through radar_transmitter, CDC'd per-bit from clk_100m to clk_120m_dac (coherency-safe: reserved codes are clamped at the source so only bit[0] toggles). S-3: opcode 0x20 now clamps reserved range-mode codes (2'b10, 2'b11) to the 3 km default so a garbled host write cannot silently enable long-range TX behaviour. Regression: tb_chirp_controller adds a 3 km-mode group (5 checks) verifying IDLE->SHORT_CHIRP skip path and DONE after CHIRP_MAX short chirps; tb_system_e2e G14 labels updated for clamped reserved codes. 32/32 regression PASS (50/50 on chirp TB).	2026-04-22 20:26:43 +05:45
Jason	fcf3999e39	Fix CDC reset domain bug (P0), strengthen testbenches with 31 structural assertions ... Split cdc_adc_to_processing reset_n into src_reset_n/dst_reset_n so source and destination clock domains use correctly-synchronized resets. Previously cdc_chirp_counter's destination-side sync chain (100MHz) was reset by sys_reset_120m_n (120MHz domain), causing 30 CDC critical warnings. RTL changes: - cdc_modules.v: split reset port, source logic uses src_reset_n, destination sync chains + output logic use dst_reset_n - radar_system_top.v: cdc_chirp_counter gets proper per-domain resets - ddc_400m.v: CDC_FIR_i/q use reset_n_400m (src) and reset_n (dst) - formal/fv_cdc_adc.v: updated wrapper for new port interface Build 7 fixes (previously untouched): - radar_transmitter.v: SPI level-shifter assigns, STM32 GPIO CDC sync - latency_buffer_2159.v: BRAM read registration - constraints: ft601 IOB -quiet fix - tb_latency_buffer.v: updated for BRAM changes Testbench hardening (tb_cdc_modules.v, +31 new assertions): - A5-A7: split-domain reset tests (staggered deassertion, independent dst reset while src active — catches the P0 bug class) - A8: port connectivity (no X/Z on outputs) - B7: cdc_single_bit port connectivity - C6: cdc_handshake reset recovery + port connectivity Full regression: 13/13 test suites pass (257 total assertions).	2026-03-17 19:38:09 +02:00
Jason	5fd632bc47	Fix all 10 CDC bugs from report_cdc audit, add overflow guard in range_bin_decimator ... CDC fixes across 6 RTL files based on post-implementation report_cdc analysis: - P0: sync stm32_mixers_enable and new_chirp_pulse to clk_120m via toggle CDC in radar_transmitter, add ft601 reset synchronizer and USB holding registers with proper edge detection in usb_data_interface - P1: add ASYNC_REG to edge_detector, convert new_chirp_frame to toggle CDC, fix USB valid edge detect to use fully-synced signal - P2: register Gray encoding in cdc_adc_to_processing source domain, sync ft601_txe and stm32_mixers_enable for status_reg in radar_system_top - Safety: add in_bin_count overflow guard in range_bin_decimator to prevent downstream BRAM corruption All 13 regression test suites pass (159 individual tests).	2026-03-17 13:48:47 +02:00
NawfalMotii79	5fbe97fa5f	Add files via upload	2026-03-09 00:17:39 +00:00