RTL (P0 pre-bringup findings R-1/R-2/R-3/R-5/R-6):
- mti_canceller: add use_long_chirp input and waveform-boundary mute
so the long->short transition in mode 01 no longer subtracts across
heterogeneous waveforms (R-1). Prev buffer is overwritten in-flight
at the boundary so the next same-waveform chirp subtracts cleanly.
- ad9484_interface_400m: 2FF sync of mmcm_locked into the 400 MHz
domain before gating reset_n_gated (R-6).
- cic_decimator_4x_enhanced: correct max_fanout narrative (R-3).
- ad9484_interface_400m: strip stale pblock comment, note 3.0 ns
max_delay instead (R-2).
- mti_canceller / doppler_processor: 200T-20km WARNING banners
flagging the broken 4096-bin path (R-5). 9-bit BRAM address aliases
silently until rewritten.
- adc_clk_mmcm.xdc: relax set_max_delay from 2.700 -> 3.000 ns,
closes WNS with headroom on 50T build.
- radar_receiver_final: wire use_long_chirp into mti_inst.
Architecture-bump finalization (2048-pt range FFT, 512 range bins,
32 Doppler bins -> 16384 output cells per frame):
- tb/cosim/radar_scene.py: FFT_SIZE 1024 -> 2048, RANGE_BINS 64 -> 512.
- tb/gen_mf_golden_ref.py: N 1024 -> 2048.
- Regenerate all affected hex goldens (MF cases 1-4, Doppler inputs
+ py goldens, receiver integration golden_doppler.mem 2048 -> 16384).
- tb_radar_receiver_final: widen range_bin_out 6 -> 9 bits, bump
GOLDEN_ENTRIES 2048 -> 16384, expand bitmaps/arrays to 512 bins,
update all check messages and thresholds.
- tb_mti_canceller, tb_fullchain_mti_cfar_realdata: tie/pass
use_long_chirp so compile still works after RTL port add.
Test-suite hardening (coverage audit findings):
- tb_mti_canceller T12: 10 new assertions exercising R-1 waveform-
boundary mute across a long/long/short/short/long sequence. Catches
a regression that re-enables subtraction across the boundary.
- tb_fir_lowpass: replace tautological check(1'b1, ...) on coefficient
symmetry with a real hierarchical check coeff[k]===coeff[31-k];
replace always-pass overflow check with a well-driven (not X/Z)
assertion on filter_overflow.
- tb_matched_filter_processing_chain: replace three always-pass peak-
bin placeholders with peak-to-mean-|out| > 2x ratio checks (catches
flat/zero output that the old tautologies silently accepted).
- tb_cdc_modules M2: replace always-pass narrow-pulse check with a
well-defined-output assertion on the synchronizer.
- tb_nco_400m: replace always-pass freq-switch check with a swing +
no-X assertion across 200 post-switch samples.
- tb_system_e2e G12.1: replace check(1, ...) with test_num > 20 so
it catches a stalled TB that skipped prior groups.
- tb_multiseg_cosim TEST 4: replace always-pass placeholder with a
bitmap that asserts segment_request visited all 4 values.
- tb_mf_chain_synth and tb_fullchain_mti_cfar_realdata: add DEPRECATED
headers plus \$fatal guards (ifndef ALLOW_STALE_*) so they cannot
be silently re-enabled in CI with stale 1024-bin goldens against
current 2048-pt RTL.
Regression: 32 passed, 0 failed. MTI TB grew 30 -> 39 checks;
receiver integration grew 17 -> 18 checks with 16384/16384 golden
match at tolerance +/- 2 LSB.
Hand-merged files modified on both fix/pre-bringup-audit-p0 and
feat/fft-2048-upgrade. Wave 1 (commit 60e49c7) took 20 files from fft
verbatim; this wave resolves the overlap.
- run_regression.sh: 3-way merge. Adopts fft's ${RECEIVER_RTL[@]} array
refactor and drops the self-blessing golden pair from p0. Skip count
bumped to 5.
- usb_data_interface.v (FT601/200T): p0 FSM + clock-loss watchdog kept
wholesale; widened stream_control 3 -> 6 bits to carry fft's extended
mode bits through the CDC sync chain and the 0xFF status word.
- mti_canceller.v: fft's BRAM-inferred 512-range-bin implementation as
the base, with p0's F-6.3 saturation counter grafted onto the d1
pipeline stage. Overflow detection uses the top-two-bits disagreement
on diff_{i,q}_full (DATA_WIDTH+1 signed).
- radar_receiver_final.v: fft's 2048-pt / 512-bin structure + p0
diagnostic plumbing (ADC overrange sticky+CDC, DDC diagnostics,
tx_frame_start edge detector replacing chirp_counter frame sync,
mti_saturation_count, range_decim_watchdog).
- radar_system_top.v: clean 3-way merge, orthogonal regions
(+38 / -27).
- usb_data_interface_ft2232h.v (FT2232H/50T): fft's per-frame bulk BRAM
rewrite kept wholesale. Ported two p0 items that are orthogonal to
the write FSM:
* ft_clk-loss watchdog (heartbeat + 2FF ASYNC_REG sync + 16-bit
timeout) ORed into a 2FF sync'd ft_effective_reset_n for the FSM.
* rd_cmd_complete flag so RD_DEASSERT can distinguish a legitimate
3-byte completion from an ft_rxf_n abort that also zeros
rd_byte_cnt.
Deliberately NOT taken from 2401f5f: cic_decimator_4x_enhanced.v and
ddc_400m.v reset-strategy changes. Those conflict with p0's shipped
registered-sync-reset + max_fanout=25 distribution, which is already
timing-clean on the production build.
Addresses findings from docs/DEVELOP_AUDIT_2026-04-19.md:
P0 source-level:
- F-4.3 ADAR1000_Manager::adarSetTxPhase now writes REG_LOAD_WORKING
with LD_WRK_REGS_LDTX_OVERRIDE (0x02) instead of 0x01. Previous value
toggled the LDRX latch on a TX-phase write, so host TX phase updates
never reached the working registers.
- F-6.1 DDC mixer_saturation / filter_overflow / diagnostics were deleted
at the receiver boundary. Now plumbed to new outputs on
radar_receiver_final (ddc_overflow_any, ddc_saturation_count) and
aggregated into gpio_dig5 in radar_system_top. Added mark_debug
attributes for ILA visibility. Test/debug inputs tied low explicitly.
- F-0.8 adc_clk_mmcm.xdc set_clock_uncertainty: removed invalid -add
flag (Vivado silently rejected it, applying zero guardband). Now uses
absolute 0.150 ns which covers 53 ps jitter + ~100 ps PVT margin.
P1:
- F-4.2 adarSetBit / adarResetBit reject broadcast=ON — the RMW sampled
a single device but wrote to all four, clobbering the other three's
state.
- F-4.4 initializeSingleDevice returns false and leaves initialized=false
when scratchpad verification fails; previously marked the device
initialized anyway so downstream PA enable could drive a dead bus.
- F-6.2 FIR I/Q filter_overflow ports, previously unconnected, now OR'd
into the module-level filter_overflow output.
- F-6.3 mti_canceller exposes 8-bit saturation counter. Saturation was
previously invisible and produces spurious Doppler harmonics.
Verification:
- 27/27 iverilog testbenches pass
- 228/228 pytest pass (cross-layer contract + cosim)
- MCU unit tests 51/51 + 24/24 pass
- Remote Vivado 2025.2 build: bitstream writes; 400 MHz mixer pipeline
now shows WNS -0.109 ns which MATCHES the audit's F-0.9 prediction
that the design only closed because F-0.8's guardband was silently
dropped. ft_clkout F-0.9 remains a show-stopper (requires MRCC pin
move), tracked separately.
Not addressed in this PR (larger scope, follow-up tickets):
F-0.4, F-0.5, F-0.6, F-0.7, F-0.9, F-1.1, F-1.2, F-2.2, F-3.2, F-4.1,
F-4.7, F-6.4, F-6.5.
MTI canceller (2-pulse, H(z)=1-z^{-1}) between range decimator and
Doppler processor. Subtracts previous chirp from current, nulling DC
Doppler (stationary clutter). Pass-through when host_mti_enable=0.
DC notch filter (post-Doppler, pre-CFAR) zeros bins within
+/-host_dc_notch_width of DC. Complements MTI for residual clutter.
New host registers: 0x26 (mti_enable), 0x27 (dc_notch_width).
Both default to 0 (disabled) - fully backward-compatible.
Verification: 23/23 regression, 29/29 MTI standalone, 3/3 real-data
co-sim (5137/5137 exact match) all PASS.
Jason