3 Commits

Author	SHA1	Message	Date
Jason	60e49c7da6	feat(fpga): integrate 2048-pt FFT upgrade — non-conflicting RTL (wave 1/3) ... File-scoped cherry-pick from feat/fft-2048-upgrade (e9705e4) for modules that only the fft branch modified: RTL: cfar_ca.v 512-row CFAR chirp_memory_loader_param.v 2-segment × 2048-sample loader doppler_processor.v 16384-deep doppler memory fft_engine.v 2048-pt FFT matched_filter_multi_segment.v 2-seg overlap-save, BRAM overlap_cache matched_filter_processing_chain.v radar_mode_controller.v XOR edge detector radar_params.vh (new) single source of truth range_bin_decimator.v 2048 -> 512 output bins rx_gain_control.v Memory: fft_twiddle_2048.mem (new) 2048-pt FFT twiddles long_chirp_seg0_{i,q}.mem 2048-sample seg 0 (was 1024) long_chirp_seg1_{i,q}.mem 2048-sample seg 1 (was 1024) long_chirp_seg{2,3}_{i,q}.mem deleted (4-seg -> 2-seg collapse) Gen: tb/cosim/gen_chirp_mem.py regen script for mem files above Waves 2 and 3 follow: manual merge for dual-modified files (radar_system_top, usb_data_interface_ft2232h, mti_canceller, radar_receiver_final), and CFAR pipeline from 2401f5f keeping p0's CIC/DDC reset strategy.	2026-04-21 01:52:32 +05:45
Jason	0745cc4f48	Pipeline CFAR noise computation: break critical path for timing closure ... Split ST_CFAR_THR into two pipeline stages (THR + MUL) to fix Build 23 timing violation (WNS = -0.309 ns). The combinational path from leading_sum through GO/SO cross-multiply into alpha*noise DSP was too long for 10 ns. New pipeline: ST_CFAR_THR: register noise_sum_comb (mode select + cross-multiply) ST_CFAR_MUL: compute alpha * noise_sum_reg in DSP ST_CFAR_CMP: compare + update window (unchanged) 3 cycles per CUT instead of 2 (~85 us vs 70 us per frame, negligible). All detection results identical: 23/23 CFAR standalone, 22/22 full regression, 3/3 real-data co-sim (5137/5137 exact match) PASS.	2026-03-20 05:24:08 +02:00
Jason	f71923b67d	Integrate CA-CFAR detector: replace fixed-threshold comparator with adaptive sliding-window CFAR engine (22/22 regression PASS) ... - Add cfar_ca.v: CA/GO/SO-CFAR with BRAM magnitude buffer, host-configurable guard cells, training cells, alpha multiplier, and mode selection - Replace old threshold detector block in radar_system_top.v with cfar_ca instantiation; backward-compatible (cfar_enable defaults to 0) - Add 5 new host registers: guard (0x21), train (0x22), alpha (0x23), mode (0x24), enable (0x25) - Expose doppler_frame_done_out from radar_receiver_final for CFAR frame sync - Add tb_cfar_ca.v standalone testbench (14 tests, 24 checks) - Add Group 14 E2E tests: 13 checks covering range-mode (0x20) and all CFAR config registers (0x21-0x25) through full USB command path - Update run_regression.sh with CFAR in lint, Phase 1, and integration compiles	2026-03-20 04:57:34 +02:00