Commit Graph

4 Commits

Author SHA1 Message Date
Jason db6b220f92 ci(fpga): PR-M.3 — wire T-6 drift cosim into regression + CI deps
Adds the T-6 independent reference drift cosim (PR-M.1, c30be89) as a
gated regression check so any future hand-edit drift in NCO_SINE_LUT,
fft_twiddle_*.mem, or DOPPLER_WINDOW_COEFF surfaces on every run.

run_regression.sh: new "Independent Reference Drift (T-6)" check after
the RX-B autocorrelation block in Phase 3. Plain `python3` (no path
sniffing). Distinguishes three states from the script's exit code +
markers:
  rc=0,  PASS markers -> PASS (counts toward `passed`)
  rc=2,  no markers   -> SKIP (counts toward `skipped`)
  rc!=0, FAIL markers -> FAIL (gates the regression)

compare_independent.py: detects missing numpy/scipy at startup and exits
with code 2 plus a [SKIP] marker pointing at `uv sync --group dev`.
Without that, an environment without scipy crashed mid-script and the
regression captured a partial 3-of-13 PASS count.

pyproject.toml: scipy>=1.13 added to the dev dependency group (used by
fpga_reference.doppler_window_ideal() for analytical Cheby ground truth).

.github/workflows/ci-tests.yml: fpga-regression now installs Python
3.12, sets up uv, runs `uv sync --group dev`, and activates the
resulting .venv before bash run_regression.sh. Without the activate
line the runner's system python3 (no scipy) would resolve first and
the drift check would [SKIP] in CI.

Verified locally:
  with venv:    Drift PASS (13 checks), Tests: 43 passed / 0 / 0
  no scipy:     Drift SKIP (msg points at install cmd), 42p / 0f / 1s
2026-05-01 18:53:09 +05:45
Jason 51740fd6f5 test(fpga): F-3.2 add DDC cosim fuzz runner with seed sweep
A new SCENARIO_FUZZ branch in tb_ddc_cosim.v accepts +hex / +csv / +tag
plusargs so an external runner can pick stimulus and output paths per
iteration. The three path registers are widened to 4 kbit each so long
temp-directory paths (e.g. /private/var/folders/...) do not overflow
the MSB and emerge truncated — a real failure mode caught while writing
this runner.

test_ddc_cosim_fuzz.py is a pytest-driven fuzz harness:
 - Generates a random plausible radar scene per seed (1-4 targets with
   random range/velocity/RCS/phase, random noise level 0.5-6.0 LSB
   stddev) via radar_scene.generate_adc_samples, fully deterministic.
 - Compiles tb_ddc_cosim.v once per session (module-scope fixture),
   then runs vvp per seed.
 - Asserts sample-count bounds consistent with 4x CIC decimation,
   signed-18 range on every baseband I/Q word, and non-zero output
   (catches silent pipeline stalls).
 - Ships with two tiers: test_ddc_fuzz_fast (8 seeds, default CI) and
   test_ddc_fuzz_full (100 seeds, opt-in via -m slow) matching the
   audit ask.

Registers the "slow" marker in pyproject.toml for the 100-seed opt-in.
2026-04-20 15:48:34 +05:45
Jason 2106e24952 fix: enforce strict ruff lint (17 rule sets) across entire repo
- Expand ruff config from E/F to 17 rule sets (B, RUF, SIM, PIE, T20,
  ARG, ERA, A, BLE, RET, ISC, TCH, UP, C4, PERF)
- Fix 907 lint errors across all Python files (GUI, FPGA cosim,
  schematics scripts, simulations, utilities, tools)
- Replace all blind except-Exception with specific exception types
- Remove commented-out dead code (ERA001) from cosim/simulation files
- Modernize typing: deprecated typing.List/Dict/Tuple to builtins
- Fix unused args/loop vars, ambiguous unicode, perf anti-patterns
- Delete legacy GUI files V1-V4
- Add V7 test suite, requirements files
- All CI jobs pass: ruff (0 errors), py_compile, pytest (92/92),
  MCU tests (20/20), FPGA regression (25/25)
2026-04-12 14:21:03 +05:45
Jason 11aa590cf2 fix: full-repo ruff lint cleanup and CI migration to uv
Resolve all 374 ruff errors across 36 Python files (E501, E702, E722,
E741, F821, F841, invalid-syntax) bringing `ruff check .` to zero
errors repo-wide with line-length=100.

Rewrite CI workflow to use uv for dependency management, whole-repo
`ruff check .`, py_compile syntax gate, and merged python-tests job.
Add pyproject.toml with ruff config and uv dependency groups.

CI structure proposed by hcm444.
2026-04-09 02:05:34 +03:00