2 Commits

Author	SHA1	Message	Date
Jason	f39a78cb1e	chore(fpga): untrack TB-generated CSV, ignore a.out ... rx_final_doppler_out.csv is written by tb_radar_receiver_final.v on every run via $fopen — it is a test-run artifact, not an oracle. It was mistakenly tracked in an earlier commit, causing unnecessary churn on every sim. Remove from the index and ignore going forward. Also ignore stray a.out from iverilog one-shot compiles. Golden references (.hex, .mem, doppler_golden_py_*.csv) remain tracked — they are load-bearing oracles used by MF / Doppler / receiver cosim testbenches.	2026-04-22 13:36:03 +05:45
Jason	463ebef554	CIC comb pipeline registers, BUFG sim guard, system TB fix, regression runner ... - cic_decimator_4x_enhanced.v: Add integrator_sampled_comb and data_valid_comb_pipe pipeline stages between integrator sampling and comb computation to break the critical path (matches remote 40cda0f) - radar_system_top.v: Wrap 3 BUFG instances in ifdef SIMULATION guard with pass-through assigns for iverilog compatibility - radar_system_tb.v: Convert generate_radar_echo function to task and move sin_lut declaration before task (iverilog declaration-order fix), add modular index clamping to prevent LUT out-of-bounds - run_regression.sh: Automated regression runner for all 18 FPGA testbenches with --quick mode. Results: 17 pass, 1 pre-existing fail - .gitignore: Exclude *.vvp, *.vcd simulation artifacts	2026-03-19 11:31:46 +02:00