 Jason
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60e49c7da6
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feat(fpga): integrate 2048-pt FFT upgrade — non-conflicting RTL (wave 1/3)
File-scoped cherry-pick from feat/fft-2048-upgrade (e9705e4) for modules
that only the fft branch modified:
RTL:
cfar_ca.v 512-row CFAR
chirp_memory_loader_param.v 2-segment × 2048-sample loader
doppler_processor.v 16384-deep doppler memory
fft_engine.v 2048-pt FFT
matched_filter_multi_segment.v 2-seg overlap-save, BRAM overlap_cache
matched_filter_processing_chain.v
radar_mode_controller.v XOR edge detector
radar_params.vh (new) single source of truth
range_bin_decimator.v 2048 -> 512 output bins
rx_gain_control.v
Memory:
fft_twiddle_2048.mem (new) 2048-pt FFT twiddles
long_chirp_seg0_{i,q}.mem 2048-sample seg 0 (was 1024)
long_chirp_seg1_{i,q}.mem 2048-sample seg 1 (was 1024)
long_chirp_seg{2,3}_{i,q}.mem deleted (4-seg -> 2-seg collapse)
Gen:
tb/cosim/gen_chirp_mem.py regen script for mem files above
Waves 2 and 3 follow: manual merge for dual-modified files
(radar_system_top, usb_data_interface_ft2232h, mti_canceller,
radar_receiver_final), and CFAR pipeline from 2401f5f keeping p0's
CIC/DDC reset strategy.
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2026-04-21 01:52:32 +05:45 |
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