From f5b8e7a20b1e4227b95b2bffc31d4e931345aec6 Mon Sep 17 00:00:00 2001
From: Jason <83615043+JJassonn69@users.noreply.github.com>
Date: Thu, 30 Apr 2026 17:46:08 +0545
Subject: [PATCH] chirp-v2 PR-B: 3-waveform mem generator + 11 new .mem files
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Rewrite gen_chirp_mem.py to emit the SHORT (1 µs), MEDIUM (5 µs), and LONG
(30 µs) waveform set on both TX and RX paths. The script is now the single
source for every chirp .mem file; the legacy 6-file set on disk
(long_chirp_lut.mem, long_chirp_seg{0,1}_{i,q}.mem, short_chirp_{i,q}.mem)
is no longer regenerated and gets deleted in PR-C/PR-E when its consumer
modules are removed.

Generated artifacts (committed):
  TX (8-bit unsigned offset-binary, fs_dac = 120 MHz):
    tx_short_lut.mem    120  lines
    tx_medium_lut.mem   600  lines
    tx_long_lut.mem     3600 lines
  RX (Q15 I/Q hex, fs_sys = 100 MHz, all 2048 lines for uniform BRAM sizing):
    rx_short_i.mem  / rx_short_q.mem    100  active + 1948 zero-pad
    rx_medium_i.mem / rx_medium_q.mem   500  active + 1548 zero-pad
    rx_long_seg0_i.mem  / rx_long_seg0_q.mem   2048 (samples [0..2047])
    rx_long_seg1_i.mem  / rx_long_seg1_q.mem   952 active + 1096 zero-pad

Phase model unchanged from chirp-v1: phi(n) = 2π·F_BASEBAND_LOW·t +
π·(BW/T)·t² with F_BASEBAND_LOW=10 MHz and BW=20 MHz. The same formula now
runs three durations and two sample rates from one helper.
rx_long_seg0_i.mem is bit-exact to the legacy long_chirp_seg0_i.mem on disk
(diff -q reports identical) — proves the SHORT/MEDIUM additions did not
perturb the LONG path.

Verification:
  - all 11 files have correct line counts (above)
  - script is idempotent (re-run produces byte-identical output)
  - ruff clean (one E501 line-length + two RUF046 redundant-int casts fixed)
  - phase regression at long-seg0 against pre-chirp-v2 reference: bit-exact

No RTL or testbench changes. The legacy .mem files remain on disk for the
existing chirp_memory_loader_param.v / plfm_chirp_controller.v consumers
until PR-C and PR-E delete those modules. No module references the new
files yet.
---
 9_Firmware/9_2_FPGA/rx_long_seg0_i.mem        | 2048 ++++++++++
 9_Firmware/9_2_FPGA/rx_long_seg0_q.mem        | 2048 ++++++++++
 9_Firmware/9_2_FPGA/rx_long_seg1_i.mem        | 2048 ++++++++++
 9_Firmware/9_2_FPGA/rx_long_seg1_q.mem        | 2048 ++++++++++
 9_Firmware/9_2_FPGA/rx_medium_i.mem           | 2048 ++++++++++
 9_Firmware/9_2_FPGA/rx_medium_q.mem           | 2048 ++++++++++
 9_Firmware/9_2_FPGA/rx_short_i.mem            | 2048 ++++++++++
 9_Firmware/9_2_FPGA/rx_short_q.mem            | 2048 ++++++++++
 9_Firmware/9_2_FPGA/tb/cosim/gen_chirp_mem.py |  324 +-
 9_Firmware/9_2_FPGA/tx_long_lut.mem           | 3600 +++++++++++++++++
 9_Firmware/9_2_FPGA/tx_medium_lut.mem         |  600 +++
 9_Firmware/9_2_FPGA/tx_short_lut.mem          |  120 +
 12 files changed, 20854 insertions(+), 174 deletions(-)
 create mode 100644 9_Firmware/9_2_FPGA/rx_long_seg0_i.mem
 create mode 100644 9_Firmware/9_2_FPGA/rx_long_seg0_q.mem
 create mode 100644 9_Firmware/9_2_FPGA/rx_long_seg1_i.mem
 create mode 100644 9_Firmware/9_2_FPGA/rx_long_seg1_q.mem
 create mode 100644 9_Firmware/9_2_FPGA/rx_medium_i.mem
 create mode 100644 9_Firmware/9_2_FPGA/rx_medium_q.mem
 create mode 100644 9_Firmware/9_2_FPGA/rx_short_i.mem
 create mode 100644 9_Firmware/9_2_FPGA/rx_short_q.mem
 create mode 100644 9_Firmware/9_2_FPGA/tx_long_lut.mem
 create mode 100644 9_Firmware/9_2_FPGA/tx_medium_lut.mem
 create mode 100644 9_Firmware/9_2_FPGA/tx_short_lut.mem

diff --git a/9_Firmware/9_2_FPGA/rx_long_seg0_i.mem b/9_Firmware/9_2_FPGA/rx_long_seg0_i.mem
new file mode 100644
index 0000000..8209045
--- /dev/null
+++ b/9_Firmware/9_2_FPGA/rx_long_seg0_i.mem
@@ -0,0 +1,2048 @@
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diff --git a/9_Firmware/9_2_FPGA/rx_long_seg0_q.mem b/9_Firmware/9_2_FPGA/rx_long_seg0_q.mem
new file mode 100644
index 0000000..6207c52
--- /dev/null
+++ b/9_Firmware/9_2_FPGA/rx_long_seg0_q.mem
@@ -0,0 +1,2048 @@
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diff --git a/9_Firmware/9_2_FPGA/rx_long_seg1_i.mem b/9_Firmware/9_2_FPGA/rx_long_seg1_i.mem
new file mode 100644
index 0000000..0dbd6d4
--- /dev/null
+++ b/9_Firmware/9_2_FPGA/rx_long_seg1_i.mem
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diff --git a/9_Firmware/9_2_FPGA/rx_long_seg1_q.mem b/9_Firmware/9_2_FPGA/rx_long_seg1_q.mem
new file mode 100644
index 0000000..f7000dc
--- /dev/null
+++ b/9_Firmware/9_2_FPGA/rx_long_seg1_q.mem
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diff --git a/9_Firmware/9_2_FPGA/rx_medium_i.mem b/9_Firmware/9_2_FPGA/rx_medium_i.mem
new file mode 100644
index 0000000..b1e8cec
--- /dev/null
+++ b/9_Firmware/9_2_FPGA/rx_medium_i.mem
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diff --git a/9_Firmware/9_2_FPGA/rx_medium_q.mem b/9_Firmware/9_2_FPGA/rx_medium_q.mem
new file mode 100644
index 0000000..f32ea7b
--- /dev/null
+++ b/9_Firmware/9_2_FPGA/rx_medium_q.mem
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diff --git a/9_Firmware/9_2_FPGA/rx_short_i.mem b/9_Firmware/9_2_FPGA/rx_short_i.mem
new file mode 100644
index 0000000..1cefc84
--- /dev/null
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diff --git a/9_Firmware/9_2_FPGA/rx_short_q.mem b/9_Firmware/9_2_FPGA/rx_short_q.mem
new file mode 100644
index 0000000..71b9a98
--- /dev/null
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diff --git a/9_Firmware/9_2_FPGA/tb/cosim/gen_chirp_mem.py b/9_Firmware/9_2_FPGA/tb/cosim/gen_chirp_mem.py
index 8b3d459..cdd2d6c 100644
--- a/9_Firmware/9_2_FPGA/tb/cosim/gen_chirp_mem.py
+++ b/9_Firmware/9_2_FPGA/tb/cosim/gen_chirp_mem.py
@@ -1,55 +1,41 @@
 #!/usr/bin/env python3
 """
-gen_chirp_mem.py — Generate all chirp .mem files for AERIS-10 FPGA.
+gen_chirp_mem.py — Generate the 11 chirp .mem files for the AERIS-10 FPGA.
 
-Generates the 6 chirp .mem files used by chirp_memory_loader_param.v:
-  - long_chirp_seg{0,1}_{i,q}.mem  (4 files, 2048 lines each)
-  - short_chirp_{i,q}.mem          (2 files, 50 lines each)
+3-ladder waveform set (chirp-v2 PR-B). Replaces the legacy 2-waveform script.
+The legacy 6-file output (long_chirp_seg{0,1}_{i,q}.mem, short_chirp_{i,q}.mem,
+long_chirp_lut.mem) is no longer regenerated by this script; the legacy files
+on disk are deleted in PR-C (RX) and PR-E (TX) when their consumers go away.
 
-Long chirp:
-  The 3000-sample baseband chirp (30 us at 100 MHz system clock) is
-  segmented into 2 blocks of 2048 samples.  Each segment covers a
-  different time window of the chirp:
-    seg0: samples    0 .. 2047
-    seg1: samples 2048 .. 4095  (only 952 valid chirp samples; 1096 zeros)
+TX side (DAC LUTs, 8-bit unsigned offset-binary, fs_dac = 120 MHz):
+  tx_short_lut.mem    120  samples (1 µs)
+  tx_medium_lut.mem   600  samples (5 µs)
+  tx_long_lut.mem     3600 samples (30 µs)
 
-  The memory loader stores 2*2048 = 4096 contiguous samples indexed
-  by {segment_select[0], sample_addr[10:0]}.  The long chirp has
-  3000 samples, so:
-    seg0: chirp[0..2047] — all valid data
-    seg1: chirp[2048..2999] + 1096 zeros (samples past chirp end)
+RX side (matched-filter reference, Q15 I/Q hex, fs_sys = 100 MHz, all 2048 entries):
+  rx_short_i.mem  / rx_short_q.mem    100  active + 1948 zero-pad
+  rx_medium_i.mem / rx_medium_q.mem   500  active + 1548 zero-pad
+  rx_long_seg0_i.mem / rx_long_seg0_q.mem   2048 (samples 0..2047 of long chirp)
+  rx_long_seg1_i.mem / rx_long_seg1_q.mem   952 active + 1096 zero-pad
+                                             (samples 2048..2999 of long chirp)
 
-Short chirp:
-  50 samples (0.5 us at 100 MHz), same chirp formula with
-  T_SHORT_CHIRP and CHIRP_BW.
-
-Phase model (baseband, post-DDC):
-  phase(n) = 2*pi*F_BASEBAND_LOW*t + pi * chirp_rate * t^2,  t = n / FS_SYS
+Phase model (baseband, post-DDC for RX, pre-upmix for TX):
+  phase(n)   = 2π · F_BASEBAND_LOW · t + π · chirp_rate · t²
   chirp_rate = CHIRP_BW / T_chirp
-  F_BASEBAND_LOW = 10 MHz  (DAC chirp low-edge frequency)
+  F_BASEBAND_LOW = 10 MHz
+  CHIRP_BW       = 20 MHz   (uniform across all three waveforms — same range res)
 
-This produces a F_BASEBAND_LOW..(F_BASEBAND_LOW+CHIRP_BW) baseband upchirp.
+End-to-end frequency plan (TX-I, unchanged from chirp-v1):
+  DAC LUT  : 10..30 MHz @ fs_dac=120 MHz
+  TX upmix : LO=10.500 GHz, high-side -> RF transmitted: 10.510..10.530 GHz
+  RX downmix: LO=10.380 GHz, high-side -> IF at ADC:    130..150 MHz
+  DDC NCO  : 120 MHz exactly (ddc_400m.v) -> baseband:   10..30 MHz
 
-End-to-end frequency plan (TX-I, 2026-04-28):
-  DAC LUT  : 10..30 MHz @ fs_dac=120 MHz       (plfm_chirp_controller.v;
-                                                 Hilbert-confirmed for both
-                                                 long and short LUTs)
-  TX upmix : LO=10.500 GHz (adf4382a_manager.h:35), high-side
-             -> RF transmitted: 10.510..10.530 GHz
-  RX downmix: LO=10.380 GHz (adf4382a_manager.h:36), high-side
-              -> IF at ADC:    130..150 MHz
-  DDC NCO  : 120 MHz exactly (ddc_400m.v:201)
-             -> baseband:     10..30 MHz   <-- matched-filter reference
+radar_scene.py uses the same F_BASEBAND_LOW and CHIRP_BW constants; both
+must stay in sync.
 
-Sideband orientation (high-side at both mixers) is the conventional choice
-and consistent with all design comments / antenna match (10.25..10.75 GHz);
-loopback capture would settle it definitively. If either mixer turns out to
-be low-side, the sign of F_BASEBAND_LOW flips and/or the chirp direction
-reverses; revisit before re-generating .mem files.
-
-radar_scene.py uses the same F_BASEBAND_LOW; both must stay in sync.
-
-Scaling: 0.9 * 32767 (Q15)
+Scaling: 0.9 of full-scale for the Q15 (RX) path. TX LUT scales 127·0.9 ≈ 114
+into the ±127 swing around the 128 (8'd128) idle code.
 
 Usage:
     python3 gen_chirp_mem.py
@@ -60,163 +46,153 @@ import os
 import sys
 
 # ============================================================================
-# AERIS-10 Parameters (matching radar_scene.py)
+# AERIS-10 Parameters
 # ============================================================================
-CHIRP_BW = 20e6           # 20 MHz sweep bandwidth
-FS_SYS = 100e6            # System clock (100 MHz, post-CIC)
-T_LONG_CHIRP = 30e-6      # 30 us long chirp duration
-T_SHORT_CHIRP = 0.5e-6    # 0.5 us short chirp duration
-FFT_SIZE = 2048
-# DAC chirp baseband low-edge frequency. The TX LUT in plfm_chirp_controller.v
-# is a 10..30 MHz upchirp at fs_dac=120 MHz (Hilbert-confirmed for both long
-# and short LUTs). With TX_LO=10.500 GHz, RX_LO=10.380 GHz (adf4382a_manager.h)
-# and the 120 MHz DDC NCO (ddc_400m.v), high-side mixing places the post-DDC
-# echo at 10..30 MHz baseband, not 0..20 MHz. The matched-filter reference
-# must include this +10 MHz DC offset.
-F_BASEBAND_LOW = 10e6
-LONG_CHIRP_SAMPLES = int(T_LONG_CHIRP * FS_SYS)   # 3000
-SHORT_CHIRP_SAMPLES = int(T_SHORT_CHIRP * FS_SYS)  # 50
-LONG_SEGMENTS = 2
-SCALE = 0.9               # Q15 scaling factor (matches radar_scene.py)
-Q15_MAX = 32767
+CHIRP_BW = 20e6                 # 20 MHz sweep — same for all three waveforms
+FS_SYS   = 100e6                # System clock for RX matched filter
+FS_DAC   = 120e6                # DAC clock for TX waveform synthesis
+F_BASEBAND_LOW = 10e6           # Low edge of post-DDC baseband
+SCALE = 0.9                     # Backoff from full-scale (both paths)
 
-# Output directory (FPGA RTL root, where .mem files live)
+# Waveform durations (seconds) — see radar_params.vh RP_DEF_*_CHIRP_CYCLES_V2
+T_SHORT  = 1e-6                 # 1 µs   (PR-B v2; chirp-v1 was 0.5 µs)
+T_MEDIUM = 5e-6                 # 5 µs
+T_LONG   = 30e-6                # 30 µs
+
+# RX FFT segment size — chirp_reference_rom (PR-C) uses one 2048-entry BRAM
+# per waveform lane. LONG is the only waveform that crosses the segment
+# boundary; SHORT and MEDIUM fit in a single 2048-entry buffer with zero-pad.
+FFT_SIZE = 2048
+
+# Q15 / 8-bit envelopes
+Q15_MAX  = 32767
+DAC_MID  = 128                  # 8'd128 idle code (offset-binary)
+DAC_AMP  = 127                  # ±127 swing around DAC_MID
+
+# Output directory: FPGA RTL root (.mem files live alongside the .v files)
 MEM_DIR = os.path.join(os.path.dirname(os.path.abspath(__file__)), '..', '..')
 
 
-def generate_full_long_chirp():
-    """
-    Generate the full 3000-sample baseband chirp in Q15.
+# ============================================================================
+# Sample generation — single phase model reused for both TX and RX
+# ============================================================================
+def chirp_phase(n: int, fs: float, t_chirp: float) -> float:
+    """Phase at sample n for the LFM upchirp."""
+    chirp_rate = CHIRP_BW / t_chirp
+    t = n / fs
+    return 2 * math.pi * F_BASEBAND_LOW * t + math.pi * chirp_rate * t * t
 
-    Returns:
-        (chirp_i, chirp_q): lists of 3000 signed 16-bit integers
-    """
-    chirp_rate = CHIRP_BW / T_LONG_CHIRP  # Hz/s
-
-    chirp_i = []
-    chirp_q = []
-
-    for n in range(LONG_CHIRP_SAMPLES):
-        t = n / FS_SYS
-        phase = 2 * math.pi * F_BASEBAND_LOW * t + math.pi * chirp_rate * t * t
-        re_val = round(Q15_MAX * SCALE * math.cos(phase))
-        im_val = round(Q15_MAX * SCALE * math.sin(phase))
-        chirp_i.append(max(-32768, min(32767, re_val)))
-        chirp_q.append(max(-32768, min(32767, im_val)))
 
+def gen_rx_iq(t_chirp: float):
+    """Generate Q15 I/Q samples at fs_sys for one chirp duration."""
+    n_samples = round(t_chirp * FS_SYS)
+    chirp_i, chirp_q = [], []
+    for n in range(n_samples):
+        ph = chirp_phase(n, FS_SYS, t_chirp)
+        re = max(-32768, min(32767, round(Q15_MAX * SCALE * math.cos(ph))))
+        im = max(-32768, min(32767, round(Q15_MAX * SCALE * math.sin(ph))))
+        chirp_i.append(re)
+        chirp_q.append(im)
     return chirp_i, chirp_q
 
 
-def generate_short_chirp():
-    """
-    Generate the 50-sample short chirp in Q15.
-
-    Returns:
-        (chirp_i, chirp_q): lists of 50 signed 16-bit integers
-    """
-    chirp_rate = CHIRP_BW / T_SHORT_CHIRP  # Hz/s (much faster sweep)
-
-    chirp_i = []
-    chirp_q = []
-
-    for n in range(SHORT_CHIRP_SAMPLES):
-        t = n / FS_SYS
-        phase = 2 * math.pi * F_BASEBAND_LOW * t + math.pi * chirp_rate * t * t
-        re_val = round(Q15_MAX * SCALE * math.cos(phase))
-        im_val = round(Q15_MAX * SCALE * math.sin(phase))
-        chirp_i.append(max(-32768, min(32767, re_val)))
-        chirp_q.append(max(-32768, min(32767, im_val)))
-
-    return chirp_i, chirp_q
+def gen_tx_real(t_chirp: float):
+    """Generate 8-bit unsigned offset-binary real samples at fs_dac."""
+    n_samples = round(t_chirp * FS_DAC)
+    samples = []
+    for n in range(n_samples):
+        ph = chirp_phase(n, FS_DAC, t_chirp)
+        # Real-valued upchirp: cos(phase). Map ±1 → 0..255 with 128 as DC.
+        v = round(DAC_AMP * SCALE * math.cos(ph)) + DAC_MID
+        samples.append(max(0, min(255, v)))
+    return samples
 
 
-def to_hex16(value):
-    """Convert signed 16-bit integer to 4-digit hex string (unsigned representation)."""
+# ============================================================================
+# .mem writers
+# ============================================================================
+def to_hex_signed16(value: int) -> str:
+    """Signed 16-bit → 4-char hex (two's complement, lowercase)."""
     if value < 0:
         value += 0x10000
     return f"{value:04x}"
 
 
-def write_mem_file(filename, values):
-    """Write a list of 16-bit signed integers to a .mem file (hex format)."""
+def to_hex_u8(value: int) -> str:
+    """Unsigned 8-bit → 2-char hex (uppercase, matches legacy long_chirp_lut.mem)."""
+    return f"{value:02X}"
+
+
+def write_lines(filename: str, lines):
     path = os.path.join(MEM_DIR, filename)
     with open(path, 'w') as f:
-        for v in values:
-            f.write(to_hex16(v) + '\n')
+        for line in lines:
+            f.write(line + '\n')
+    return path
+
+
+def write_rx_iq_padded(prefix: str, chirp_i, chirp_q, target_len: int = FFT_SIZE,
+                       offset: int = 0):
+    """
+    Write {prefix}_i.mem and {prefix}_q.mem with `target_len` lines.
+    `offset` selects which slice of the chirp to write — used for LONG segmentation.
+    Cells past the chirp end are zero-padded. Cells before the chirp start (impossible
+    here but kept symmetric) are also zero.
+    """
+    i_lines, q_lines = [], []
+    for k in range(target_len):
+        src_idx = k + offset
+        if 0 <= src_idx < len(chirp_i):
+            i_lines.append(to_hex_signed16(chirp_i[src_idx]))
+            q_lines.append(to_hex_signed16(chirp_q[src_idx]))
+        else:
+            i_lines.append('0000')
+            q_lines.append('0000')
+    write_lines(f"{prefix}_i.mem", i_lines)
+    write_lines(f"{prefix}_q.mem", q_lines)
+
+
+def write_tx_lut(filename: str, samples):
+    """Write 8-bit TX LUT — one sample per line, exactly len(samples) lines."""
+    write_lines(filename, [to_hex_u8(v) for v in samples])
+
+
+# ============================================================================
+# main
+# ============================================================================
+def verify_phase_match():
+    """
+    Cross-check that each generated chirp matches the closed-form phase model
+    bit-exactly. radar_scene.py uses the same phase formula and constants;
+    if it ever diverges, this assertion will fire.
+    """
+    for name, t_chirp in [("SHORT", T_SHORT), ("MEDIUM", T_MEDIUM), ("LONG", T_LONG)]:
+        i, q = gen_rx_iq(t_chirp)
+        n_check = min(64, len(i))
+        for n in range(n_check):
+            ph = chirp_phase(n, FS_SYS, t_chirp)
+            ei = max(-32768, min(32767, round(Q15_MAX * SCALE * math.cos(ph))))
+            eq = max(-32768, min(32767, round(Q15_MAX * SCALE * math.sin(ph))))
+            assert i[n] == ei and q[n] == eq, f"{name} phase mismatch at n={n}"
 
 
 def main():
+    verify_phase_match()
 
-    # ---- Long chirp ----
-    long_i, long_q = generate_full_long_chirp()
+    # ---- TX LUTs (8-bit real, fs_dac = 120 MHz) ----
+    write_tx_lut("tx_short_lut.mem",  gen_tx_real(T_SHORT))    # 120 lines
+    write_tx_lut("tx_medium_lut.mem", gen_tx_real(T_MEDIUM))   # 600 lines
+    write_tx_lut("tx_long_lut.mem",   gen_tx_real(T_LONG))     # 3600 lines
 
-    # Verify first sample matches generate_reference_chirp_q15() from radar_scene.py
-    # (which only generates the first 1024 samples)
-
-    # Segment into 4 x 1024 blocks
-    for seg in range(LONG_SEGMENTS):
-        start = seg * FFT_SIZE
-        end = start + FFT_SIZE
-
-        seg_i = []
-        seg_q = []
-        valid_count = 0
-
-        for idx in range(start, end):
-            if idx < LONG_CHIRP_SAMPLES:
-                seg_i.append(long_i[idx])
-                seg_q.append(long_q[idx])
-                valid_count += 1
-            else:
-                seg_i.append(0)
-                seg_q.append(0)
-
-        FFT_SIZE - valid_count
-
-        write_mem_file(f"long_chirp_seg{seg}_i.mem", seg_i)
-        write_mem_file(f"long_chirp_seg{seg}_q.mem", seg_q)
-
-    # ---- Short chirp ----
-    short_i, short_q = generate_short_chirp()
-
-    write_mem_file("short_chirp_i.mem", short_i)
-    write_mem_file("short_chirp_q.mem", short_q)
-
-    # ---- Verification summary ----
-
-    # Self-check: recompute the phase formula and verify the seg0 .mem matches.
-    # radar_scene.py.generate_reference_chirp_q15() uses the same phase form
-    # and the same F_BASEBAND_LOW; the two stay in sync by construction.
-    chirp_rate = CHIRP_BW / T_LONG_CHIRP
-    mismatches = 0
-    for n in range(FFT_SIZE):
-        t = n / FS_SYS
-        phase = 2 * math.pi * F_BASEBAND_LOW * t + math.pi * chirp_rate * t * t
-        expected_i = max(-32768, min(32767, round(Q15_MAX * SCALE * math.cos(phase))))
-        expected_q = max(-32768, min(32767, round(Q15_MAX * SCALE * math.sin(phase))))
-        if long_i[n] != expected_i or long_q[n] != expected_q:
-            mismatches += 1
-
-    if mismatches == 0:
-        pass
-    else:
-        return 1
-
-    # Check magnitude envelope
-    max(math.sqrt(i*i + q*q) for i, q in zip(long_i, long_q, strict=False))
-
-    # Check seg1 zero padding (samples 3000-4095 should be zero)
-    seg1_i_path = os.path.join(MEM_DIR, 'long_chirp_seg1_i.mem')
-    with open(seg1_i_path) as f:
-        seg1_lines = [line.strip() for line in f if line.strip()]
-    # Indices 952..2047 in seg1 (global 3000..4095) should be zero
-    nonzero_tail = sum(1 for line in seg1_lines[952:] if line != '0000')
-
-    if nonzero_tail == 0:
-        pass
-    else:
-        pass
+    # ---- RX I/Q (Q15, fs_sys = 100 MHz, all padded to FFT_SIZE=2048) ----
+    short_i, short_q   = gen_rx_iq(T_SHORT)    # 100 active samples
+    medium_i, medium_q = gen_rx_iq(T_MEDIUM)   # 500 active samples
+    long_i, long_q     = gen_rx_iq(T_LONG)     # 3000 active samples
 
+    write_rx_iq_padded("rx_short",  short_i,  short_q)              # offset=0
+    write_rx_iq_padded("rx_medium", medium_i, medium_q)             # offset=0
+    write_rx_iq_padded("rx_long_seg0", long_i, long_q, offset=0)              # [0..2047]
+    write_rx_iq_padded("rx_long_seg1", long_i, long_q, offset=FFT_SIZE)       # [2048..2999]+pad
 
     return 0
 
diff --git a/9_Firmware/9_2_FPGA/tx_long_lut.mem b/9_Firmware/9_2_FPGA/tx_long_lut.mem
new file mode 100644
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diff --git a/9_Firmware/9_2_FPGA/tx_medium_lut.mem b/9_Firmware/9_2_FPGA/tx_medium_lut.mem
new file mode 100644
index 0000000..f6d46f1
--- /dev/null
+++ b/9_Firmware/9_2_FPGA/tx_medium_lut.mem
@@ -0,0 +1,600 @@
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diff --git a/9_Firmware/9_2_FPGA/tx_short_lut.mem b/9_Firmware/9_2_FPGA/tx_short_lut.mem
new file mode 100644
index 0000000..16483ce
--- /dev/null
+++ b/9_Firmware/9_2_FPGA/tx_short_lut.mem
@@ -0,0 +1,120 @@
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