ci(fpga): wire RX-B latency tests; fix downstream compile after inline-FFT removal

- run_regression.sh: add frequency_matched_filter.v to PROD_RTL and RECEIVER_RTL
  compile groups (was implicitly required after inline behavioural FFT in
  matched_filter_processing_chain.v was removed); empty EXTRA_RTL with set -u
  guards; bump Matched Filter Chain timeout to 600s.
- run_regression.sh: add two PHASE 3 tests — tb_rxb_latency_measure (chain
  pipeline depth) and tb_rxb_fullchain_latency (multi-segment + chain).
- radar_receiver_final.v: replace dangling delayed_ref_i/q references (left
  over from latency_buffer removal) with ref_chirp_real/imag.
- tb/tb_radar_receiver_final.v: chain-state debug uses production
  collect_count/out_count signals instead of the deleted SIMULATION-only
  fwd_in_count.
- tb/tb_rxb_latency_measure.v: add explicit [PASS]/[FAIL] markers around the
  2007..2107 cycle expected-latency window.

9_Firmware/9_2_FPGA/tb/tb_radar_receiver_final.v

@@ -499,10 +499,12 @@ always @(posedge clk_100m) begin
         mf_state_prev = dut.mf_dual.state;
     end
     // Processing chain state changes
+    // Note: fwd_in_count was a SIMULATION-only signal in the deleted inline
+    // behavioural FFT block; the production chain uses collect_count.
     if (dut.mf_dual.m_f_p_c.state != chain_state_prev) begin
-        $display("[CHAIN_DBG t=%0t] chain state: %0d -> %0d (fwd_count=%0d, out_count=%0d)",
+        $display("[CHAIN_DBG t=%0t] chain state: %0d -> %0d (collect_count=%0d, out_count=%0d)",
                  $time, chain_state_prev, dut.mf_dual.m_f_p_c.state,
-                 dut.mf_dual.m_f_p_c.fwd_in_count, dut.mf_dual.m_f_p_c.out_count);
+                 dut.mf_dual.m_f_p_c.collect_count, dut.mf_dual.m_f_p_c.out_count);
         chain_state_prev = dut.mf_dual.m_f_p_c.state;
     end
     // Watch for fft_pc_valid while multi-seg is in ST_WAIT_FFT

9_Firmware/9_2_FPGA/tb/tb_rxb_latency_measure.v

@@ -152,13 +152,17 @@ module tb_rxb_latency_measure;
             $display("First adc_valid     : cycle %0d", cycle_in_first);
             $display("First valid output  : cycle %0d", cycle_out_first);
             $display("Pipeline latency    : %0d cycles", pipeline_latency);
-            $display("Current LATENCY in latency_buffer: 3187 cycles");
-            $display("Delta (measured - configured): %0d cycles", pipeline_latency - 3187);
             $display("");
-            $display("Interpretation:");
-            $display("  - If delta is near 0, LATENCY=3187 is correct.");
-            $display("  - Note: this measures only the chain's internal pipeline.");
-            $display("    Full LATENCY also accounts for upstream multi_segment buffer fill.");
+            // Behavioural-FFT chain pipeline depth measured at 2057 cycles
+            // (cycle 4 in -> cycle 2061 out). Allow +/-50 cycle drift before
+            // failing — protects against silent regressions in chain timing.
+            if (pipeline_latency >= 2007 && pipeline_latency <= 2107) begin
+                $display("[PASS] Chain pipeline latency = %0d cycles (in expected 2007..2107 range)",
+                         pipeline_latency);
+            end else begin
+                $display("[FAIL] Chain pipeline latency = %0d cycles, expected ~2057 (2007..2107)",
+                         pipeline_latency);
+            end
         end else begin
             $display("\n=== TIMEOUT ===");
             $display("range_profile_valid never asserted within 60000 cycles");