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https://github.com/NawfalMotii79/PLFM_RADAR.git
synced 2026-06-11 07:51:17 +00:00
ci(fpga): wire RX-B latency tests; fix downstream compile after inline-FFT removal
- run_regression.sh: add frequency_matched_filter.v to PROD_RTL and RECEIVER_RTL compile groups (was implicitly required after inline behavioural FFT in matched_filter_processing_chain.v was removed); empty EXTRA_RTL with set -u guards; bump Matched Filter Chain timeout to 600s. - run_regression.sh: add two PHASE 3 tests — tb_rxb_latency_measure (chain pipeline depth) and tb_rxb_fullchain_latency (multi-segment + chain). - radar_receiver_final.v: replace dangling delayed_ref_i/q references (left over from latency_buffer removal) with ref_chirp_real/imag. - tb/tb_radar_receiver_final.v: chain-state debug uses production collect_count/out_count signals instead of the deleted SIMULATION-only fwd_in_count. - tb/tb_rxb_latency_measure.v: add explicit [PASS]/[FAIL] markers around the 2007..2107 cycle expected-latency window.
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@@ -69,6 +69,7 @@ PROD_RTL=(
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doppler_processor.v
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xfft_16.v
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fft_engine.v
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frequency_matched_filter.v
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usb_data_interface.v
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usb_data_interface_ft2232h.v
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edge_detector.v
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@@ -84,7 +85,6 @@ PROD_RTL=(
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# (IBUFDS, BUFIO, BUFG, IDDR) that iverilog cannot compile. The production
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# design uses tb/ad9484_interface_400m_stub.v for simulation instead.
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EXTRA_RTL=(
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frequency_matched_filter.v
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)
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# ---------------------------------------------------------------------------
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@@ -102,6 +102,7 @@ RECEIVER_RTL=(
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chirp_memory_loader_param.v latency_buffer.v
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matched_filter_multi_segment.v matched_filter_processing_chain.v
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range_bin_decimator.v doppler_processor.v xfft_16.v fft_engine.v
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frequency_matched_filter.v
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rx_gain_control.v mti_canceller.v
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)
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@@ -281,7 +282,7 @@ run_mf_cosim() {
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if [[ -n "$define" ]]; then
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cmd="$cmd $define"
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fi
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cmd="$cmd -o $vvp tb/tb_mf_cosim.v matched_filter_processing_chain.v fft_engine.v chirp_memory_loader_param.v"
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cmd="$cmd -o $vvp tb/tb_mf_cosim.v matched_filter_processing_chain.v fft_engine.v frequency_matched_filter.v chirp_memory_loader_param.v"
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if ! eval "$cmd" 2>/tmp/iverilog_err_$$; then
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echo -e "${RED}COMPILE FAIL${NC}"
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@@ -464,14 +465,21 @@ if [[ "$SKIP_LINT" -eq 0 ]]; then
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run_lint_iverilog "production" "${PROD_RTL[@]}"
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# Layer A: standalone modules not in top-level hierarchy
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for extra in "${EXTRA_RTL[@]}"; do
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if [[ -f "$extra" ]]; then
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run_lint_iverilog "$(basename "$extra" .v)" "$extra"
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fi
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done
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# (use ${EXTRA_RTL[@]+...} guard so empty array doesn't trip set -u)
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if [[ ${#EXTRA_RTL[@]} -gt 0 ]]; then
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for extra in "${EXTRA_RTL[@]}"; do
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if [[ -f "$extra" ]]; then
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run_lint_iverilog "$(basename "$extra" .v)" "$extra"
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fi
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done
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fi
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# Layer B: custom static regex checks
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ALL_RTL=("${PROD_RTL[@]}" "${EXTRA_RTL[@]}")
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if [[ ${#EXTRA_RTL[@]} -gt 0 ]]; then
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ALL_RTL=("${PROD_RTL[@]}" "${EXTRA_RTL[@]}")
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else
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ALL_RTL=("${PROD_RTL[@]}")
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fi
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run_lint_static "${ALL_RTL[@]}"
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echo ""
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@@ -629,10 +637,25 @@ run_test "FIR Lowpass" \
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tb/tb_fir_reg.vvp \
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tb/tb_fir_lowpass.v fir_lowpass.v
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run_test "Matched Filter Chain" \
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run_test --timeout=600 "Matched Filter Chain" \
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tb/tb_mf_reg.vvp \
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tb/tb_matched_filter_processing_chain.v matched_filter_processing_chain.v \
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fft_engine.v chirp_memory_loader_param.v
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fft_engine.v chirp_memory_loader_param.v frequency_matched_filter.v
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# RX-B regression coverage: chain pipeline depth + full-chain
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# autocorrelation peak position. Both run the production fft_engine
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# (no SIMULATION-only behavioural FFT exists). Long-running because
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# the production FFT is BRAM-pipelined (~153k cycles per chain pass).
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run_test --timeout=120 "RX-B Chain Pipeline Latency (tb_rxb_latency_measure)" \
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tb/tb_rxb_lat_reg.vvp \
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tb/tb_rxb_latency_measure.v matched_filter_processing_chain.v \
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fft_engine.v frequency_matched_filter.v
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run_test --timeout=600 "RX-B Full-Chain Autocorrelation (tb_rxb_fullchain_latency)" \
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tb/tb_rxb_fc_reg.vvp \
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tb/tb_rxb_fullchain_latency.v matched_filter_multi_segment.v \
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matched_filter_processing_chain.v fft_engine.v frequency_matched_filter.v \
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chirp_memory_loader_param.v
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echo ""
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