fix(mcu): F-4.3/4.4 (Option A) — AD9523 PLL1 bypass for first bring-up

The F-4.1+4.2+4.7 patch (ddc0df4) made ad9523_init() run before the
user pdata overrides, which means pll1_bypass_en=0 (the previous
override) is now actually honoured by the driver. Combined with the
fact that pll1_charge_pump_current_nA and pll1_feedback_div were
never set in main.cpp, PLL1 would be expected active but couldn't
lock (CP=0) — ad9523_status() with bypass_en=0 checks PLL1+REFA+REFB
bits, so the failure surfaces, returns -1, and configure_ad9523()
halts boot at main.cpp:1742.

Option A: set pll1_bypass_en=1. VCXO free-runs on its own crystal
stability; ad9523_status() skips PLL1 checks. Boot path is now
clean. Trade-off: VCXO frequency drifts with temperature (~±20 ppm
over -40°C..+85°C for typical XO) — acceptable for first-flight
checkout, but eventual production should re-enable PLL1 (Option B,
deferred to F-4.3/4.4 with measured loop-filter values).

Comment notes the deferral and what's needed before flipping to
bypass=0 (CP current + loop filter rzero tuned to VCXO Kvco).

Regression: 86/0.

9_Firmware/9_1_Microcontroller/9_1_3_C_Cpp_Code/main.cpp

@@ -1479,8 +1479,13 @@ static int configure_ad9523(void)
     pdata.refb_diff_rcv_en = 0;  // REFB 100 MHz single-ended
     pdata.osc_in_diff_en = 0;
 
-    // PLL1: keep bypass disabled so VCXO can be used as reference cleanup if desired
-    pdata.pll1_bypass_en = 0;
+    // PLL1: bypassed for first bring-up — VCXO free-runs. ad9523_status()
+    // skips PLL1/REFA/REFB checks (ad9523.c:262 gates on pll1_bypass_en==0).
+    // F-4.3/4.4 deferred: switching to bypass=0 (PLL1 active, VCXO
+    // disciplined to OCXO REFB) requires pll1_charge_pump_current_nA and
+    // pll1_loop_filter_rzero values tuned against the actual VCXO Kvco
+    // and loop-filter network — design after bench-verified OCXO + VCXO.
+    pdata.pll1_bypass_en = 1;
     pdata.refa_r_div = 1;
     pdata.refb_r_div = 1;