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https://github.com/NawfalMotii79/PLFM_RADAR.git
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fix(fpga): TX-G — surface chirps_mismatch_error to host status
`chirps_mismatch_error` was set in radar_system_top when the host requested chirps_per_elev != Doppler FFT size, but never wired into the USB status response — a latent silent failure. Wired the flag through both USB interfaces (FT601 + FT2232H) into bit [10] of status word 4 (was reserved). GUI parser exposes it as StatusResponse.chirps_mismatch. - usb_data_interface*.v: new status_chirps_mismatch input, packed at [10] - radar_system_top.v: connect chirps_mismatch_error to both USB instances - radar_protocol.py + test_GUI_V65_Tk.py: parse new bit, +1 round-trip test - tb_usb_data_interface.v: drive the new port, update word-4 expectation Tests: GUI 92/92 (was 91), MCU 75/75, USB TB 91/91, ruff clean repo-wide. The 2 remaining FPGA regression failures (Receiver Integration, MF Chain) are the pre-existing iverilog-can't-link-Xilinx-IP issue tracked separately as the open RX-NEW-3 follow-up.
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@@ -147,6 +147,7 @@ class StatusResponse:
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agc_peak_magnitude: int = 0 # 8-bit peak magnitude [7:0]
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agc_saturation_count: int = 0 # 8-bit saturation count [7:0]
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agc_enable: int = 0 # 1-bit AGC enable readback
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chirps_mismatch: int = 0 # TX-G: 1 if FPGA clamped/rejected host chirps_per_elev
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# ============================================================================
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@@ -247,9 +248,9 @@ class RadarProtocol:
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# Word 3: {short_listen[31:16], 10'd0, chirps_per_elev[5:0]}
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sr.chirps_per_elev = words[3] & 0x3F
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sr.short_listen = (words[3] >> 16) & 0xFFFF
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# Word 4: {agc_current_gain[31:28], agc_peak_magnitude[27:20],
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# agc_saturation_count[19:12], agc_enable[11], 9'd0, range_mode[1:0]}
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# Word 4 layout: gain[31:28] peak[27:20] sat[19:12] agc_en[11] mismatch[10] mode[1:0]
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sr.range_mode = words[4] & 0x03
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sr.chirps_mismatch = (words[4] >> 10) & 0x01
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sr.agc_enable = (words[4] >> 11) & 0x01
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sr.agc_saturation_count = (words[4] >> 12) & 0xFF
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sr.agc_peak_magnitude = (words[4] >> 20) & 0xFF
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