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fix(fpga): TX-G — surface chirps_mismatch_error to host status

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`chirps_mismatch_error` was set in radar_system_top when the host
requested chirps_per_elev != Doppler FFT size, but never wired into the
USB status response — a latent silent failure.

Wired the flag through both USB interfaces (FT601 + FT2232H) into bit
[10] of status word 4 (was reserved). GUI parser exposes it as
StatusResponse.chirps_mismatch.

- usb_data_interface*.v: new status_chirps_mismatch input, packed at [10]
- radar_system_top.v: connect chirps_mismatch_error to both USB instances
- radar_protocol.py + test_GUI_V65_Tk.py: parse new bit, +1 round-trip test
- tb_usb_data_interface.v: drive the new port, update word-4 expectation

Tests: GUI 92/92 (was 91), MCU 75/75, USB TB 91/91, ruff clean repo-wide.
The 2 remaining FPGA regression failures (Receiver Integration, MF Chain)
are the pre-existing iverilog-can't-link-Xilinx-IP issue tracked
separately as the open RX-NEW-3 follow-up.
This commit is contained in:
Jason
2026-04-24 11:06:26 +05:45
parent 89dc9156c7
commit ca2b6e527d
6 changed files with 36 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files
9_Firmware/9_2_FPGA/tb/tb_usb_data_interface.v
+6 -2
View File
@@ -69,6 +69,7 @@ module tb_usb_data_interface;
reg [15:0] status_short_listen;
reg [5:0] status_chirps_per_elev;
reg [1:0] status_range_mode;
reg status_chirps_mismatch;
// Self-test status readback inputs
reg [4:0] status_self_test_flags;
@@ -132,6 +133,7 @@ module tb_usb_data_interface;
.status_short_listen (status_short_listen),
.status_chirps_per_elev(status_chirps_per_elev),
.status_range_mode (status_range_mode),
.status_chirps_mismatch(status_chirps_mismatch),
// Self-test status readback
.status_self_test_flags (status_self_test_flags),
@@ -199,6 +201,7 @@ module tb_usb_data_interface;
status_short_listen = 16'd17450;
status_chirps_per_elev = 6'd32;
status_range_mode = 2'b00;
status_chirps_mismatch = 1'b0;
status_self_test_flags = 5'b00000;
status_self_test_detail = 8'd0;
status_self_test_busy = 1'b0;
@@ -921,6 +924,7 @@ module tb_usb_data_interface;
status_short_listen = 16'd17450;
status_chirps_per_elev = 6'd32;
status_range_mode = 2'b10; // Long-range for status test
status_chirps_mismatch = 1'b1; // TX-G: exercise the new bit too
// Self-test status: all 5 tests passed, detail=0xA5, not busy
status_self_test_flags = 5'b11111;
status_self_test_detail = 8'hA5;
@@ -964,8 +968,8 @@ module tb_usb_data_interface;
"Status readback: word 2 = {guard, short_chirp}");
check(uut.status_words[3] === {16'd17450, 10'd0, 6'd32},
"Status readback: word 3 = {short_listen, 0, chirps_per_elev}");
check(uut.status_words[4] === {4'd5, 8'd180, 8'd12, 1'b1, 9'd0, 2'b10},
"Status readback: word 4 = {agc_gain=5, peak=180, sat=12, en=1, range_mode=2}");
check(uut.status_words[4] === {4'd5, 8'd180, 8'd12, 1'b1, 1'b1, 8'd0, 2'b10},
"Status readback: word 4 = {agc_gain=5, peak=180, sat=12, en=1, mismatch=1, range_mode=2}");
// status_words[5] = {7'd0, busy, 8'd0, detail[7:0], 3'd0, flags[4:0]}
// = {7'd0, 1'b0, 8'd0, 8'hA5, 3'd0, 5'b11111}
check(uut.status_words[5] === {7'd0, 1'b0, 8'd0, 8'hA5, 3'd0, 5'b11111},