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feat(gui): PR-R — host control surface fill-in (audit M-2/M-3/M-4/M-6/M-7)

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The RTL has been ahead of the host opcode/widget surface since PR-G:
several runtime knobs (MEDIUM PRI, soft-CFAR alpha, ADC power-down) are
fully wired in radar_system_top.v but had no enum / spinbox path, so
the operator could only reach them via raw _send_custom_command. This
PR closes the gap for everything except M-5 (status-packet medium PRI
readback, which needs an RTL change to add a status word).

M-2 — Opcode enum gains MEDIUM_CHIRP=0x17, MEDIUM_LISTEN=0x18,
       CFAR_ALPHA_SOFT=0x2D. Truth-table docstring refreshed.
       Two new spinboxes in Waveform Timing ("Medium Chirp Cycles",
       "Medium Listen Cycles") with the V2 defaults 500 / 15600 (5 us
       chirp, 161 us PRI). One new spinbox in Detection (CFAR)
       ("CFAR Alpha Soft (Q4.4)") with the RP_DEF_CFAR_ALPHA_SOFT=0x18
       default.

M-3 — ADC_PWDN=0x32 added to the enum (was previously commented as
       "reserved for S-25"; the fix landed at radar_system_top.v:1152
       routing to the physical adc_pwdn pin). New "ADC (AD9484)"
       group on the right column with two buttons: ADC Normal (0x32=0)
       and ADC Power Down (0x32=1). Buttons rather than a spinbox
       prevent accidental non-{0,1} values.

M-4 — ADC_FORMAT widget added to the same ADC group: a 2-choice combo
       ("Offset-binary (SJ1 1-2)" vs "Two's-complement (SJ1 2-3)") with
       a Set button, since AD9484 SPI is tied off (CSB high) and the
       only way to flip sign convention is via this opcode.

M-6 — Replay opcode dispatch in _dispatch_to_software_fpga() expanded:
       SoftwareFPGA gains cfar_alpha_soft mirror + setter; 0x2D wired
       through. RTL-only opcodes (chirp timing, range mode, ADC strap,
       self-test, status_request) are no longer silently dropped — they
       log at info-level "acknowledged (no effect on replay — RTL-only
       state)" so the operator gets visible feedback.

M-7 — Chirps Per Elevation widget default 32 -> 48; hint changed from
       "1-32, clamped" to "must be 48 (RTL clamps)". RTL latches
       chirps_mismatch_error in status word 4 bit 10 for any value != 48
       since PR-F. Bonus: SHORT defaults bumped 50/17450 -> 100/17400 to
       match RP_DEF_SHORT_*_CYCLES_V2 (PR-E 1-us SHORT chirp width).

Tests: +10 (TestOpcodeEnumFillIn 5, TestSoftwareFpgaCfarAlphaSoft 2,
       TestReplayOpcodeDispatch 3). 247/247 PASS. Ruff clean.

M-5 (status packet medium_chirp/medium_listen readback) deferred —
needs an RTL change to extend status_words from 7 to 8 (current word 3
has only 10 reserved bits, not enough for two 16-bit fields).
This commit is contained in:
Jason
2026-05-02 17:03:09 +05:45
parent 115c5f0778
commit c2637251b0
4 changed files with 198 additions and 32 deletions
Download Patch File Download Diff File Expand all files Collapse all files
9_Firmware/9_3_GUI/radar_protocol.py
+30 -17
View File
@@ -111,17 +111,19 @@ class Opcode(IntEnum):
"""Host register opcodes — must match radar_system_top.v case(usb_cmd_opcode).
FPGA truth table (from radar_system_top.v opcode dispatch case-block):
0x01 host_radar_mode 0x16 host_gain_shift
0x02 host_trigger_pulse 0x17 host_medium_chirp_cycles (M-2 — no enum yet)
0x03 host_detect_threshold 0x18 host_medium_listen_cycles (M-2 — no enum yet)
0x04 host_stream_control 0x20 host_range_mode
0x10 host_long_chirp_cycles 0x21-0x27 CFAR / MTI / DC-notch
0x11 host_long_listen_cycles 0x28-0x2C AGC control
0x12 host_guard_cycles 0x2D host_cfar_alpha_soft (M-2 — no enum yet)
0x13 host_short_chirp_cycles 0x30 host_self_test_trigger
0x14 host_short_listen_cycles 0x31/0xFF host_status_request
0x15 host_chirps_per_elev 0x32 host_adc_pwdn (M-3 — no enum yet)
0x33 host_adc_format (AD9484 SCLK/DFS strap; AUDIT-C3)
0x01 host_radar_mode 0x20 host_range_mode
0x02 host_trigger_pulse 0x21-0x27 CFAR / MTI / DC-notch
0x03 host_detect_threshold 0x28-0x2C AGC control
0x04 host_stream_control 0x2D host_cfar_alpha_soft
0x10 host_long_chirp_cycles 0x30 host_self_test_trigger
0x11 host_long_listen_cycles 0x31/0xFF host_status_request
0x12 host_guard_cycles 0x32 host_adc_pwdn
0x13 host_short_chirp_cycles 0x33 host_adc_format
0x14 host_short_listen_cycles
0x15 host_chirps_per_elev
0x16 host_gain_shift
0x17 host_medium_chirp_cycles (PR-G G2)
0x18 host_medium_listen_cycles (PR-G G2)
"""
# --- Basic control (0x01-0x04) ---
RADAR_MODE = 0x01 # 2-bit mode select
@@ -132,13 +134,17 @@ class Opcode(IntEnum):
# --- Digital gain (0x16) ---
GAIN_SHIFT = 0x16 # 4-bit digital gain shift
# --- Chirp timing (0x10-0x15) ---
# --- Chirp timing (0x10-0x18) ---
LONG_CHIRP = 0x10
LONG_LISTEN = 0x11
GUARD = 0x12
SHORT_CHIRP = 0x13
SHORT_LISTEN = 0x14
CHIRPS_PER_ELEV = 0x15
# PR-G G2 / PR-Q.1: MEDIUM ladder. Defaults RP_DEF_MEDIUM_*_CYCLES_V2 give
# PRI = 161 us so the 3-PRI CRT unfolder has 3 distinct PRIs (175/161/167).
MEDIUM_CHIRP = 0x17
MEDIUM_LISTEN = 0x18
# --- Signal processing (0x20-0x27) ---
RANGE_MODE = 0x20
@@ -157,18 +163,25 @@ class Opcode(IntEnum):
AGC_DECAY = 0x2B
AGC_HOLDOFF = 0x2C
# --- 2-tier CFAR soft threshold (0x2D, PR-G G1) ---
# 8-bit Q4.4 alpha for the soft (CAND) tier of the 2-class CFAR. Default
# RP_DEF_CFAR_ALPHA_SOFT = 0x18 (1.5 in Q4.4) corresponds to ~Pfa 1e-5.
CFAR_ALPHA_SOFT = 0x2D
# --- Board self-test / status (0x30-0x31, 0xFF) ---
SELF_TEST_TRIGGER = 0x30
SELF_TEST_STATUS = 0x31
STATUS_REQUEST = 0xFF
# --- AD9484 ADC sign-convention (0x33, AUDIT-C3) ---
# 2'b00 = offset-binary (default; SJ1 jumper pins 1-2 bridged)
# 2'b01 = two's-complement (SJ1 jumper pins 2-3 bridged)
# --- AD9484 ADC power + sign convention (0x32, 0x33; AUDIT-C3 / S-25) ---
# 0x32 ADC_PWDN: 1-bit power-down driving the AD9484 PWDN pin
# (radar_system_top.v -> physical adc_pwdn). 0=normal, 1=PD.
# 0x33 ADC_FORMAT: 2'b00 = offset-binary (SJ1 pins 1-2 bridged, default),
# 2'b01 = two's-complement (SJ1 pins 2-3 bridged).
# AD9484 CSB is hard-tied HIGH on the Main Board (SPI unavailable);
# this opcode lets the host adapt the DDC to the physical strap
# 0x33 lets the host adapt the DDC sign convention to the physical strap
# without rebuilding the bitstream.
# (Opcode 0x32 is reserved for the future AUDIT-S25 adc_pwdn fix.)
ADC_PWDN = 0x32
ADC_FORMAT = 0x33