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fix(fpga): PR-O.8 — cfg_tdata 24->16 for Pipelined Streaming I/O

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PR-O in 8541443 packed cfg_tdata using PG109 Burst I/O semantics (22-bit
SCALE_SCH, 24-bit total). The xfft_2048 IP we instantiate is Pipelined
Streaming I/O — that arch has SCALE_SCH width = 2*ceil(NFFT_MAX/2) = 12
bits, cfg_tdata = 16 bits. Mismatch surfaced when the Vivado-regenerated
.xci reported C_S_AXIS_CONFIG_TDATA_WIDTH=16. Realigns wrappers + TBs.

Total /N scaling preserved: 22'h155555 (/N as 11 stages of >>1) becomes
12'hAA9 (stage 1 alone >>1 + stages 2-11 grouped as 5 pairs of >>2 each).
Iverilog fft_engine.v fallback unchanged — applies fixed >>>1 per stage.

Verified: tb_fft_engine_axi_bridge 4/4, tb_matched_filter_processing_chain
40/40. Vivado .dcp / .veo regenerated from .xci; gitignored as usual.
This commit is contained in:
Jason
2026-05-02 10:08:00 +05:45
parent 8541443c64
commit af64b0952e
6 changed files with 62 additions and 69 deletions
Download Patch File Download Diff File Expand all files Collapse all files
9_Firmware/9_2_FPGA/tb/tb_fft_engine_axi_bridge.v
+3 -2
View File
@@ -319,14 +319,15 @@ endmodule
// ============================================================================
// Stub xfft_2048 — replaces the production wrapper for this TB.
// AUDIT-C10/C-8: cfg_tdata is 24-bit in scaled mode; tuser dropped with BFP.
// AUDIT-C10/C-8 + PR-O.8: cfg_tdata is 16-bit in scaled mode (PG109 Pipelined
// Streaming I/O); tuser dropped with BFP.
// PR-O.7: AXIS data widened to 64-bit packed {Q[31:0], I[31:0]} so the IFFT
// can carry the conjugate-mult Q30 product end-to-end.
// ============================================================================
module xfft_2048 (
input wire aclk,
input wire aresetn,
input wire [23:0] s_axis_config_tdata,
input wire [15:0] s_axis_config_tdata,
input wire s_axis_config_tvalid,
output wire s_axis_config_tready,
input wire [63:0] s_axis_data_tdata,
9_Firmware/9_2_FPGA/tb/tb_xfft_2048_xsim.v
+8 -6
View File
@@ -32,10 +32,12 @@ module tb_xfft_2048_xsim;
reg aclk = 0;
reg aresetn = 0;
// AUDIT-C10/C-8: cfg_tdata widened to 24 bits (scaled mode SCALE_SCH+FWD/INV).
// PR-O.7: data AXIS widened to 64-bit packed {Q[31:0], I[31:0]} —
// matches the regenerated xfft_2048_ip with input_width=32.
reg [23:0] cfg_tdata;
// AUDIT-C10/C-8 + PR-O.8: cfg_tdata is 16 bits (scaled mode + Pipelined
// Streaming I/O — SCALE_SCH width = 2*ceil(NFFT_MAX/2) = 12 bits + 1 bit
// FWD/INV + 3 bits padding). PR-O.7: data AXIS widened to 64-bit
// packed {Q[31:0], I[31:0]} — matches the Vivado-regenerated
// xfft_2048_ip with input_width=32.
reg [15:0] cfg_tdata;
reg cfg_tvalid;
wire cfg_tready;
@@ -101,8 +103,8 @@ module tb_xfft_2048_xsim;
input fwd;
begin
@(posedge aclk);
// {pad[0], SCALE_SCH[21:0], FWD/INV[0]} — see radar_params.vh
cfg_tdata <= {1'b0, `RP_FFT_SCALE_SCH, fwd};
// {pad[2:0], SCALE_SCH[11:0], FWD/INV[0]} — see radar_params.vh
cfg_tdata <= {3'b0, `RP_FFT_SCALE_SCH, fwd};
cfg_tvalid <= 1'b1;
@(posedge aclk);
while (!cfg_tready) @(posedge aclk);