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https://github.com/NawfalMotii79/PLFM_RADAR.git
synced 2026-06-09 15:07:14 +00:00
feat(fpga,mcu,gui): PR-AB.b — drift-free dwell sync via DIG_6 frame_pulse + AGC always-on policy
FPGA (Phase 1+2): - gpio_dig6 (PD14) now carries chirp_scheduler frame_pulse, FPGA-stretched to ~100 ns so the STM32 EXTI on PD14 can latch reliably. - gpio_dig7 (PD15) returns to its pre-PR-AB.b role: control-fault OR (range_decim_watchdog | CDC overrun); MCU stuck-high sampler unchanged. - rx_range_decim_watchdog gains a sticky in source clock domain so a slow status poll cannot miss a 1-cycle assertion (Phase 1). - New tb_dig6_frame_pulse.v (13 checks); tb_status_words_stickies.v extended with DIG_7 fault-OR coverage (14 checks); retired tb_audit_s10_gpio_split.v. - Port comments in radar_system_top.v / _50t.v and XDC roles refreshed. MCU (Phase 3): - PD14 reconfigured to GPIO_MODE_IT_RISING + GPIO_PULLDOWN; new EXTI15_10_IRQHandler in stm32f7xx_it.c dispatches to HAL_GPIO_EXTI_Callback that bumps a volatile g_frame_pulse_count. - runRadarPulseSequence dwell loop replaces 3x HAL_Delay(8) with waitForFramePulse(20) — per-pattern dwell now tracks the actual mask-aware ladder length (drift-free, mask-aware), with a 20 ms timeout safety net. - AGC outer loop is ALWAYS-ON in production (compile-time policy); bench builds compile the body out via -DMCU_AGC_FORCE_DISABLED. The runtime enable/debounce + DIG_6 polling that previously gated AGC are removed. - main.h adds FPGA_FRAME_PULSE_* aliases pointing at FPGA_DIG6_*. GUI (Phase 4): - Settings tab gains a Bench / Diagnostics group with a BENCH-MODE checkbox (off by default, persisted via QSettings). - AGC group header swaps between a green "AGC: ALWAYS-ON" badge (production) and Enable/Disable AGC buttons (bench), pinned to the top of the group. The redundant 0/1 spinbox row for opcode 0x28 is removed — buttons send the same opcode and cannot accept invalid input. - Both the FPGA Control AGC Status box and the AGC Monitor strip share a helper that honours bench-mode in production (always shows ALWAYS-ON in green so the two views never disagree with the badge). - _add_fpga_param_row uses setFixedWidth on label and Set button + explicit stretch=1 on the hint, so all rows align column-wise whether they sit directly in a QVBoxLayout or inside a wrapper QWidget. Regression: FPGA 42/0/0 (PR-M.4 baseline) - MCU 34/34 - GPS extended 51/51 - GUI v7 150/150 - BENCH-MODE flip behaviorally verified. Hardware-blocked steps deferred: bench-scope verify (PD14 dwell pulse, counter advance, PD15 stuck-high recovery still triggers). Closes #182.
This commit is contained in:
Jason
@@ -212,6 +212,25 @@ void OTG_FS_IRQHandler(void)
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/* USER CODE END OTG_FS_IRQn 1 */
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}
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/**
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* @brief This function handles EXTI lines [15:10] interrupts.
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*
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* PR-AB.b: PD14 (FPGA frame_pulse / DIG_6) is the only EXTI source on lines
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* 10-15. HAL_GPIO_EXTI_IRQHandler clears the pending bit and dispatches to
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* HAL_GPIO_EXTI_Callback in main.cpp, which increments g_frame_pulse_count
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* to release the runRadarPulseSequence dwell loop.
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*/
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void EXTI15_10_IRQHandler(void)
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{
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/* USER CODE BEGIN EXTI15_10_IRQn 0 */
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/* USER CODE END EXTI15_10_IRQn 0 */
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HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_14);
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/* USER CODE BEGIN EXTI15_10_IRQn 1 */
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/* USER CODE END EXTI15_10_IRQn 1 */
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}
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/* USER CODE BEGIN 1 */
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/* USER CODE END 1 */
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@@ -300,6 +300,25 @@ void systemPowerUpSequence();
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void systemPowerDownSequence();
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void initializeBeamMatrices();
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void runRadarPulseSequence();
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/* PR-AB.b: FPGA chirp_scheduler frame_pulse (DIG_6 / PD14, ~100 ns stretched)
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* is wired to EXTI15_10. Each rising edge bumps g_frame_pulse_count from the
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* ISR; the dwell loop in runRadarPulseSequence waits for the counter to
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* advance instead of HAL_Delay-padding, so per-pattern dwell tracks the
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* actual mask-aware ladder length (drift-free, mask-aware). The ladder is
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* ~8 ms; we use a 20 ms timeout so a missed pulse cannot stall the loop. */
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static volatile uint32_t g_frame_pulse_count = 0;
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static inline void waitForFramePulse(uint32_t timeout_ms)
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{
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uint32_t prev = g_frame_pulse_count;
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uint32_t t0 = HAL_GetTick();
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while (g_frame_pulse_count == prev) {
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if ((HAL_GetTick() - t0) >= timeout_ms) {
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return; // timeout — caller continues; missed-pulse degrades to wall-clock cadence
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}
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}
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}
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/* F-2.1: executeChirpSequence() removed. The MCU is no longer in the chirp
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* dispatch path -- production runs FPGA mode 2'b01 (auto-scan) where
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* chirp_scheduler.v owns chirp timing and adar_tr_x. See runRadarPulseSequence
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@@ -376,6 +395,17 @@ extern "C" {
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USBD_CDC_SetRxBuffer(&hUsbDeviceFS, &usb_rx_buffer[0]);
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USBD_CDC_ReceivePacket(&hUsbDeviceFS);
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}
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// PR-AB.b: EXTI callback for FPGA frame_pulse on PD14 (DIG_6).
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// EXTI15_10_IRQHandler in stm32f7xx_it.c calls HAL_GPIO_EXTI_IRQHandler,
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// which dispatches here. Bumping g_frame_pulse_count releases the dwell
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// loop's waitForFramePulse spin. PD15 (DIG_7 fault flag) stays polled
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// by checkSystemHealth — no EXTI on that line.
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void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) {
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if (GPIO_Pin == FPGA_FRAME_PULSE_Pin) {
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g_frame_pulse_count++;
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}
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}
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}
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void systemPowerUpSequence() {
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@@ -577,25 +607,26 @@ void runRadarPulseSequence() {
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* reference; if multiple per-pos broadside frames are ever needed
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* they should re-enter behind a runtime switch.
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*
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* Per-pattern dwell:
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* Per-pattern dwell tracks the actual chirp_scheduler ladder length
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* (drift-free, mask-aware) by waiting on the FPGA frame_pulse on
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* DIG_6 / PD14 — see waitForFramePulse + HAL_GPIO_EXTI_Callback above.
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* Nominal ladder is:
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* 16 × PRI_SHORT (175 us) +
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* 16 × PRI_MEDIUM (161 us) +
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* 16 × PRI_LONG (167 us) = 8048 us per ladder, rounded to 8 ms.
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* HAL_Delay yields to SysTick / IRQs, so unlike the removed
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* executeChirpSequence busy-loop the MCU stays responsive to USB CDC,
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* UART, and I2C peripherals during the dwell. For drift-immune sync
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* we'd wait on an FPGA `subframe_pulse` GPIO instead — DIG_7
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* (H12→PD15) is wired in the schematic but currently driven by the
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* F-6.4 watchdog OR; reassigning it is a tracked follow-up
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* (PR-AB.b). */
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static const uint32_t BEAM_PATTERN_DWELL_MS = 8u;
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* 16 × PRI_LONG (167 us) = 8048 us
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* but with subframe_enable masking a single PRI it can drop to ~2.7 ms,
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* which a fixed HAL_Delay(8) used to over-pad. The 20 ms timeout below
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* is a safety floor — if a frame_pulse ever goes missing (FPGA reset,
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* PD14 disconnected) the loop degrades to wall-clock cadence rather
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* than hanging. */
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static const uint32_t FRAME_PULSE_TIMEOUT_MS = 20u;
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// One broadside (vector_0) reference frame per azimuth — replaces the
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// 15 in-loop fires that PR-AB.a removed.
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DIAG("SYS", "Broadside reference (vector_0) — 1× per azimuth");
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adarManager.setCustomBeamPattern16(vector_0, ADAR1000Manager::BeamDirection::TX);
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adarManager.setCustomBeamPattern16(vector_0, ADAR1000Manager::BeamDirection::RX);
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HAL_Delay(BEAM_PATTERN_DWELL_MS);
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waitForFramePulse(FRAME_PULSE_TIMEOUT_MS);
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m += m_max/2;
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for(int beam_pos = 0; beam_pos < 15; beam_pos++) {
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@@ -604,13 +635,13 @@ void runRadarPulseSequence() {
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// Pattern 1: matrix1 (negative-θ scan, peak at -62°..-3°)
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adarManager.setCustomBeamPattern16(matrix1[beam_pos], ADAR1000Manager::BeamDirection::TX);
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adarManager.setCustomBeamPattern16(matrix1[beam_pos], ADAR1000Manager::BeamDirection::RX);
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HAL_Delay(BEAM_PATTERN_DWELL_MS);
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waitForFramePulse(FRAME_PULSE_TIMEOUT_MS);
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m += m_max/2;
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// Pattern 2: matrix2 (positive-θ scan, peak at +3°..+62°)
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adarManager.setCustomBeamPattern16(matrix2[beam_pos], ADAR1000Manager::BeamDirection::TX);
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adarManager.setCustomBeamPattern16(matrix2[beam_pos], ADAR1000Manager::BeamDirection::RX);
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HAL_Delay(BEAM_PATTERN_DWELL_MS);
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waitForFramePulse(FRAME_PULSE_TIMEOUT_MS);
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m += m_max/2;
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// Reset chirp counter if needed
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@@ -1718,6 +1749,17 @@ int main(void)
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DIAG("SYS", "DWT cycle counter initialized, TIM1 started");
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DIAG("SYS", "HAL tick at init start: %lu ms", (unsigned long)HAL_GetTick());
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/* PR-AB.b: production AGC policy is ALWAYS-ON. Bench builds compile this
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* out via -DMCU_AGC_FORCE_DISABLED so engineers can drive the ADAR VGA
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* by hand. Default class state is enabled=false (see ADAR1000_AGC ctor),
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* so we have to flip it here for the production polling loop to do work. */
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#ifndef MCU_AGC_FORCE_DISABLED
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outerAgc.enabled = true;
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DIAG("AGC", "Outer-loop AGC ALWAYS-ON (production policy)");
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#else
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DIAG("AGC", "Outer-loop AGC compiled out (MCU_AGC_FORCE_DISABLED bench build)");
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#endif
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/* MCU-A4: skip the full 180 s OCXO warmup on warm restart. BKPSRAM
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* survives MCU-only resets (IWDG, SYSRESETREQ, brown-out) so the warmup
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* flag from the previous boot tells us the OCXO oven is still hot and
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@@ -2582,30 +2624,23 @@ int main(void)
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runRadarPulseSequence();
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/* [AGC] Outer-loop AGC: sync enable from FPGA via DIG_6 (PD14),
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* then read saturation flag (DIG_5 / PD13) and adjust ADAR1000 VGA
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* common gain once per radar frame (~258 ms).
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* FPGA register host_agc_enable is the single source of truth —
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* DIG_6 propagates it to MCU every frame.
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* 2-frame confirmation debounce: only change outerAgc.enabled when
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* two consecutive frames read the same DIG_6 value. Prevents a
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* single-sample glitch from causing a spurious AGC state transition.
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* Added latency: 1 extra frame (~258 ms), acceptable for control plane. */
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/* [AGC] Outer-loop AGC: read saturation flag (DIG_5 / PD13) once per
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* radar frame and adjust the ADAR1000 VGA common gain. PR-AB.b
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* repurposed DIG_6 to carry the FPGA frame_pulse, so the runtime
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* enable/debounce path is gone — production firmware runs AGC
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* unconditionally (always-on policy). Bench builds compile this body
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* out by defining MCU_AGC_FORCE_DISABLED, which lets engineers drive
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* the ADAR VGA manually via adarManager / GUI gain widgets without
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* the AGC fighting them. The host opcode-0x28 register stays plumbed
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* for telemetry display; the MCU just no longer reads it. */
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#ifndef MCU_AGC_FORCE_DISABLED
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{
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bool dig6_now = (HAL_GPIO_ReadPin(FPGA_DIG6_GPIO_Port,
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FPGA_DIG6_Pin) == GPIO_PIN_SET);
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static bool dig6_prev = false; // matches boot default (AGC off)
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if (dig6_now == dig6_prev) {
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outerAgc.enabled = dig6_now;
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}
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dig6_prev = dig6_now;
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}
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if (outerAgc.enabled) {
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bool sat = HAL_GPIO_ReadPin(FPGA_DIG5_SAT_GPIO_Port,
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FPGA_DIG5_SAT_Pin) == GPIO_PIN_SET;
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outerAgc.update(sat);
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outerAgc.applyGain(adarManager);
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}
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#endif
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/* [GAP-3 FIX 2] Kick hardware watchdog — if we don't reach here within
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* ~4 s, the IWDG resets the MCU automatically. */
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@@ -3143,12 +3178,30 @@ static void MX_GPIO_Init(void)
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
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HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
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/*Configure GPIO pins : PD13 PD14 PD15 */
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GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15;
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/*Configure GPIO pins : PD13 PD15 — polled inputs
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* PD13 (FPGA_DIG5_SAT): saturation flag for AGC outer loop
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* PD15 (FPGA_DIG7): control-fault OR, polled by checkSystemHealth */
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GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_15;
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GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
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/*Configure GPIO pin : PD14 — PR-AB.b FPGA frame_pulse, EXTI rising edge.
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* Pulldown so a disconnected FPGA can't ring the line and starve the dwell
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* loop with phantom pulses (the FPGA-side stretcher drives 3.3V CMOS active
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* high for ~100 ns). NVIC enable below routes EXTI15_10_IRQn to the
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* handler in stm32f7xx_it.c. */
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GPIO_InitStruct.Pin = FPGA_FRAME_PULSE_Pin;
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GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
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GPIO_InitStruct.Pull = GPIO_PULLDOWN;
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HAL_GPIO_Init(FPGA_FRAME_PULSE_GPIO_Port, &GPIO_InitStruct);
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/* Priority below USB_OTG_FS (0) and SysTick — frame_pulse ISR is short
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* (one volatile increment) and a couple of ms of jitter is invisible to
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* the dwell loop, so it doesn't need top priority. */
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HAL_NVIC_SetPriority(FPGA_FRAME_PULSE_EXTI_IRQn, 5, 0);
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HAL_NVIC_EnableIRQ(FPGA_FRAME_PULSE_EXTI_IRQn);
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/*Configure GPIO pins : ADF4382_RX_LKDET_Pin ADF4382_TX_LKDET_Pin */
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GPIO_InitStruct.Pin = ADF4382_RX_LKDET_Pin|ADF4382_TX_LKDET_Pin;
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GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
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@@ -142,7 +142,14 @@ void Error_Handler(void);
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#define EN_DIS_COOLING_Pin GPIO_PIN_7
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#define EN_DIS_COOLING_GPIO_Port GPIOD
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/* FPGA digital I/O (directly connected GPIOs) */
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/* FPGA digital I/O (directly connected GPIOs)
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* DIG_5 (PD13): signal-saturation flag — input, polled by AGC outer loop
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* (gated by !MCU_AGC_FORCE_DISABLED).
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* DIG_6 (PD14): chirp_scheduler frame_pulse, ~100 ns FPGA-stretched —
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* EXTI rising + pulldown; ISR increments g_frame_pulse_count
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* (PR-AB.b drift-free dwell sync).
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* DIG_7 (PD15): control-fault OR (range_decim_watchdog | CIC→FIR overrun) —
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* polled by checkSystemHealth stuck-high sampler. */
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#define FPGA_DIG5_SAT_Pin GPIO_PIN_13
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#define FPGA_DIG5_SAT_GPIO_Port GPIOD
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#define FPGA_DIG6_Pin GPIO_PIN_14
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@@ -150,6 +157,11 @@ void Error_Handler(void);
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#define FPGA_DIG7_Pin GPIO_PIN_15
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#define FPGA_DIG7_GPIO_Port GPIOD
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/* PR-AB.b: alias names that match the post-Phase-3 role of DIG_6. */
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#define FPGA_FRAME_PULSE_Pin FPGA_DIG6_Pin
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#define FPGA_FRAME_PULSE_GPIO_Port FPGA_DIG6_GPIO_Port
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#define FPGA_FRAME_PULSE_EXTI_IRQn EXTI15_10_IRQn
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#define ADF4382_RX_CE_Pin GPIO_PIN_9
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#define ADF4382_RX_CE_GPIO_Port GPIOG
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#define ADF4382_RX_CS_Pin GPIO_PIN_10
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@@ -50,7 +50,7 @@ static void test_defaults()
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assert(agc.min_gain == 0);
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assert(agc.max_gain == 127);
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assert(agc.holdoff_frames == 4);
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assert(agc.enabled == false); // disabled by default — FPGA DIG_6 is source of truth
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assert(agc.enabled == false); // class default; main.cpp flips this on under !MCU_AGC_FORCE_DISABLED
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assert(agc.holdoff_counter == 0);
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assert(agc.last_saturated == false);
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assert(agc.saturation_event_count == 0);
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