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test(fpga): C-3 — align DDC ADC format test with exact conversion

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Jason
2026-05-09 14:07:54 +05:45
parent 21bf7a0228
commit a718e00475
1 changed files with 10 additions and 10 deletions
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9_Firmware/9_2_FPGA/tb/tb_ddc_400m.v
+10 -10
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@@ -233,9 +233,9 @@ module tb_ddc_400m;
// the wire is internal to the DUT. // the wire is internal to the DUT.
// //
// Expected pre-DSP values (MIXER_WIDTH=18, ADC_WIDTH=8): // Expected pre-DSP values (MIXER_WIDTH=18, ADC_WIDTH=8):
// format=00 (offset-binary), adc=0x80 -> +256 (mid-scale ≈ 0V) // format=00 (offset-binary), adc=0x80 -> 0 (mid-scale 0V)
// format=00 (offset-binary), adc=0x00 -> -65280 (full negative) // format=00 (offset-binary), adc=0x00 -> -65536 (full negative)
// format=00 (offset-binary), adc=0xFF -> +65280 (full positive) // format=00 (offset-binary), adc=0xFF -> +65024 (full positive)
// format=01 (2's-complement), adc=0x00 -> 0 (mid-scale 0V) // format=01 (2's-complement), adc=0x00 -> 0 (mid-scale 0V)
// format=01 (2's-complement), adc=0x80 -> -65536 (full negative) // format=01 (2's-complement), adc=0x80 -> -65536 (full negative)
// format=01 (2's-complement), adc=0x7F -> +65024 (full positive) // format=01 (2's-complement), adc=0x7F -> +65024 (full positive)
@@ -253,20 +253,20 @@ module tb_ddc_400m;
repeat (5) @(posedge clk_400m); // 2-FF sync settle repeat (5) @(posedge clk_400m); // 2-FF sync settle
adc_data = 8'h80; adc_data = 8'h80;
@(posedge clk_400m); #1; @(posedge clk_400m); #1;
check(uut.adc_signed_w === 18'sd256, check(uut.adc_signed_w === 18'sd0,
"format=00 adc=0x80 -> +256 (offset-binary mid-scale)"); "format=00 adc=0x80 -> 0 (offset-binary mid-scale)");
// Offset-binary full negative (adc=0x00) // Offset-binary full negative (adc=0x00)
adc_data = 8'h00; adc_data = 8'h00;
@(posedge clk_400m); #1; @(posedge clk_400m); #1;
check(uut.adc_signed_w === -18'sd65280, check(uut.adc_signed_w === -18'sd65536,
"format=00 adc=0x00 -> -65280 (offset-binary min)"); "format=00 adc=0x00 -> -65536 (offset-binary min)");
// Offset-binary full positive (adc=0xFF) // Offset-binary full positive (adc=0xFF)
adc_data = 8'hFF; adc_data = 8'hFF;
@(posedge clk_400m); #1; @(posedge clk_400m); #1;
check(uut.adc_signed_w === 18'sd65280, check(uut.adc_signed_w === 18'sd65024,
"format=00 adc=0xFF -> +65280 (offset-binary max)"); "format=00 adc=0xFF -> +65024 (offset-binary max)");
// Switch to 2's-complement and let the synchronizer settle // Switch to 2's-complement and let the synchronizer settle
adc_format = 2'b01; adc_format = 2'b01;
@@ -295,7 +295,7 @@ module tb_ddc_400m;
repeat (5) @(posedge clk_400m); repeat (5) @(posedge clk_400m);
adc_data = 8'h80; adc_data = 8'h80;
@(posedge clk_400m); #1; @(posedge clk_400m); #1;
check(uut.adc_signed_w === 18'sd256, check(uut.adc_signed_w === 18'sd0,
"format=10 (reserved) -> offset-binary fallback"); "format=10 (reserved) -> offset-binary fallback");
// Restore default for any later tests // Restore default for any later tests