mirror of
https://github.com/NawfalMotii79/PLFM_RADAR.git
synced 2026-06-10 23:41:18 +00:00
chirp-v2 PR-E: plfm_chirp_controller_v2 + scheduler-driven TX via async-FIFO
Replaces plfm_chirp_controller_enhanced (5-state FSM with hardcoded LONG/SHORT timings + 60-entry inline short LUT) with plfm_chirp_controller_v2, a pure DAC playback driver: IDLE -> CHIRP -> IDLE keyed off a 1-cycle dst_chirp_valid pulse, with sample count selected by dst_wave_sel (SHORT=120 / MEDIUM=600 / LONG=3600). Inter-chirp timing (LISTEN, GUARD, frame boundaries) is now owned exclusively by chirp_scheduler. Scheduler -> TX bridge: cdc_async_fifo (Cummings style #2, WIDTH=2 DEPTH=4) crosses {wave_sel} from clk_100m to clk_120m_dac, with chirp_pulse as src_valid. frame_pulse rides a separate toggle CDC for chirp_counter clear and the new_chirp_frame status output. mixers_enable now also gates the scheduler so it stays in S_IDLE while the radar is "off" — without this gate the first chirp_pulse fires at reset and gets dropped before mixers come up. Files: - NEW plfm_chirp_controller_v2.v DAC playback driver (3 LUTs, FSM) - DEL plfm_chirp_controller.v legacy controller (382 lines) - DEL long_chirp_lut.mem legacy LUT (3600 lines), replaced by tx_long_lut.mem from PR-B - chirp_scheduler.v + mixers_enable input (master quiesce) - radar_receiver_final.v + sched_*_out output ports + mixers_enable_100m - radar_system_top.v wire sched_*_out -> tx_inst.sched_*; pass stm32_mixers_enable_100m to rx_inst - radar_transmitter.v full rewrite: drop new_chirp edge detector + toggle CDC, instantiate cdc_async_fifo for {wave_sel}, toggle CDC for frame_pulse, plfm_chirp_controller_v2 in place of _enhanced - tb/tb_chirp_controller.v + tb/tb_chirp_contract.v rewritten for v2 contract (43/43 unit + 10/10 contract green) - tb/tb_radar_receiver_final.v + .mixers_enable_100m(1'b1) pin - run_regression.sh, scripts/200t/build_200t.tcl file-list bumped Test summary: - tb_chirp_controller_v2: 43/43 PASS - tb_chirp_contract: 10/10 contracts upheld - tb_rxb_fullchain: peak 24033 ~80x (parity with PR-D) - tb_mti_canceller: 43/43 PASS - tb_system_e2e: 33/49 (1 new vs 34/49 PR-D baseline: G2.2 new_chirp_frame, intentional v2 frame-pulse semantics — fires once per Doppler frame instead of once per stm32 chirp toggle. TB needs widening in PR-H to wait the full frame.)
This commit is contained in:
Jason
@@ -1,46 +1,54 @@
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 19:04:35 12/14/2025
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// Design Name:
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// Module Name: radar_transmitter
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module radar_transmitter(
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// System Clocks
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input wire clk_100m, // System clock
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input wire clk_120m_dac, // 120MHz DAC clock
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input wire reset_n, // Reset synchronized to clk_120m_dac
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// radar_transmitter — DAC-side wrapper around plfm_chirp_controller_v2.
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//
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// chirp-v2 PR-E reorganization:
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// chirp_scheduler (clk_100m, in receiver_final) is now the master timekeeper.
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// It emits {wave_sel[1:0], chirp_pulse, frame_pulse} on clk_100m. We bridge
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// them to clk_120m_dac here:
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// - wave_sel + chirp_pulse → cdc_async_fifo (Cummings style #2). Each
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// chirp_pulse pushes wave_sel into the FIFO; the dst-side dst_valid
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// pulse drives plfm_chirp_controller_v2.dst_chirp_valid.
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// - frame_pulse → toggle CDC → 1-cycle pulse on clk_120m_dac for
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// chirp_counter clear and the new_chirp_frame status output.
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//
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// Beam steering:
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// stm32_new_elevation / stm32_new_azimuth still run through edge detectors
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// on clk_100m and feed the controller's internal beam counters. These are
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// independent of the chirp FSM and unchanged from chirp-v1.
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//
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// stm32_new_chirp:
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// Removed from this module — the scheduler in receiver_final now owns chirp
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// timing. The top-level GPIO is still wired to receiver_final via
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// stm32_new_chirp_rx; the transmitter has no separate path.
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//////////////////////////////////////////////////////////////////////////////////
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module radar_transmitter(
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// System Clocks
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input wire clk_100m, // System clock
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input wire clk_120m_dac, // 120MHz DAC clock
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input wire reset_n, // Reset synchronized to clk_120m_dac
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input wire reset_100m_n, // Reset synchronized to clk_100m (for edge detectors/CDC)
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// DAC Interface
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output wire [7:0] dac_data,
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output wire dac_clk,
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output wire dac_sleep,
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output wire rx_mixer_en,
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output wire tx_mixer_en,
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// STM32 Control Interface
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input wire stm32_new_chirp,
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input wire stm32_new_elevation,
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output wire tx_mixer_en,
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// Scheduler outputs from receiver_final (clk_100m domain) — PR-E
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input wire [1:0] sched_wave_sel,
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input wire sched_chirp_pulse,
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input wire sched_frame_pulse,
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// STM32 Control Interface (chirp moved to scheduler; beam-step still here)
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input wire stm32_new_elevation,
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input wire stm32_new_azimuth,
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input wire stm32_mixers_enable,
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output wire fpga_rf_switch,
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// ADAR1000 Control Interface
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input wire stm32_mixers_enable,
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output wire fpga_rf_switch,
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// ADAR1000 Control Interface
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output wire adar_tx_load_1,
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output wire adar_rx_load_1,
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output wire adar_tx_load_2,
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@@ -53,7 +61,7 @@ module radar_transmitter(
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output wire adar_tr_2,
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output wire adar_tr_3,
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output wire adar_tr_4,
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// Level Shifter SPI Interface (STM32F7 to ADAR1000)
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input wire stm32_sclk_3v3,
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input wire stm32_mosi_3v3,
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@@ -62,188 +70,210 @@ module radar_transmitter(
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input wire stm32_cs_adar2_3v3,
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input wire stm32_cs_adar3_3v3,
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input wire stm32_cs_adar4_3v3,
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output wire stm32_sclk_1v8,
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output wire stm32_mosi_1v8,
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input wire stm32_miso_1v8,
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output wire stm32_cs_adar1_1v8,
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output wire stm32_cs_adar2_1v8,
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output wire stm32_cs_adar3_1v8,
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output wire stm32_cs_adar4_1v8,
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// Beam Position Tracking
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output wire [5:0] current_elevation,
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output wire [5:0] current_azimuth,
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output wire [5:0] current_chirp,
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output wire new_chirp_frame
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output wire stm32_cs_adar4_1v8,
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);
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// ========== SPI LEVEL SHIFTER PASSTHROUGH ==========
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// FPGA bridges 3.3V STM32 SPI bus (Bank 15) to 1.8V ADAR1000 SPI bus (Bank 34).
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// The FPGA I/O banks handle the actual voltage translation; these assigns
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// route the signals through the fabric.
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assign stm32_sclk_1v8 = stm32_sclk_3v3;
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assign stm32_mosi_1v8 = stm32_mosi_3v3;
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assign stm32_miso_3v3 = stm32_miso_1v8;
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assign stm32_cs_adar1_1v8 = stm32_cs_adar1_3v3;
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assign stm32_cs_adar2_1v8 = stm32_cs_adar2_3v3;
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assign stm32_cs_adar3_1v8 = stm32_cs_adar3_3v3;
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assign stm32_cs_adar4_1v8 = stm32_cs_adar4_3v3;
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// Edge Detection Signals
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wire new_chirp_pulse;
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wire new_elevation_pulse;
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wire new_azimuth_pulse;
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// CDC: Synchronized versions of async STM32 GPIO inputs to clk_100m
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wire stm32_new_chirp_sync;
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wire stm32_new_elevation_sync;
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wire stm32_new_azimuth_sync;
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// CDC: Synchronized versions of signals crossing clk_100m -> clk_120m_dac
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wire mixers_enable_120m; // stm32_mixers_enable sync'd to clk_120m_dac
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wire new_chirp_pulse_120m; // new_chirp_pulse (toggle CDC) in clk_120m_dac domain
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// Chirp Control Signals
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wire [7:0] chirp_data;
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wire chirp_valid;
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wire chirp_sequence_done;
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// Toggle CDC for new_chirp_pulse: clk_100m -> clk_120m_dac
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// Edge detector produces a 1-cycle pulse on clk_100m. A level synchronizer
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// would miss it (120/100 MHz ratio). Toggle CDC converts pulse to level toggle,
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// syncs the toggle, then detects edges on the destination side.
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reg chirp_toggle_100m;
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always @(posedge clk_100m or negedge reset_100m_n) begin
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if (!reset_100m_n)
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chirp_toggle_100m <= 1'b0;
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else if (new_chirp_pulse)
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chirp_toggle_100m <= ~chirp_toggle_100m;
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end
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// Sync the toggle to clk_120m_dac domain
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wire chirp_toggle_120m;
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cdc_single_bit #(.STAGES(3)) cdc_chirp_toggle (
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.src_clk(clk_100m),
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.dst_clk(clk_120m_dac),
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.reset_n(reset_n),
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.src_signal(chirp_toggle_100m),
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.dst_signal(chirp_toggle_120m)
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);
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// Detect edges on synchronized toggle to recover pulse in clk_120m domain
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reg chirp_toggle_120m_prev;
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always @(posedge clk_120m_dac or negedge reset_n) begin
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if (!reset_n)
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chirp_toggle_120m_prev <= 1'b0;
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else
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chirp_toggle_120m_prev <= chirp_toggle_120m;
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end
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assign new_chirp_pulse_120m = chirp_toggle_120m ^ chirp_toggle_120m_prev;
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// Sync stm32_mixers_enable (async GPIO level) to clk_120m_dac domain
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cdc_single_bit #(.STAGES(3)) cdc_mixers_en_120m (
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.src_clk(clk_100m), // Treat as pseudo-source (GPIO is async)
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.dst_clk(clk_120m_dac),
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.reset_n(reset_n),
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.src_signal(stm32_mixers_enable),
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.dst_signal(mixers_enable_120m)
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// Beam Position Tracking
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output wire [5:0] current_elevation,
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output wire [5:0] current_azimuth,
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output wire [5:0] current_chirp,
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output wire new_chirp_frame
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);
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// CDC synchronizers: async STM32 GPIO inputs -> clk_100m domain
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// These prevent metastability in the edge detectors. Without these,
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// the edge detector's first FF can go metastable, and the XOR output
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// can glitch, producing false chirp/elevation/azimuth pulses.
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cdc_single_bit #(.STAGES(2)) cdc_stm32_chirp (
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.src_clk(clk_100m), // Pseudo-source for async GPIO
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.dst_clk(clk_100m),
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.reset_n(reset_100m_n),
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.src_signal(stm32_new_chirp),
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.dst_signal(stm32_new_chirp_sync)
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);
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cdc_single_bit #(.STAGES(2)) cdc_stm32_elevation (
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.src_clk(clk_100m),
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.dst_clk(clk_100m),
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.reset_n(reset_100m_n),
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.src_signal(stm32_new_elevation),
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.dst_signal(stm32_new_elevation_sync)
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);
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cdc_single_bit #(.STAGES(2)) cdc_stm32_azimuth (
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.src_clk(clk_100m),
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.dst_clk(clk_100m),
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.reset_n(reset_100m_n),
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.src_signal(stm32_new_azimuth),
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.dst_signal(stm32_new_azimuth_sync)
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);
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// Enhanced STM32 Input Edge Detection with Debouncing
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// Inputs are now CDC-synchronized (safe from metastability)
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edge_detector_enhanced chirp_edge (
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.clk(clk_100m),
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.reset_n(reset_100m_n),
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.signal_in(stm32_new_chirp_sync),
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.rising_falling_edge(new_chirp_pulse)
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);
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edge_detector_enhanced elevation_edge (
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.clk(clk_100m),
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.reset_n(reset_100m_n),
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.signal_in(stm32_new_elevation_sync),
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.rising_falling_edge(new_elevation_pulse)
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);
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edge_detector_enhanced azimuth_edge (
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.clk(clk_100m),
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.reset_n(reset_100m_n),
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.signal_in(stm32_new_azimuth_sync),
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.rising_falling_edge(new_azimuth_pulse)
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// ========== SPI LEVEL SHIFTER PASSTHROUGH ==========
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// FPGA bridges 3.3V STM32 SPI bus (Bank 15) to 1.8V ADAR1000 SPI bus (Bank 34).
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// The FPGA I/O banks handle the actual voltage translation; these assigns
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// route the signals through the fabric.
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assign stm32_sclk_1v8 = stm32_sclk_3v3;
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assign stm32_mosi_1v8 = stm32_mosi_3v3;
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assign stm32_miso_3v3 = stm32_miso_1v8;
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assign stm32_cs_adar1_1v8 = stm32_cs_adar1_3v3;
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assign stm32_cs_adar2_1v8 = stm32_cs_adar2_3v3;
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assign stm32_cs_adar3_1v8 = stm32_cs_adar3_3v3;
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assign stm32_cs_adar4_1v8 = stm32_cs_adar4_3v3;
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// Beam-step edge detection (STM32 GPIO -> clk_100m pulses)
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wire new_elevation_pulse;
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wire new_azimuth_pulse;
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// CDC: Synchronized versions of async STM32 GPIO inputs to clk_100m
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wire stm32_new_elevation_sync;
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wire stm32_new_azimuth_sync;
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// CDC: stm32_mixers_enable into clk_120m_dac domain
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wire mixers_enable_120m;
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// PR-E: scheduler bridge outputs in clk_120m_dac domain
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wire dst_chirp_valid;
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wire [1:0] dst_wave_sel;
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wire sched_overrun_unused;
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wire frame_pulse_120m;
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// Chirp Control Signals
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wire [7:0] chirp_data;
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wire chirp_valid;
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wire chirp_sequence_done;
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// ============================================================================
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// PR-E: chirp_pulse + wave_sel CDC (clk_100m → clk_120m_dac)
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//
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// Each scheduler chirp_pulse on clk_100m pushes wave_sel into a Gray-coded
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// async FIFO. The dst side auto-drains so dst_chirp_valid is a 1-cycle pulse
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// on clk_120m_dac, and dst_wave_sel carries the matching waveform identity.
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// ============================================================================
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cdc_async_fifo #(
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.WIDTH(2),
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.DEPTH(4)
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) cdc_chirp_fifo (
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.src_clk (clk_100m),
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.dst_clk (clk_120m_dac),
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.src_reset_n (reset_100m_n),
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.dst_reset_n (reset_n),
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.src_data (sched_wave_sel),
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.src_valid (sched_chirp_pulse),
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.dst_data (dst_wave_sel),
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.dst_valid (dst_chirp_valid),
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.overrun (sched_overrun_unused)
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);
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// Enhanced PLFM Chirp Generation
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plfm_chirp_controller_enhanced plfm_chirp_inst (
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.clk_120m(clk_120m_dac),
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.clk_100m(clk_100m),
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.reset_n(reset_n),
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.new_chirp(new_chirp_pulse_120m), // CDC-synchronized pulse in clk_120m domain
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.new_elevation(new_elevation_pulse),
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.new_azimuth(new_azimuth_pulse),
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.new_chirp_frame(new_chirp_frame),
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.mixers_enable(mixers_enable_120m), // CDC-synchronized level in clk_120m domain
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.chirp_data(chirp_data),
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.chirp_valid(chirp_valid),
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.chirp_done(chirp_sequence_done),
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.rf_switch_ctrl(fpga_rf_switch),
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.rx_mixer_en(rx_mixer_en),
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.tx_mixer_en(tx_mixer_en),
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.adar_tx_load_1(adar_tx_load_1),
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.adar_rx_load_1(adar_rx_load_1),
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.adar_tx_load_2(adar_tx_load_2),
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.adar_rx_load_2(adar_rx_load_2),
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.adar_tx_load_3(adar_tx_load_3),
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.adar_rx_load_3(adar_rx_load_3),
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.adar_tx_load_4(adar_tx_load_4),
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.adar_rx_load_4(adar_rx_load_4),
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.adar_tr_1(adar_tr_1),
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.adar_tr_2(adar_tr_2),
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.adar_tr_3(adar_tr_3),
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.adar_tr_4(adar_tr_4),
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.elevation_counter(current_elevation),
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.azimuth_counter(current_azimuth),
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.chirp_counter(current_chirp)
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);
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// Enhanced DAC Interface
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dac_interface_enhanced dac_interface_inst (
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.clk_120m(clk_120m_dac),
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// ============================================================================
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// frame_pulse toggle CDC (clk_100m → clk_120m_dac)
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// ============================================================================
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reg frame_toggle_100m;
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always @(posedge clk_100m or negedge reset_100m_n) begin
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if (!reset_100m_n)
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frame_toggle_100m <= 1'b0;
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else if (sched_frame_pulse)
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frame_toggle_100m <= ~frame_toggle_100m;
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end
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wire frame_toggle_120m;
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cdc_single_bit #(.STAGES(3)) cdc_frame_toggle (
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.src_clk(clk_100m),
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.dst_clk(clk_120m_dac),
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.reset_n(reset_n),
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.chirp_data(chirp_data),
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.src_signal(frame_toggle_100m),
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.dst_signal(frame_toggle_120m)
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);
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reg frame_toggle_120m_prev;
|
||||
always @(posedge clk_120m_dac or negedge reset_n) begin
|
||||
if (!reset_n)
|
||||
frame_toggle_120m_prev <= 1'b0;
|
||||
else
|
||||
frame_toggle_120m_prev <= frame_toggle_120m;
|
||||
end
|
||||
assign frame_pulse_120m = frame_toggle_120m ^ frame_toggle_120m_prev;
|
||||
|
||||
// ============================================================================
|
||||
// stm32_mixers_enable level CDC into clk_120m_dac
|
||||
// ============================================================================
|
||||
cdc_single_bit #(.STAGES(3)) cdc_mixers_en_120m (
|
||||
.src_clk(clk_100m), // Treat as pseudo-source (GPIO is async)
|
||||
.dst_clk(clk_120m_dac),
|
||||
.reset_n(reset_n),
|
||||
.src_signal(stm32_mixers_enable),
|
||||
.dst_signal(mixers_enable_120m)
|
||||
);
|
||||
|
||||
// ============================================================================
|
||||
// Beam-step CDC + edge detection (clk_100m, unchanged from v1)
|
||||
// ============================================================================
|
||||
cdc_single_bit #(.STAGES(2)) cdc_stm32_elevation (
|
||||
.src_clk(clk_100m),
|
||||
.dst_clk(clk_100m),
|
||||
.reset_n(reset_100m_n),
|
||||
.src_signal(stm32_new_elevation),
|
||||
.dst_signal(stm32_new_elevation_sync)
|
||||
);
|
||||
|
||||
cdc_single_bit #(.STAGES(2)) cdc_stm32_azimuth (
|
||||
.src_clk(clk_100m),
|
||||
.dst_clk(clk_100m),
|
||||
.reset_n(reset_100m_n),
|
||||
.src_signal(stm32_new_azimuth),
|
||||
.dst_signal(stm32_new_azimuth_sync)
|
||||
);
|
||||
|
||||
edge_detector_enhanced elevation_edge (
|
||||
.clk(clk_100m),
|
||||
.reset_n(reset_100m_n),
|
||||
.signal_in(stm32_new_elevation_sync),
|
||||
.rising_falling_edge(new_elevation_pulse)
|
||||
);
|
||||
|
||||
edge_detector_enhanced azimuth_edge (
|
||||
.clk(clk_100m),
|
||||
.reset_n(reset_100m_n),
|
||||
.signal_in(stm32_new_azimuth_sync),
|
||||
.rising_falling_edge(new_azimuth_pulse)
|
||||
);
|
||||
|
||||
// ============================================================================
|
||||
// PLFM Chirp Generator (chirp-v2)
|
||||
// ============================================================================
|
||||
plfm_chirp_controller_v2 plfm_chirp_inst (
|
||||
.clk_120m (clk_120m_dac),
|
||||
.clk_100m (clk_100m),
|
||||
.reset_n (reset_n),
|
||||
.reset_100m_n (reset_100m_n),
|
||||
.mixers_enable (mixers_enable_120m),
|
||||
|
||||
// Scheduler bridge (clk_120m_dac, post-CDC)
|
||||
.dst_chirp_valid (dst_chirp_valid),
|
||||
.dst_wave_sel (dst_wave_sel),
|
||||
.frame_pulse_120m(frame_pulse_120m),
|
||||
|
||||
// Beam-step pulses (clk_100m)
|
||||
.new_elevation (new_elevation_pulse),
|
||||
.new_azimuth (new_azimuth_pulse),
|
||||
|
||||
// DAC outputs
|
||||
.chirp_data (chirp_data),
|
||||
.chirp_valid (chirp_valid),
|
||||
.new_chirp_frame(new_chirp_frame),
|
||||
.chirp_done (chirp_sequence_done),
|
||||
.rf_switch_ctrl (fpga_rf_switch),
|
||||
.rx_mixer_en (rx_mixer_en),
|
||||
.tx_mixer_en (tx_mixer_en),
|
||||
|
||||
// ADAR
|
||||
.adar_tx_load_1 (adar_tx_load_1),
|
||||
.adar_rx_load_1 (adar_rx_load_1),
|
||||
.adar_tx_load_2 (adar_tx_load_2),
|
||||
.adar_rx_load_2 (adar_rx_load_2),
|
||||
.adar_tx_load_3 (adar_tx_load_3),
|
||||
.adar_rx_load_3 (adar_rx_load_3),
|
||||
.adar_tx_load_4 (adar_tx_load_4),
|
||||
.adar_rx_load_4 (adar_rx_load_4),
|
||||
.adar_tr_1 (adar_tr_1),
|
||||
.adar_tr_2 (adar_tr_2),
|
||||
.adar_tr_3 (adar_tr_3),
|
||||
.adar_tr_4 (adar_tr_4),
|
||||
|
||||
// Status counters
|
||||
.chirp_counter (current_chirp),
|
||||
.elevation_counter(current_elevation),
|
||||
.azimuth_counter (current_azimuth)
|
||||
);
|
||||
|
||||
// ============================================================================
|
||||
// DAC Output Interface
|
||||
// ============================================================================
|
||||
dac_interface_enhanced dac_interface_inst (
|
||||
.clk_120m (clk_120m_dac),
|
||||
.reset_n (reset_n),
|
||||
.chirp_data (chirp_data),
|
||||
.chirp_valid(chirp_valid),
|
||||
.dac_data(dac_data),
|
||||
.dac_clk(dac_clk),
|
||||
.dac_sleep(dac_sleep)
|
||||
);
|
||||
endmodule
|
||||
.dac_data (dac_data),
|
||||
.dac_clk (dac_clk),
|
||||
.dac_sleep (dac_sleep)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
Reference in New Issue
Block a user