chirp-v2 PR-E: plfm_chirp_controller_v2 + scheduler-driven TX via async-FIFO

Replaces plfm_chirp_controller_enhanced (5-state FSM with hardcoded
LONG/SHORT timings + 60-entry inline short LUT) with plfm_chirp_controller_v2,
a pure DAC playback driver: IDLE -> CHIRP -> IDLE keyed off a 1-cycle
dst_chirp_valid pulse, with sample count selected by dst_wave_sel
(SHORT=120 / MEDIUM=600 / LONG=3600). Inter-chirp timing (LISTEN, GUARD,
frame boundaries) is now owned exclusively by chirp_scheduler.

Scheduler -> TX bridge: cdc_async_fifo (Cummings style #2, WIDTH=2 DEPTH=4)
crosses {wave_sel} from clk_100m to clk_120m_dac, with chirp_pulse as
src_valid. frame_pulse rides a separate toggle CDC for chirp_counter
clear and the new_chirp_frame status output. mixers_enable now also gates
the scheduler so it stays in S_IDLE while the radar is "off" — without
this gate the first chirp_pulse fires at reset and gets dropped before
mixers come up.

Files:
- NEW  plfm_chirp_controller_v2.v      DAC playback driver (3 LUTs, FSM)
- DEL  plfm_chirp_controller.v         legacy controller (382 lines)
- DEL  long_chirp_lut.mem              legacy LUT (3600 lines), replaced
                                       by tx_long_lut.mem from PR-B
- chirp_scheduler.v       + mixers_enable input (master quiesce)
- radar_receiver_final.v  + sched_*_out output ports + mixers_enable_100m
- radar_system_top.v      wire sched_*_out -> tx_inst.sched_*; pass
                          stm32_mixers_enable_100m to rx_inst
- radar_transmitter.v     full rewrite: drop new_chirp edge detector +
                          toggle CDC, instantiate cdc_async_fifo for
                          {wave_sel}, toggle CDC for frame_pulse,
                          plfm_chirp_controller_v2 in place of _enhanced
- tb/tb_chirp_controller.v  + tb/tb_chirp_contract.v  rewritten for v2
                          contract (43/43 unit + 10/10 contract green)
- tb/tb_radar_receiver_final.v  + .mixers_enable_100m(1'b1) pin
- run_regression.sh, scripts/200t/build_200t.tcl  file-list bumped

Test summary:
- tb_chirp_controller_v2:   43/43 PASS
- tb_chirp_contract:        10/10 contracts upheld
- tb_rxb_fullchain:         peak 24033 ~80x (parity with PR-D)
- tb_mti_canceller:         43/43 PASS
- tb_system_e2e:            33/49 (1 new vs 34/49 PR-D baseline: G2.2
                            new_chirp_frame, intentional v2 frame-pulse
                            semantics — fires once per Doppler frame
                            instead of once per stm32 chirp toggle.
                            TB needs widening in PR-H to wait the full
                            frame.)

9_Firmware/9_2_FPGA/chirp_scheduler.v

@@ -71,6 +71,13 @@ module chirp_scheduler (
     input  wire stm32_new_subframe,
     input  wire stm32_new_frame,
 
+    // Master enable (PR-E). When low, the scheduler holds in S_IDLE and
+    // emits no chirp_pulse — the FSM resumes on the next clock edge after
+    // mixers_enable returns high. Keeps the radar quiet between operator
+    // commands and prevents stale chirp_pulses from being buffered by the
+    // TX-side cdc_async_fifo before mixers come up.
+    input  wire mixers_enable,
+
     // ====== Outputs ======
     output reg  [1:0]  wave_sel,         // canonical waveform identity
     output reg         chirp_pulse,      // 1-cycle pulse: chirp begins this clk
@@ -256,6 +263,15 @@ always @(posedge clk or negedge reset_n) begin
         subframe_id       <= 2'd0;
         track_mode_active <= 1'b0;
         track_remaining   <= 6'd0;
+    end else if (!mixers_enable) begin
+        // Master disable — quiesce the FSM so chirp_pulse never asserts and
+        // the TX side stays at idle. Doesn't disturb track_mode_active so
+        // the host can still observe whether track was last requested.
+        state          <= S_IDLE;
+        timer          <= 17'd0;
+        chirp_pulse    <= 1'b0;
+        subframe_pulse <= 1'b0;
+        frame_pulse    <= 1'b0;
     end else begin
         // Pulses default low — set high for one cycle on relevant transitions.
         chirp_pulse    <= 1'b0;