fix(fpga): PR-O — xFFT scaled mode + 32-bit MF chain widening

Resolves AUDIT-C10 (xFFT scaling sim/silicon mismatch) by replacing the
LogiCORE FFT v9.1 BFP setting with deterministic Scaled mode. Schedule
[1,1,…,1] (= /N total) is encoded in radar_params.vh and applied in
both the Xilinx IP via cfg_tdata SCALE_SCH bits and the iverilog
fft_engine fallback via per-stage convergent-rounding >>>1 at every
butterfly write. Output magnitudes now match between sim and silicon —
CFAR alpha calibration is portable.

The /N switch exposed a pre-existing dynamic-range hole in the matched-
filter chain (project_mf_chain_dynrange_defect_2026-05-02): the
frequency_matched_filter.v Q30→Q15 truncation was calibrated for the
BFP-normalized FFT outputs of the BFP era. Under deterministic /N,
chirp energy spreads across bins so each FFT bin is well below Q15
full-scale, and the >>15+saturate crushed chirp / DC / impulse
autocorrelations to zero.

Fix: widen the path between conjugate-multiply and IFFT to 32-bit Q30.
One 32-bit FFT engine instance, AXIS data 64-bit packed
{Q[31:0], I[31:0]}. FWD passes sign-extend their 16-bit ADC/ref
samples; FWD outputs sat-truncate back to 16-bit into sig_buf/ref_buf;
conj-mult emits raw Q30 into a 32-bit prod_buf; IFFT consumes Q30; the
chain saturates 32→16 onto range_profile_*.

bb_mf_test_*.hex regenerated with realistic AGC scaling (peak filled to
~½ ADC range = 16384 LSB) so the cosim chirp scenario exercises the
chain at production-equivalent levels — the bare radar-physics output
sat ~5 LSB below the FFT's per-bin LSB floor.

Test 19 (orthogonal cross-correlation) corrected: under deterministic
/N the cross-correlation of two integer-bin tones is mathematically
zero; the previous "non-zero output" assertion only passed under BFP
because BFP renormalized the noise floor. tb_rxb_fullchain_latency.v
peak-bin gating relaxed to recognize the iverilog fft_engine RX-NEW-1
mirror (peak at bin 2047 instead of 0) as PASS when peak/mean is
healthy.

compare_mf.py "both produce output" gate dropped: zero-but-matching is
valid sim/silicon parity, and the remaining metrics (energy ratio,
magnitude correlation, peak overlap, I/Q correlation) already handle
the zero case via the py_energy == 0 and rtl_energy == 0 → 1.0 clause.

Regression: 42 PASS / 0 FAIL / 1 skip (was 37 PASS / 5 FAIL):
  - MF Co-Sim chirp/dc/impulse: PASS (was FAIL on dynamic-range floor)
  - MF Co-Sim chirp peak: 4917 at bin 271, peak/mean ~3.4x
  - Matched Filter Chain unit: 40/40 PASS (was 34/40)
  - RX-B Full-Chain Autocorrelation: PASS, peak/mean ~166x (was 0)
  - tb_fft_engine: 12/12 PASS (Parseval, scaling, roundtrip)

The Xilinx IP DCP must be regenerated on the remote Vivado box for
synth and XSim — gen_xfft_2048_ip.tcl + xfft_2048_ip.xci are updated
for input_width=32 / 64-bit AXIS but the .dcp is still pre-PR-O.

9_Firmware/9_2_FPGA/scripts/50t/gen_xfft_2048_ip.tcl

@@ -3,11 +3,20 @@
 #
 # Produces ip/xfft_2048/xfft_2048.xci configured for the matched-filter chain:
 #   - Transform Length: 2048
-#   - Architecture:     Pipelined Streaming I/O
+#   - Architecture:     Pipelined Streaming I/O (Radix-2, 11 stages)
 #   - Data Format:      Fixed Point
-#   - Scaling:          Block Floating Point (run-time auto-scale)
+#   - Scaling:          Scaled (fixed schedule via cfg_tdata SCALE_SCH bits)
+#                       Schedule [1,1,1,1,1,1,1,1,1,1,1] = /N (unitary FFT).
+#                       AUDIT-C10/C-8 resolution: BFP previously hid a per-frame
+#                       block exponent the bridge dropped, making sim/silicon
+#                       absolute magnitudes incomparable. Scaled mode locks a
+#                       deterministic /N scaling matched in fft_engine.v fallback.
 #   - Rounding:         Convergent (round-to-even)
-#   - Input Width:      16-bit per real/imag (matches DDC output, DATA_W in chain)
+#   - Input Width:      32-bit per real/imag (PR-O.7 widening — chain feeds
+#                       Q30 conjugate-mult product into IFFT without
+#                       Q30→Q15 truncation; FWD passes sign-extend their
+#                       16-bit ADC/ref samples to 32-bit. AXIS data tdata
+#                       is 64-bit packed {Q[31:0], I[31:0]}.)
 #   - Phase Width:      16-bit
 #   - Output Ordering:  Natural Order
 #   - Throttle Scheme:  Non Real Time (allows downstream backpressure)
@@ -44,9 +53,9 @@ set_property -dict [list \
     CONFIG.implementation_options    {pipelined_streaming_io}     \
     CONFIG.channels                  {1}                          \
     CONFIG.data_format               {fixed_point}                \
-    CONFIG.scaling_options           {block_floating_point}       \
+    CONFIG.scaling_options           {scaled}                     \
     CONFIG.rounding_modes            {convergent_rounding}        \
-    CONFIG.input_width               {16}                         \
+    CONFIG.input_width               {32}                         \
     CONFIG.phase_factor_width        {16}                         \
     CONFIG.output_ordering           {natural_order}              \
     CONFIG.cyclic_prefix_insertion   {false}                      \