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fix(fpga): C-4 — replace IDDR DDR demux with negedge IFF for AD9484 SDR

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The AD9484 is SDR LVDS — datasheet p.5 lists "Output (LVDS—SDR)" as the
only output mode and p.16 confirms "data outputs are valid on the rising
edge of DCO." DCO runs at fs (400 MHz), one new sample per period, held
stable across the period. There is no DDR mode and no SPI access (CSB is
tied to +1V8 on the production board, RADAR_Main_Board.sch:46719).

ad9484_interface_400m.v previously instantiated an IDDR per data bit and
alternated Q1/Q2 via a `dco_phase` FSM, expecting to demux a "DDR" stream
into 400 MSPS. Because the chip is SDR, both Q1 and Q2 represent the same
sample, and the alternation produced approximately
  [s_{-1}, s_1, s_1, s_3, s_3, s_5, …]
— odd-sample duplication with even-sample loss, equivalent to
decimate-by-2 followed by ZOH-upsample-by-2. In the frequency domain
that's a fold around fs/4 = 100 MHz; our 120-150 MHz IF lands at
50-80 MHz, so the DDC's 120 MHz NCO mixes the wrong frequency and the
matched filter sees baseband 40-70 MHz off where it expects.

The bug was hidden by tb/ad9484_interface_400m_stub.v, which has always
done single-rising-edge SDR-correct capture, so all iverilog regression
ran against the correct semantics — only the synthesizable Xilinx-
primitive path was wrong. This bug only fires on real silicon.

Fix:
- ad9484_interface_400m.v: drop IDDR + dco_phase; capture each data bit
  with a single (* IOB = "TRUE" *) negedge-clocked IFF on adc_dco_bufio.
  Falling DCO sits 1.25 ns inside AD9484's stable window, giving ~0.4 ns
  setup margin against tPD = 0.85 ns. Same pattern on the OR (overrange)
  path. Output FSM now emits one Q per BUFG cycle = clean 400 MSPS.
- tb_ad9484_xsim.v: add Test Group 8 (AUDIT-C4) that drives a 64-sample
  counter ramp synchronously with rising DCO, captures the output, and
  asserts (a) consecutive deltas equal +1 for ≥ (captured-6) of the
  stream, (b) zero duplicate samples (catches DDR-style demux), (c) zero
  unexpected jumps (catches DDR-style sample drops). This locks in SDR
  semantics so any future regression that reintroduces a DDR demux on
  this chip fails loudly.
- ad9484_interface_400m_stub.v: comment-only update — the stub already
  does correct SDR capture; document AUDIT-C4 + why iverilog regression
  was silent on the synth-path bug.
- xc7a200t_fbg484.xdc: fix stale "DDR class" comment near the OR pair
  (now "SDR LVDS").

Verification: bash run_regression.sh — 42 passed, 0 failed, 1 skipped
(the skip is the T-6 drift cosim, which needs scipy from the dev group;
CI installs it via uv sync --group dev). Test Group 8 in the xsim TB
runs against the real UNISIM primitives and is exercised separately on
the Vivado host (run_xfft_xsim.sh-style flow).
This commit is contained in:
Jason
2026-05-01 23:12:55 +05:45
parent abde60dd7e
commit 6f5ff792fa
4 changed files with 174 additions and 91 deletions
Download Patch File Download Diff File Expand all files Collapse all files
9_Firmware/9_2_FPGA/tb/ad9484_interface_400m_stub.v
+10 -2
View File
@@ -5,12 +5,20 @@
// Replaces the real ad9484_interface_400m which uses Xilinx primitives
// (IBUFDS, BUFG, IDDR) that cannot compile in iverilog.
//
// AUDIT-C4 (2026-05-01): AD9484 is SDR LVDS — one new sample per rising
// DCO edge, data stable across the full DCO period. This stub captures
// adc_d_p on the rising edge of adc_dco_p, which already matches the
// chip's SDR semantics. The synthesizable path was rewritten in the same
// audit to route IDDR Q2 only (falling-edge stable capture) instead of
// alternating Q1/Q2 — the previous behaviour produced a 2× duplicated
// output stream that masqueraded as 400 MSPS DDR.
//
// Convention for testbench use:
// - Drive adc_d_p[7:0] with single-ended 8-bit ADC data
// - Drive adc_dco_p with the 400MHz clock (testbench-generated)
// - Drive adc_dco_p with the 400 MHz clock (testbench-generated)
// - adc_d_n and adc_dco_n are ignored
// - adc_dco_bufg = adc_dco_p (pass-through, no BUFG)
// - 1-cycle pipeline latency on data, same as real IDDR+register path
// - 1-cycle pipeline latency on data
// ============================================================================
module ad9484_interface_400m (
9_Firmware/9_2_FPGA/tb/tb_ad9484_xsim.v
+94 -2
View File
@@ -8,10 +8,13 @@
//
// Key things tested:
// 1. Differential LVDS data capture (IBUFDS)
// 2. DDR data capture (IDDR, SAME_EDGE_PIPELINED mode)
// 2. IDDR Q2 (falling-edge) data capture in SAME_EDGE_PIPELINED mode
// 3. Reset synchronizer (P1-7 fix: async assert, sync de-assert)
// 4. Data integrity through full pipeline
// 5. Phase interleaving (rising/falling edge multiplexing)
// 5. AUDIT-C4: SDR-correctness — every rising-DCO sample appears exactly
// once in the output stream (no duplications, no drops). Catches any
// future regression that reintroduces a DDR-style Q1/Q2 demux on this
// SDR-only chip.
// ============================================================================
module tb_ad9484_xsim;
@@ -293,6 +296,95 @@ module tb_ad9484_xsim;
// adc_pwdn is not part of this module (it's in radar_system_top)
// Just verify the module port list is complete
// ════════════════════════════════════════════════════════
// TEST GROUP 8: AUDIT-C4 — SDR-correctness counter ramp
// ════════════════════════════════════════════════════════
// The AD9484 is SDR LVDS: one new sample per rising DCO edge,
// held stable across the full DCO period. We model that by
// launching a new counter value just after each rising DCO
// edge (~tPD = 0.85 ns) and holding it stable. The interface
// captures Q2 of the IDDR (falling-edge, in the stable window)
// and re-registers into BUFG → output.
//
// Correctness invariant: once the pipeline fills, the output
// stream must increment by exactly 1 per BUFG cycle — no
// duplications, no skips. A DDR-style Q1/Q2 demux (the previous
// bug) would emit each sample twice and drop alternating ones,
// which this test catches.
$display("\n--- Test Group 8: SDR Counter Ramp (AUDIT-C4) ---");
reset_n = 0;
adc_d_p = 8'h00;
#100;
reset_n = 1;
repeat (8) @(posedge adc_dco_p);
begin : sdr_ramp
reg [7:0] ramp_value;
reg [7:0] last_out;
reg have_last;
integer captured;
integer diff_one_count;
integer diff_zero_count;
integer diff_other_count;
ramp_value = 8'h10; // start away from 0
have_last = 0;
last_out = 8'h00;
captured = 0;
diff_one_count = 0;
diff_zero_count = 0;
diff_other_count = 0;
// Drive 64 samples in SDR style: launch new value just after
// each rising DCO edge, hold stable. Wrap-around in 8-bit is
// fine (consecutive +1 across 0xFF→0x00 still passes the
// diff-of-1 check).
for (i = 0; i < 64; i = i + 1) begin
@(posedge adc_dco_p);
#0.5; // ≈ AD9484 tPD launch delay
adc_d_p = ramp_value;
ramp_value = ramp_value + 8'd1;
// Sample the output near the next rising edge, after
// the BUFG-domain pipeline has settled.
if (adc_data_valid_400m) begin
if (have_last) begin
case (adc_data_400m - last_out)
8'd1: diff_one_count = diff_one_count + 1;
8'd0: diff_zero_count = diff_zero_count + 1;
default: diff_other_count = diff_other_count + 1;
endcase
end
last_out = adc_data_400m;
have_last = 1;
captured = captured + 1;
end
end
$display(" SDR ramp: captured=%0d diff=+1: %0d diff=0 (dup): %0d other: %0d",
captured, diff_one_count, diff_zero_count, diff_other_count);
// Need a meaningful number of samples to draw conclusions.
check(captured >= 32, "SDR ramp captured >= 32 output samples");
// Most consecutive output deltas must be +1. Allow a small
// slack window for pipeline-startup transients.
check(diff_one_count >= (captured - 6),
"SDR ramp: consecutive output samples increment by +1");
// Zero deltas would indicate the broken DDR-style Q1/Q2
// duplication. With Q2-only routing this should be 0 (allow
// 1 for the very first comparison if pipeline-startup races).
check(diff_zero_count <= 1,
"SDR ramp: no sample duplication (would indicate DDR demux bug)");
// No skips either — the broken demux dropped odd-indexed
// samples (delta == 2). Anything beyond +1/0 is a fail.
check(diff_other_count == 0,
"SDR ramp: no sample skips or unexpected jumps");
end
// ════════════════════════════════════════════════════════
// Summary
// ════════════════════════════════════════════════════════