feat(fpga): swap matched-filter chain to Xilinx LogiCORE FFT v9.1 IP

Replaces the in-house iterative fft_engine.v in the matched-filter chain
with the Pipelined Streaming Xilinx FFT IP, closing RX-NEW-3 (FFT chain
~11x too slow vs PRI budget).

Components:
  * ip/xfft_2048_ip/xfft_2048_ip.xci — committed IP definition
    (16-bit fixed point, BFP scaling, convergent rounding, natural order,
    pipelined-streaming, BRAM data/reorder/phase factors). Vivado
    regenerates .dcp / sim-netlist from this on each build.
  * scripts/50t/gen_xfft_2048_ip.tcl — IP-Catalog generation script
  * scripts/50t/run_xfft_xsim.sh — XSim batch runner for tb_xfft_2048_xsim
  * xfft_2048.v — AXI-Stream wrapper. FFT_USE_XILINX_IP define routes to
    real LogiCORE for synth/XSim; falls back to fft_engine batched
    one-shot for iverilog (unit coverage only).
  * fft_engine_axi_bridge.v — exposes legacy fft_engine port surface on
    top of the xfft_2048 AXI wrapper, so the chain swap is a 1-line
    module-name change.
  * matched_filter_processing_chain.v — fft_engine -> fft_engine_axi_bridge
  * scripts/50t/build_50t.tcl — read_ip + generate_target + synth_ip;
    adds FFT_USE_XILINX_IP to verilog defines.
  * tb/tb_xfft_2048_xsim.v — XSim verification (DC, impulse, tone bin 128).
    All 5 assertions PASS on remote with the real IP; tuser=0x0a (BLK_EXP=10)
    confirms BFP scaling working.

Local iverilog regression: 32/34 PASS — identical to baseline. Same two
RX-NEW-3 failures (Receiver Integration, Matched Filter Chain) — these
only resolve in remote XSim with the real IP, since iverilog uses the
fft_engine fallback inside xfft_2048 (~150K cycles/pass, not the
~2200-cycle Pipelined Streaming throughput). MF cosim 4/4 PASS confirms
bridge bit-exact in fallback mode.

Pending: remote XSim of tb_radar_receiver_final to demonstrate Doppler
frames produced within PRI budget; remote synth to confirm DSP/timing
post-IP.

9_Firmware/9_2_FPGA/run_regression.sh

@@ -69,6 +69,8 @@ PROD_RTL=(
     doppler_processor.v
     xfft_16.v
     fft_engine.v
+    xfft_2048.v
+    fft_engine_axi_bridge.v
     frequency_matched_filter.v
     usb_data_interface.v
     usb_data_interface_ft2232h.v
@@ -102,6 +104,7 @@ RECEIVER_RTL=(
     chirp_memory_loader_param.v latency_buffer.v
     matched_filter_multi_segment.v matched_filter_processing_chain.v
     range_bin_decimator.v doppler_processor.v xfft_16.v fft_engine.v
+    xfft_2048.v fft_engine_axi_bridge.v
     frequency_matched_filter.v
     rx_gain_control.v mti_canceller.v
 )
@@ -282,7 +285,7 @@ run_mf_cosim() {
     if [[ -n "$define" ]]; then
         cmd="$cmd $define"
     fi
-    cmd="$cmd -o $vvp tb/tb_mf_cosim.v matched_filter_processing_chain.v fft_engine.v frequency_matched_filter.v chirp_memory_loader_param.v"
+    cmd="$cmd -o $vvp tb/tb_mf_cosim.v matched_filter_processing_chain.v fft_engine.v xfft_2048.v fft_engine_axi_bridge.v frequency_matched_filter.v chirp_memory_loader_param.v"
 
     if ! eval "$cmd" 2>/tmp/iverilog_err_$$; then
         echo -e "${RED}COMPILE FAIL${NC}"
@@ -640,7 +643,8 @@ run_test "FIR Lowpass" \
 run_test --timeout=600 "Matched Filter Chain" \
     tb/tb_mf_reg.vvp \
     tb/tb_matched_filter_processing_chain.v matched_filter_processing_chain.v \
-    fft_engine.v chirp_memory_loader_param.v frequency_matched_filter.v
+    fft_engine.v xfft_2048.v fft_engine_axi_bridge.v \
+    chirp_memory_loader_param.v frequency_matched_filter.v
 
 # RX-B regression coverage: chain pipeline depth + full-chain
 # autocorrelation peak position. Both run the production fft_engine
@@ -649,12 +653,13 @@ run_test --timeout=600 "Matched Filter Chain" \
 run_test --timeout=120 "RX-B Chain Pipeline Latency (tb_rxb_latency_measure)" \
     tb/tb_rxb_lat_reg.vvp \
     tb/tb_rxb_latency_measure.v matched_filter_processing_chain.v \
-    fft_engine.v frequency_matched_filter.v
+    fft_engine.v xfft_2048.v fft_engine_axi_bridge.v frequency_matched_filter.v
 
 run_test --timeout=600 "RX-B Full-Chain Autocorrelation (tb_rxb_fullchain_latency)" \
     tb/tb_rxb_fc_reg.vvp \
     tb/tb_rxb_fullchain_latency.v matched_filter_multi_segment.v \
-    matched_filter_processing_chain.v fft_engine.v frequency_matched_filter.v \
+    matched_filter_processing_chain.v fft_engine.v xfft_2048.v \
+    fft_engine_axi_bridge.v frequency_matched_filter.v \
     chirp_memory_loader_param.v
 
 echo ""