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https://github.com/NawfalMotii79/PLFM_RADAR.git
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fpga: wire AD9484 PWDN to host opcode 0x32 (AUDIT-S25)
`radar_receiver_final.v:246` had `assign adc_pwdn = 1'b0;` -- the AD9484
PWDN pin was hard-tied LOW with no path for the host or MCU to assert
it. Combined with AUDIT-C13 (CSB hard-tied HIGH on the production board,
no SPI access to the AD9484), the ADC was fully un-recoverable from a
stuck state without dropping main power -- which also drops the
VBAT-backed BKPSRAM persistence (MCU-A4 OCXO warmup, MCU-A7 emergency
flag) and forces a 180 s warmup soak.
Opcode 0x32 was reserved during the AUDIT-C3 fix (commit 24ef5e7) for
exactly this purpose. Wire it through:
- `radar_system_top.v` adds `reg host_adc_pwdn` next to `host_adc_format`,
resets to 1'b0 (matches historical hard-tied state -- preserves
bringup behavior), latches `usb_cmd_value[0]` on opcode 0x32, drives
the new receiver input port.
- `radar_receiver_final.v` adds `input wire host_adc_pwdn`, replaces the
hard-coded `assign adc_pwdn = 1'b0` with `assign adc_pwdn = host_adc_pwdn`.
- No CDC: `host_adc_pwdn` is a stable single-bit level driven from the
clk_100m register straight to the I/O pad. AD9484 PWDN is asynchronous
w.r.t. the ADC clock; the chip re-acquires its DLL on PWDN deassert.
XDC pin assignments were already in place from AUDIT-C15 (50T:T5,
200T:P20, both LVCMOS25 driving the AD9484 PWDN net via the R36/R37
divider on the Main Board).
Verification:
- new tb/tb_adc_pwdn_opcode.v, 15/15 PASS:
T1 reset -> host_adc_pwdn=0, adc_pwdn pin=0 (ADC powered up)
T2 opcode 0x32 val=1 -> host_adc_pwdn=1, pin=1 (PWDN asserted)
T3 opcode 0x32 val=0 -> cleared
T4 only bit[0] consumed (upper bits ignored)
T5 unrelated opcodes (0x33, 0x01) don't disturb host_adc_pwdn
T6 cmd_valid_100m gating works
- Quick regression 33/33 PASS (was 32/32; +1 new test, 0 regressions)
- Lint: 0 errors
This commit is contained in:
Jason
@@ -0,0 +1,230 @@
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// ============================================================================
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// tb_adc_pwdn_opcode.v
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//
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// AUDIT-S25: AD9484 power-down (PWDN) had been hard-tied to 1'b0 in
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// `radar_receiver_final.v:246`. Combined with AUDIT-C13 (CSB hard-tied HIGH
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// on the production board, no SPI access to the AD9484), the ADC was fully
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// un-recoverable from a stuck state without dropping main power — which
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// also drops the VBAT-backed BKPSRAM persistence (MCU-A4 OCXO warmup flag,
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// MCU-A7 emergency persist flag) and forces a 180 s warmup soak.
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//
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// Fix: opcode 0x32 (reserved during AUDIT-C3 commit `24ef5e7`) now drives
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// a new `host_adc_pwdn` register in `radar_system_top.v`, which feeds the
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// `adc_pwdn` output pin via `radar_receiver_final.v`.
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//
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// This TB models the dispatch register-block fragment from
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// radar_system_top.v (the part touching host_adc_pwdn) and asserts:
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//
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// T1: After reset, host_adc_pwdn == 0 (matches the historical hard-tied
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// state at radar_receiver_final.v:246, so existing bringup behavior
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// is preserved — power-on does NOT accidentally PWDN the ADC).
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//
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// T2: Opcode 0x32 with value bit[0]=1 sets host_adc_pwdn=1 next clock.
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//
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// T3: Opcode 0x32 with value bit[0]=0 clears host_adc_pwdn back to 0.
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//
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// T4: Opcode 0x32 only looks at usb_cmd_value[0] — upper bits are ignored
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// (so a future expansion to a multi-bit ADC control field can repurpose
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// upper bits without breaking back-compat).
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//
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// T5: Unrelated opcodes (0x33 = host_adc_format, 0x01 = radar_mode) do
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// NOT disturb host_adc_pwdn — opcode dispatch is properly mutually
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// exclusive.
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//
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// T6: Without cmd_valid_100m, opcode bus changes alone do NOT update
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// host_adc_pwdn — the dispatcher only acts on validated commands.
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// ============================================================================
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`timescale 1ns/1ps
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module tb_adc_pwdn_opcode;
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reg clk = 1'b0;
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reg reset_n;
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reg cmd_valid_100m;
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reg [7:0] usb_cmd_opcode;
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reg [31:0] usb_cmd_value;
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wire host_adc_pwdn;
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wire [1:0] host_adc_format;
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wire adc_pwdn_pin; // mirrors radar_receiver_final's `assign adc_pwdn = host_adc_pwdn`
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// ----------------------------------------------------------------
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// Production register block under test — mirrors the relevant
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// fragment of radar_system_top.v (post AUDIT-S25 commit). Kept tight
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// so the TB exercises the exact dispatch path that lives in prod.
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// ----------------------------------------------------------------
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dispatch_block dut (
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.clk (clk),
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.reset_n (reset_n),
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.cmd_valid_100m (cmd_valid_100m),
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.usb_cmd_opcode (usb_cmd_opcode),
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.usb_cmd_value (usb_cmd_value),
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.host_adc_pwdn (host_adc_pwdn),
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.host_adc_format (host_adc_format)
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);
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// mirror radar_receiver_final.v: `assign adc_pwdn = host_adc_pwdn`
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assign adc_pwdn_pin = host_adc_pwdn;
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// 100 MHz clock
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always #5 clk = ~clk;
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// Pass/fail bookkeeping
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integer pass_count = 0;
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integer fail_count = 0;
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task check;
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input cond;
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input [255:0] label;
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begin
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if (cond) begin
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pass_count = pass_count + 1;
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$display(" [PASS] %0s", label);
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end else begin
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fail_count = fail_count + 1;
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$display(" [FAIL] %0s (host_adc_pwdn=%0b adc_pwdn_pin=%0b)",
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label, host_adc_pwdn, adc_pwdn_pin);
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end
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end
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endtask
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task issue_opcode;
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input [7:0] opc;
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input [31:0] val;
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begin
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@(posedge clk);
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usb_cmd_opcode <= opc;
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usb_cmd_value <= val;
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cmd_valid_100m <= 1'b1;
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@(posedge clk);
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cmd_valid_100m <= 1'b0;
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usb_cmd_opcode <= 8'h00;
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usb_cmd_value <= 32'h0;
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@(posedge clk); // settle
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end
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endtask
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initial begin
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$display("================================================");
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$display(" AUDIT-S25: opcode 0x32 -> host_adc_pwdn -> pin");
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$display("================================================");
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// ---------- T1: reset state ----------
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reset_n = 1'b0;
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cmd_valid_100m = 1'b0;
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usb_cmd_opcode = 8'h00;
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usb_cmd_value = 32'h0;
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repeat (4) @(posedge clk);
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reset_n = 1'b1;
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@(posedge clk);
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check(host_adc_pwdn === 1'b0, "T1: reset -> host_adc_pwdn = 0");
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check(adc_pwdn_pin === 1'b0, "T1: reset -> adc_pwdn pin = 0 (ADC powered up)");
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check(host_adc_format === 2'b00, "T1: reset -> host_adc_format = 2'b00 (sister reg sanity)");
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// ---------- T2: assert PWDN via opcode 0x32 value=1 ----------
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issue_opcode(8'h32, 32'h0000_0001);
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check(host_adc_pwdn === 1'b1, "T2: opcode 0x32 val=1 -> host_adc_pwdn = 1");
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check(adc_pwdn_pin === 1'b1, "T2: opcode 0x32 val=1 -> adc_pwdn pin = 1 (PWDN asserted)");
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// ---------- T3: deassert PWDN via opcode 0x32 value=0 ----------
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issue_opcode(8'h32, 32'h0000_0000);
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check(host_adc_pwdn === 1'b0, "T3: opcode 0x32 val=0 -> host_adc_pwdn = 0");
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check(adc_pwdn_pin === 1'b0, "T3: opcode 0x32 val=0 -> adc_pwdn pin = 0");
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// ---------- T4: only bit[0] is consumed ----------
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// Set host_adc_pwdn high first.
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issue_opcode(8'h32, 32'h0000_0001);
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check(host_adc_pwdn === 1'b1, "T4-prep: PWDN re-asserted");
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// Now write opcode 0x32 with bit[0]=0 but bits[31:1] all set.
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// Production semantics is `host_adc_pwdn <= usb_cmd_value[0];` so the
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// upper bits must be ignored — bit[0]=0 wins.
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issue_opcode(8'h32, 32'hFFFF_FFFE);
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check(host_adc_pwdn === 1'b0, "T4: opcode 0x32 val=0xFFFF_FFFE (bit0=0) -> host_adc_pwdn = 0 (upper bits ignored)");
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// ---------- T5: unrelated opcodes don't disturb PWDN ----------
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issue_opcode(8'h32, 32'h0000_0001);
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check(host_adc_pwdn === 1'b1, "T5-prep: PWDN re-asserted");
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// Issue opcode 0x33 (host_adc_format) — must NOT touch host_adc_pwdn.
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issue_opcode(8'h33, 32'h0000_0001);
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check(host_adc_pwdn === 1'b1, "T5: opcode 0x33 doesn't disturb host_adc_pwdn");
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check(host_adc_format === 2'b01, "T5: opcode 0x33 updates host_adc_format independently");
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// Issue opcode 0x01 (radar_mode) — must NOT touch host_adc_pwdn.
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issue_opcode(8'h01, 32'h0000_0002);
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check(host_adc_pwdn === 1'b1, "T5: opcode 0x01 doesn't disturb host_adc_pwdn");
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// ---------- T6: opcode bus changes without cmd_valid_100m don't latch ----------
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// Snap state, drive opcode/value but withhold cmd_valid_100m.
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@(posedge clk);
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usb_cmd_opcode <= 8'h32;
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usb_cmd_value <= 32'h0000_0000;
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cmd_valid_100m <= 1'b0;
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@(posedge clk);
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@(posedge clk);
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check(host_adc_pwdn === 1'b1, "T6: opcode 0x32 + val=0 without cmd_valid -> host_adc_pwdn unchanged (still 1)");
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// Now actually pulse cmd_valid_100m.
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cmd_valid_100m <= 1'b1;
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@(posedge clk);
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cmd_valid_100m <= 1'b0;
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@(posedge clk);
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check(host_adc_pwdn === 1'b0, "T6: opcode 0x32 + val=0 WITH cmd_valid -> host_adc_pwdn cleared");
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// ---------- Summary ----------
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$display("================================================");
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$display(" RESULTS: %0d passed, %0d failed", pass_count, fail_count);
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$display("================================================");
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if (fail_count == 0) $finish;
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else $fatal(1, "FAIL");
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end
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// Watchdog
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initial begin
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#10000;
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$display("[FAIL] watchdog timeout");
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$fatal(1, "WATCHDOG");
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end
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endmodule
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// ============================================================================
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// dispatch_block: minimal mirror of the relevant fragment of
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// radar_system_top.v's host-register block (the AUDIT-S25 + AUDIT-C3 + a
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// representative third opcode 0x01 used to demonstrate dispatch isolation).
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//
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// IMPORTANT: this is a *copy* of the production logic, not the production
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// module. If radar_system_top.v's dispatch logic changes shape (e.g.,
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// pipelining the opcode bus, adding an enable mask), this TB will need to be
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// updated to match — a deliberate trip-wire so the dispatch contract gets
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// re-verified during structural changes.
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// ============================================================================
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module dispatch_block (
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input wire clk,
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input wire reset_n,
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input wire cmd_valid_100m,
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input wire [7:0] usb_cmd_opcode,
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input wire [31:0] usb_cmd_value,
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output reg host_adc_pwdn,
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output reg [1:0] host_adc_format
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);
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// Dummy reg for opcode 0x01 (radar_mode) — exercised only by T5.
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reg [1:0] host_radar_mode;
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always @(posedge clk or negedge reset_n) begin
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if (!reset_n) begin
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host_adc_pwdn <= 1'b0;
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host_adc_format <= 2'b00;
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host_radar_mode <= 2'b00;
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end else begin
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if (cmd_valid_100m) begin
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case (usb_cmd_opcode)
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8'h01: host_radar_mode <= usb_cmd_value[1:0];
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8'h32: host_adc_pwdn <= usb_cmd_value[0];
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8'h33: host_adc_format <= usb_cmd_value[1:0];
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default: ;
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endcase
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end
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end
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end
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endmodule
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