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https://github.com/NawfalMotii79/PLFM_RADAR.git
synced 2026-06-10 23:41:18 +00:00
AUDIT-C11: replace Gray-CDC at CIC→FIR with home-grown async FIFO
cdc_adc_to_processing carries multi-bit data across 400→100 MHz via TWO independent synchronizer chains (data Gray-encoded + a separate 2-bit toggle). Under metastability, the chains can resolve on different cycles, letting the destination latch a half-resolved Gray word that decodes to an arbitrary value. Audit C-11. Practical MTBF is years per event but the design is non-conformant for arbitrary multi-bit data — Gray code's single-bit-flip protection only holds for ±1 transitions, not for CIC samples that can change by hundreds of LSBs. Replace with cdc_async_fifo, a Cummings SNUG-2002 style #2 async FIFO. Data does NOT cross domains; it sits in dual-clock distRAM (write port src_clk, read port dst_clk). Only the read/write Gray-coded POINTERS cross — and pointers genuinely change ±1 per increment, so Gray code's protection is correct by construction. Home-grown rather than XPM_FIFO_ASYNC: vendor-neutral (iverilog can simulate it directly, no SIM stub), keeps the project's existing home-grown CDC convention (3 sibling primitives in cdc_modules.v), and avoids XPM library version skew. Port shape is preserved (same WIDTH=18, same dst_data/dst_valid/ overrun semantics — 1-cycle pulse per read in steady state) so the swap is local to two instantiations in ddc_400m.v. Sticky-overrun aggregation downstream is unchanged. XDC: project already has blanket set_false_path on clk_100m ↔ adc_dco_p, which covers both new pointer crossings. Synchronizer FFs carry ASYNC_REG="TRUE" for placement-aware MTBF. No XDC change needed. New TB tb_cdc_async_fifo.v exercises 7 groups (28 checks): reset, single-sample passthrough, multi-Gray-bit-flip (0x00000 ↔ 0x3FFFF — audit's recommended coverage point, asserts NO intermediate values appear at dst_data), matched-rate continuous stream, sustained-burst overrun, drain-to-empty, and mid-stream reset. Resource: 8 LUTRAMs per instance × 2 instances = 16 LUTRAMs (~0.05% of XC7A50T budget). Verified: full FPGA regression 42/42 PASS (was 41/41; +1 new test, 0 regressions in DDC Chain / Doppler Co-Sim / Full-Chain Real-Data / Receiver Integration / System Top / System E2E / MF Co-Sim — all of which exercise the swap path through the production signal chain). 0 lint errors.
This commit is contained in:
Jason
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`timescale 1ns / 1ps
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// ============================================================================
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// tb_cdc_async_fifo — exercises the home-grown Cummings async FIFO that
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// replaces cdc_adc_to_processing on the CIC→FIR (400→100 MHz) crossing.
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//
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// Coverage objectives (audit C-11 recommendation):
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// 1. Reset behaviour on both domains.
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// 2. Single sample passthrough (data integrity).
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// 3. Continuous stream at matched src/dst rate (steady-state bandwidth).
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// 4. Multi-Gray-bit-flip stimulus — alternate 0x00000 ↔ 0x3FFFF: each
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// transition flips ALL Gray bits at once, which is exactly the input
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// pattern that exposes the cdc_adc_to_processing skew hazard. This
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// FIFO must never present an intermediate value at dst_data — only
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// the alternating extremes.
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// 5. Sustained burst: src_valid every src_clk cycle (4× the dst drain
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// rate). FIFO fills, overrun pulses, no data corruption on cells
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// already in flight.
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// 6. Drain to empty: after src stops, dst_valid pulses exactly N times
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// for N writes that fit in the FIFO, then dst_valid stays LOW.
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//
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// Clock ratio mirrors production: src=400 MHz, dst=100 MHz (4:1).
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// ============================================================================
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module tb_cdc_async_fifo;
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localparam SRC_CLK_PERIOD = 2.5; // 400 MHz
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localparam DST_CLK_PERIOD = 10.0; // 100 MHz
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localparam WIDTH = 18;
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localparam DEPTH = 16;
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integer pass_count;
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integer fail_count;
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integer test_num;
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task check;
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input cond;
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input [511:0] label;
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begin
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test_num = test_num + 1;
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if (cond) begin
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$display("[PASS] Test %0d: %0s", test_num, label);
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pass_count = pass_count + 1;
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end else begin
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$display("[FAIL] Test %0d: %0s", test_num, label);
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fail_count = fail_count + 1;
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end
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end
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endtask
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// ── DUT signals ───────────────────────────────────────────────
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reg src_clk;
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reg dst_clk;
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reg src_reset_n;
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reg dst_reset_n;
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reg [WIDTH-1:0] src_data;
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reg src_valid;
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wire [WIDTH-1:0] dst_data;
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wire dst_valid;
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wire overrun;
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always #(SRC_CLK_PERIOD/2) src_clk = ~src_clk;
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always #(DST_CLK_PERIOD/2) dst_clk = ~dst_clk;
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cdc_async_fifo #(
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.WIDTH(WIDTH),
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.DEPTH(DEPTH)
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) dut (
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.src_clk (src_clk),
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.dst_clk (dst_clk),
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.src_reset_n (src_reset_n),
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.dst_reset_n (dst_reset_n),
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.src_data (src_data),
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.src_valid (src_valid),
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.dst_data (dst_data),
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.dst_valid (dst_valid),
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.overrun (overrun)
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);
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// ── Captured-output queue (collected on every dst_valid pulse) ────
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reg [WIDTH-1:0] capture_q [0:1023];
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integer capture_n;
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always @(posedge dst_clk) begin
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if (!dst_reset_n) begin
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capture_n <= 0;
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end else if (dst_valid) begin
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capture_q[capture_n] <= dst_data;
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capture_n <= capture_n + 1;
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end
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end
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// ── Overrun pulse counter (src domain) ────────────────────────────
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integer overrun_count;
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always @(posedge src_clk) begin
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if (!src_reset_n) overrun_count <= 0;
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else if (overrun) overrun_count <= overrun_count + 1;
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end
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// ── Helpers ───────────────────────────────────────────────────────
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task drive_sample;
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input [WIDTH-1:0] v;
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begin
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@(posedge src_clk);
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src_data <= v;
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src_valid <= 1'b1;
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@(posedge src_clk);
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src_valid <= 1'b0;
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end
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endtask
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// Drive src_valid HIGH every src_clk cycle for n cycles, with
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// a counter pattern as data so we can verify ordering.
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task drive_burst;
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input integer n;
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input [WIDTH-1:0] base;
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integer k;
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begin
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for (k = 0; k < n; k = k + 1) begin
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@(posedge src_clk);
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src_data <= base + k;
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src_valid <= 1'b1;
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end
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@(posedge src_clk);
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src_valid <= 1'b0;
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end
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endtask
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task wait_dst_cycles;
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input integer n;
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integer k;
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begin
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for (k = 0; k < n; k = k + 1) @(posedge dst_clk);
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end
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endtask
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// ── Main ──────────────────────────────────────────────────────────
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integer i, expected_overrun;
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integer alt_count, intermediate_count;
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initial begin
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$dumpfile("tb_cdc_async_fifo.vcd");
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$dumpvars(0, tb_cdc_async_fifo);
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src_clk = 0;
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dst_clk = 0;
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src_reset_n = 0;
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dst_reset_n = 0;
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src_data = {WIDTH{1'b0}};
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src_valid = 1'b0;
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pass_count = 0;
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fail_count = 0;
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test_num = 0;
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// ════════════════════════════════════════════════════════
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// Group 1: Reset
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// ════════════════════════════════════════════════════════
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$display("\n=== Group 1: Reset ===");
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#100;
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check(dst_valid === 1'b0, "G1.1: dst_valid LOW during reset");
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check(dst_data === {WIDTH{1'b0}}, "G1.2: dst_data 0 during reset");
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check(overrun === 1'b0, "G1.3: overrun LOW during reset");
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// Release dst first (out-of-order reset deassertion is allowed)
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@(posedge dst_clk); dst_reset_n = 1'b1;
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wait_dst_cycles(2);
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check(dst_valid === 1'b0, "G1.4: dst_valid LOW (src still in reset)");
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@(posedge src_clk); src_reset_n = 1'b1;
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wait_dst_cycles(4);
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check(dst_valid === 1'b0, "G1.5: dst_valid LOW after both resets release (FIFO empty)");
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// ════════════════════════════════════════════════════════
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// Group 2: Single sample passthrough
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// ════════════════════════════════════════════════════════
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$display("\n=== Group 2: Single sample passthrough ===");
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capture_n = 0;
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drive_sample(18'h12345);
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wait_dst_cycles(8);
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check(capture_n === 1, "G2.1: exactly 1 sample emitted");
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check(capture_q[0] === 18'h12345, "G2.2: data integrity (0x12345)");
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// ════════════════════════════════════════════════════════
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// Group 3: Multi-Gray-bit-flip stimulus (audit C-11 coverage)
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// Alternate 0x00000 ↔ 0x3FFFF — these two values differ by ALL
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// 18 bits in binary, so Gray code also flips many bits between
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// them. cdc_adc_to_processing's data/toggle skew failure mode
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// would manifest as an intermediate value (anything other than
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// these two). The FIFO must NEVER produce an intermediate.
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// ════════════════════════════════════════════════════════
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$display("\n=== Group 3: Multi-Gray-bit-flip (0x00000 <-> 0x3FFFF) ===");
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capture_n = 0;
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for (i = 0; i < 32; i = i + 1) begin
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drive_sample((i & 1) ? 18'h3FFFF : 18'h00000);
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// small inter-sample gap to let dst drain so FIFO doesn't fill
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wait_dst_cycles(2);
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end
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wait_dst_cycles(16);
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check(capture_n === 32, "G3.1: 32 samples emitted (no drops)");
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intermediate_count = 0;
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alt_count = 0;
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for (i = 0; i < capture_n; i = i + 1) begin
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if (capture_q[i] === 18'h00000 || capture_q[i] === 18'h3FFFF) begin
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alt_count = alt_count + 1;
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end else begin
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intermediate_count = intermediate_count + 1;
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end
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end
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check(intermediate_count === 0,
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"G3.2: NO intermediate values (every sample is 0x00000 or 0x3FFFF)");
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check(alt_count === 32,
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"G3.3: all 32 samples are one of the two extremes");
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// Verify ordering: even index → 0x00000, odd index → 0x3FFFF
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// (sampling order matches src_valid order because FIFO is FIFO)
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for (i = 0; i < capture_n; i = i + 1) begin
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if ((i & 1) ? (capture_q[i] !== 18'h3FFFF)
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: (capture_q[i] !== 18'h00000)) begin
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$display(" [trace] G3 ordering mismatch at index %0d: 0x%h", i, capture_q[i]);
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end
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end
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// Just one summary check on ordering:
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check((capture_q[0] === 18'h00000) && (capture_q[1] === 18'h3FFFF) &&
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(capture_q[30] === 18'h00000) && (capture_q[31] === 18'h3FFFF),
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"G3.4: alternation order preserved across the run");
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// ════════════════════════════════════════════════════════
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// Group 4: Continuous stream — counter pattern, no overrun
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// src writes one sample every 4 src cycles (100 MHz src valid
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// rate, matched to dst drain rate)
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// ════════════════════════════════════════════════════════
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$display("\n=== Group 4: Matched-rate continuous stream ===");
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capture_n = 0;
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overrun_count = 0;
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// Drive 64 samples with 3-cycle gap → 100 MHz effective src rate
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for (i = 0; i < 64; i = i + 1) begin
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@(posedge src_clk); src_data <= i[WIDTH-1:0]; src_valid <= 1'b1;
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@(posedge src_clk); src_valid <= 1'b0;
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@(posedge src_clk);
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@(posedge src_clk);
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end
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wait_dst_cycles(32);
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check(overrun_count === 0, "G4.1: no overrun at matched src/dst rate");
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check(capture_n === 64, "G4.2: all 64 samples passed through");
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check(capture_q[0] === 18'd0, "G4.3: first sample = 0");
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check(capture_q[63] === 18'd63, "G4.4: last sample = 63");
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// Spot-check ordering
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check(capture_q[10] === 18'd10 && capture_q[42] === 18'd42,
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"G4.5: monotonic counter pattern preserved");
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// ════════════════════════════════════════════════════════
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// Group 5: Overrun — sustained burst, src_valid every cycle
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// FIFO has DEPTH=16, drain is 4× slower than fill, so after
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// ~21 src writes the FIFO fills and overrun starts pulsing.
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// ════════════════════════════════════════════════════════
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$display("\n=== Group 5: Burst overrun ===");
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capture_n = 0;
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overrun_count = 0;
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// Wait for dst to fully drain anything pending
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wait_dst_cycles(8);
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@(posedge src_clk);
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drive_burst(64, 18'h10000); // src_valid HIGH for 64 src cycles
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wait_dst_cycles(48); // let FIFO drain
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check(overrun_count > 0, "G5.1: overrun fired during sustained burst");
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// 64 writes; FIFO drains 1 entry per 4 src cycles = 16 drained during burst.
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// So writes that succeed = 16 (in FIFO) + 16 (drained) = ~32; drops = 64-32 = ~32.
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check(capture_n >= 16 && capture_n <= 48,
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"G5.2: capture count in expected range (FIFO depth + drained)");
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// Whatever made it through must be a contiguous prefix-suffix of the
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// counter pattern — first sample MUST be 0x10000 (the burst base);
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// the FIFO never reorders.
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check(capture_q[0] === 18'h10000, "G5.3: first captured sample = burst base");
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// ════════════════════════════════════════════════════════
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// Group 6: Drain to empty + idle behaviour
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// ════════════════════════════════════════════════════════
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$display("\n=== Group 6: Drain + idle ===");
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wait_dst_cycles(64);
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capture_n = 0;
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overrun_count = 0;
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wait_dst_cycles(32);
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check(capture_n === 0, "G6.1: no spurious dst_valid while idle");
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check(dst_valid === 1'b0, "G6.2: dst_valid LOW after drain");
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check(overrun_count === 0, "G6.3: no overrun while idle");
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// Single-shot post-idle write should still work
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drive_sample(18'h2AAAA);
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wait_dst_cycles(8);
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check(capture_n === 1, "G6.4: post-idle single sample emitted");
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check(capture_q[0] === 18'h2AAAA, "G6.5: post-idle data integrity");
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// ════════════════════════════════════════════════════════
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// Group 7: Reset mid-stream — both pointers must zero, dst_valid LOW
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// ════════════════════════════════════════════════════════
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$display("\n=== Group 7: Reset mid-stream ===");
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wait_dst_cycles(8);
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// Pre-load a few samples
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drive_sample(18'h11111);
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drive_sample(18'h22222);
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// Assert reset on both before they drain
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@(posedge dst_clk); dst_reset_n = 1'b0;
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@(posedge src_clk); src_reset_n = 1'b0;
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capture_n = 0;
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wait_dst_cycles(8);
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check(dst_valid === 1'b0, "G7.1: dst_valid LOW under mid-stream reset");
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check(capture_n === 0, "G7.2: no captures during reset");
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// Release
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@(posedge dst_clk); dst_reset_n = 1'b1;
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@(posedge src_clk); src_reset_n = 1'b1;
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wait_dst_cycles(8);
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check(dst_valid === 1'b0, "G7.3: dst_valid LOW after reset release (FIFO empty)");
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// Post-reset write
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drive_sample(18'h3CCCC);
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wait_dst_cycles(8);
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check(capture_q[0] === 18'h3CCCC, "G7.4: post-reset write succeeds");
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// ── Final summary ─────────────────────────────────────────
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$display("\n============================================");
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$display(" RESULTS: %0d passed / %0d failed / %0d total",
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pass_count, fail_count, test_num);
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$display("============================================");
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if (fail_count == 0) $display(" STATUS: ALL TESTS PASSED");
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else $display(" STATUS: FAILURES DETECTED");
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$finish;
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end
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// Watchdog
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initial begin
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#200000;
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$display("[FAIL] WATCHDOG: simulation hung");
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$finish;
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end
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endmodule
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