fix(gui): software_fpga revival post-e8b495c — port chain helpers to fpga_model

Restore SoftwareFPGA's process_chirps() pipeline by porting the missing
chain stages (MTI canceller, DC notch, CFAR, threshold detection) plus
thin wrappers (range FFT, decimator, Doppler FFT) to fpga_model.py and
swapping software_fpga.py's import target from the deleted
golden_reference.py to fpga_model.

History: golden_reference.py was deleted in e8b495c (the "dead golden
code cleanup") but software_fpga.py kept importing from it.  The
ImportError was swallowed at v7/__init__.py:49-52 so package load
succeeded, but every direct `from v7.software_fpga import SoftwareFPGA`
hit the import-time failure — masking 21 broken tests as
"ModuleNotFoundError" instead of surfacing the real issue.

This was actively breaking the GUI replay-from-raw-IQ feature
(dashboard.py:1334-1347, 1577 + GUI_V65_Tk.py:271-300, 1106-1129):
opening a .npy SDR capture instantiates SoftwareFPGA + ReplayEngine;
the dashboard's opcode dual-dispatch routes spinbox changes to the
SoftwareFPGA setters so re-processing reflects live param tweaks.
With the import broken since April, that path silently dies.

fpga_model.py:
- New top-level constants: FFT_SIZE=2048, NUM_RANGE_BINS=512 (from
  RangeBinDecimator.OUTPUT_BINS), DOPPLER_CHIRPS=48,
  DOPPLER_TOTAL_BINS=48 (track current production: PR-O.6 / PR-F).
- run_range_fft(iq_i, iq_q, twiddle_file): N inferred from input
  length; works for legacy 1024-pt and production 2048-pt callers.
- run_range_bin_decimator(range_i, range_q, mode): per-frame wrapper
  over RangeBinDecimator.decimate (4x decim -> 512 bins).
- run_mti_canceller(decim_i, decim_q, enable): 2-pulse canceller,
  ported verbatim from golden_reference @ commit 237e74c~1.
- run_doppler_fft(mti_i, mti_q): num_subframes inferred from chirp
  count; RANGE_BINS overridden per input shape so legacy
  2-sub-frame (32-chirp) and production 3-sub-frame (48-chirp)
  callers both work.
- run_dc_notch(doppler_i, doppler_q, width): per-bin DC notch,
  generalised to any sub-frame count.
- run_cfar_ca(...): CA / GO / SO modes with bit-accurate alpha-q44
  threshold + 17-bit saturation, ported from golden_reference.
- run_detection(doppler_i, doppler_q, threshold): |I|+|Q| L1 magnitude
  threshold detection.

software_fpga.py:
- _GOLDEN_REF_DIR (cosim/real_data/) -> _FPGA_COSIM_DIR (cosim/)
- `from golden_reference import (...)` -> `from fpga_model import (...)`
- TWIDDLE_1024 -> TWIDDLE_2048 (production 2048-pt range FFT).
- Stage 1 comment: "Range bin decimation (1024 -> 64)" ->
  "(production 2048 -> 512)".
- Stage 1 twiddle path picks fft_twiddle_2048.mem only when
  n_samples=2048 matches; otherwise None to fall back to math-
  generated twiddles for legacy callers.
- Module docstring updated to reflect post-cleanup history.

test_v7.py — modernise three tests to current production dimensions:
- test_process_chirps_returns_radar_frame: pad input to 2048 samples;
  assertions reference NUM_RANGE_BINS / NUM_DOPPLER_BINS from
  radar_protocol; n_dop derived from input chirp count.
- test_cfar_enable_changes_detections: 48 chirps x 2048 samples;
  output (NUM_RANGE_BINS, NUM_DOPPLER_BINS).  No longer skips on
  cosim absence — uses synthetic input.
- test_get_frame_raw_iq_synthetic: (2, 48, 2048) raw IQ;
  (NUM_RANGE_BINS, NUM_DOPPLER_BINS) output.
- test_cosim_dir: also skip when doppler_map_*.npy absent (matches
  _cosim_available pattern in TestSoftwareFPGASignalChain).

Local: test_v7 100/0/0 (9 graceful skips: optional deps + missing
cosim .npy data), test_GUI_V65_Tk 117/0/2.  Down from 21 ERRORs.

9_Firmware/9_3_GUI/v7/software_fpga.py

@@ -1,14 +1,22 @@
 """
 v7.software_fpga — Bit-accurate software replica of the AERIS-10 FPGA signal chain.
 
-Imports processing functions directly from golden_reference.py (Option A)
-to avoid code duplication.  Every stage is toggleable via the same host
-register interface the real FPGA exposes, so the dashboard spinboxes can
-drive either backend transparently.
+Imports processing functions directly from fpga_model.py to avoid code
+duplication.  Every stage is toggleable via the same host register
+interface the real FPGA exposes, so the dashboard spinboxes can drive
+either backend transparently during replay-from-raw-IQ.
+
+Signal chain order (matching RTL, post-PR-O.6 / PR-F dimensions —
+2048-pt range FFT, 4x decimation -> 512 range bins, 48 chirps in
+3 sub-frames -> 48 Doppler bins):
 
-Signal chain order (matching RTL):
     quantize → range_fft → decimator → MTI → doppler_fft → dc_notch → CFAR → RadarFrame
 
+History: golden_reference.py was deleted in commit e8b495c (the "dead golden
+code cleanup").  fpga_model.py is the surviving bit-accurate model and
+holds the chain helpers via the run_* shims appended in the post-cleanup
+revival.
+
 Usage:
     fpga = SoftwareFPGA()
     fpga.set_cfar_enable(True)
@@ -25,16 +33,17 @@ from pathlib import Path
 import numpy as np
 
 # ---------------------------------------------------------------------------
-# Import golden_reference by adding the cosim path to sys.path
+# Import chain helpers from fpga_model.py (cosim/) — was golden_reference.py
+# under cosim/real_data/ before commit e8b495c.
 # ---------------------------------------------------------------------------
-_GOLDEN_REF_DIR = str(
+_FPGA_COSIM_DIR = str(
     Path(__file__).resolve().parents[2]  # 9_Firmware/
-    / "9_2_FPGA" / "tb" / "cosim" / "real_data"
+    / "9_2_FPGA" / "tb" / "cosim"
 )
-if _GOLDEN_REF_DIR not in sys.path:
-    sys.path.insert(0, _GOLDEN_REF_DIR)
+if _FPGA_COSIM_DIR not in sys.path:
+    sys.path.insert(0, _FPGA_COSIM_DIR)
 
-from golden_reference import (  # noqa: E402
+from fpga_model import (  # noqa: E402
     run_range_fft,
     run_range_bin_decimator,
     run_mti_canceller,
@@ -53,10 +62,12 @@ from radar_protocol import RadarFrame  # noqa: E402
 log = logging.getLogger(__name__)
 
 # ---------------------------------------------------------------------------
-# Twiddle factor file paths (relative to FPGA root)
+# Twiddle factor file paths (relative to FPGA root).  Production range FFT
+# is 2048-pt (PR-O.6); fpga_model.load_twiddle_rom auto-falls back to
+# math-generated twiddles when a path is None.
 # ---------------------------------------------------------------------------
 _FPGA_DIR = Path(__file__).resolve().parents[2] / "9_2_FPGA"
-TWIDDLE_1024 = str(_FPGA_DIR / "fft_twiddle_1024.mem")
+TWIDDLE_2048 = str(_FPGA_DIR / "fft_twiddle_2048.mem")
 TWIDDLE_16 = str(_FPGA_DIR / "fft_twiddle_16.mem")
 
 # CFAR mode int→string mapping (FPGA register 0x24: 0=CA, 1=GO, 2=SO)
@@ -176,18 +187,20 @@ class SoftwareFPGA:
         n_chirps = iq_i.shape[0]
         n_samples = iq_i.shape[1]
 
-        # --- Stage 1: Range FFT (per chirp) ---
+        # --- Stage 1: Range FFT (per chirp). N is inferred from input length;
+        #     pass a twiddle file only when it matches the input N (defaults
+        #     to math-generated twiddles otherwise).
         range_i = np.zeros((n_chirps, n_samples), dtype=np.int64)
         range_q = np.zeros((n_chirps, n_samples), dtype=np.int64)
-        twiddle_1024 = TWIDDLE_1024 if os.path.exists(TWIDDLE_1024) else None
+        twiddle_path = TWIDDLE_2048 if (n_samples == 2048 and os.path.exists(TWIDDLE_2048)) else None
         for c in range(n_chirps):
             range_i[c], range_q[c] = run_range_fft(
                 iq_i[c].astype(np.int64),
                 iq_q[c].astype(np.int64),
-                twiddle_file=twiddle_1024,
+                twiddle_file=twiddle_path,
             )
 
-        # --- Stage 2: Range bin decimation (1024 → 64) ---
+        # --- Stage 2: Range bin decimation (production 2048 -> 512) ---
         decim_i, decim_q = run_range_bin_decimator(range_i, range_q)
 
         # --- Stage 3: MTI canceller (pre-Doppler, per-chirp) ---