fix(fpga): C-3 — parameterize DDC ADC sign-conversion via host opcode 0x33

The DDC hard-coded an offset-binary->2C subtract on the AD9484 path. The
chip's output format is selected by the SCLK/DFS strap (jumper SJ1 on
RADAR_Main_Board.sch), and CSB is hard-tied HIGH so SPI cannot be used
to confirm or change it from firmware. If the board is assembled with
SJ1 on pins 2-3 (two's-complement), the existing RTL silently mis-
converts every sample.

Add a 2-bit adc_format input to ddc_400m_enhanced (2-FF synchronized
clk_100m -> clk_400m, ASYNC_REG attribute), drive it from a new top-
level register host_adc_format written by host opcode 0x33, and wire
it through radar_receiver_final. Default 2'b00 matches the SJ1 default
strap (offset-binary) and preserves pre-patch behavior. Opcode 0x32 is
intentionally left unused; reserved for the future S-25 fix
(host-driven adc_pwdn).

Tests: tb/tb_ddc_400m.v Test Group 5 — 7 new assertions covering
offset-binary at {0x80, 0x00, 0xFF}, two's-complement at
{0x00, 0x80, 0x7F}, and reserved 2'b10 fallback. 14/14 PASS.

Refs: AUDIT-C3 (DDC offset-binary hardcoded).
Schematic ref: RADAR_Main_Board.sch:46719 (CSB on +1V8_CLOCK_F),
:46845 (SCLK/DFS via SJ1).

9_Firmware/9_3_GUI/radar_protocol.py

@@ -62,6 +62,8 @@ class Opcode(IntEnum):
         0x11  host_long_listen_cycles 0x28-0x2C  AGC control
         0x12  host_guard_cycles      0x30  host_self_test_trigger
         0x13  host_short_chirp_cycles 0x31/0xFF  host_status_request
+        0x33  host_adc_format       (AD9484 SCLK/DFS strap; AUDIT-C3)
+        (0x32 reserved for the future S-25 adc_pwdn host-control fix)
     """
     # --- Basic control (0x01-0x04) ---
     RADAR_MODE          = 0x01  # 2-bit mode select
@@ -102,6 +104,15 @@ class Opcode(IntEnum):
     SELF_TEST_STATUS    = 0x31
     STATUS_REQUEST      = 0xFF
 
+    # --- AD9484 ADC sign-convention (0x33, AUDIT-C3) ---
+    # 2'b00 = offset-binary (default; SJ1 jumper pins 1-2 bridged)
+    # 2'b01 = two's-complement (SJ1 jumper pins 2-3 bridged)
+    # AD9484 CSB is hard-tied HIGH on the Main Board (SPI unavailable);
+    # this opcode lets the host adapt the DDC to the physical strap
+    # without rebuilding the bitstream.
+    # (Opcode 0x32 is reserved for the future AUDIT-S25 adc_pwdn fix.)
+    ADC_FORMAT          = 0x33
+
 
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 # Data Structures