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fix(fpga): C-3 — parameterize DDC ADC sign-conversion via host opcode 0x33

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The DDC hard-coded an offset-binary->2C subtract on the AD9484 path. The
chip's output format is selected by the SCLK/DFS strap (jumper SJ1 on
RADAR_Main_Board.sch), and CSB is hard-tied HIGH so SPI cannot be used
to confirm or change it from firmware. If the board is assembled with
SJ1 on pins 2-3 (two's-complement), the existing RTL silently mis-
converts every sample.

Add a 2-bit adc_format input to ddc_400m_enhanced (2-FF synchronized
clk_100m -> clk_400m, ASYNC_REG attribute), drive it from a new top-
level register host_adc_format written by host opcode 0x33, and wire
it through radar_receiver_final. Default 2'b00 matches the SJ1 default
strap (offset-binary) and preserves pre-patch behavior. Opcode 0x32 is
intentionally left unused; reserved for the future S-25 fix
(host-driven adc_pwdn).

Tests: tb/tb_ddc_400m.v Test Group 5 — 7 new assertions covering
offset-binary at {0x80, 0x00, 0xFF}, two's-complement at
{0x00, 0x80, 0x7F}, and reserved 2'b10 fallback. 14/14 PASS.

Refs: AUDIT-C3 (DDC offset-binary hardcoded).
Schematic ref: RADAR_Main_Board.sch:46719 (CSB on +1V8_CLOCK_F),
:46845 (SCLK/DFS via SJ1).
This commit is contained in:
Jason
2026-04-29 14:18:25 +05:45
parent 4f0b82de6e
commit 24ef5e7251
7 changed files with 159 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files
9_Firmware/9_2_FPGA/tb/tb_ddc_400m.v
+81
View File
@@ -14,6 +14,7 @@ module tb_ddc_400m;
reg [7:0] adc_data;
reg adc_data_valid_i;
reg adc_data_valid_q;
reg [1:0] adc_format; // AUDIT-C3: ADC sign-conversion select
wire signed [17:0] baseband_i;
wire signed [17:0] baseband_q;
wire baseband_valid_i;
@@ -53,6 +54,7 @@ module tb_ddc_400m;
.adc_data (adc_data),
.adc_data_valid_i (adc_data_valid_i),
.adc_data_valid_q (adc_data_valid_q),
.adc_format (adc_format),
.baseband_i (baseband_i),
.baseband_q (baseband_q),
.baseband_valid_i (baseband_valid_i),
@@ -99,6 +101,7 @@ module tb_ddc_400m;
adc_data = 0;
adc_data_valid_i = 0;
adc_data_valid_q = 0;
adc_format = 2'b00; // Default offset-binary
test_mode = 2'b00;
test_phase_inc = 0;
force_saturation = 0;
@@ -221,6 +224,84 @@ module tb_ddc_400m;
$display(" debug_sample_count = %0d", debug_sample_count);
check(debug_sample_count > 0, "Sample counter increments");
// ════════════════════════════════════════════════════════
// TEST GROUP 5: AUDIT-C3 — ADC format selection
//
// Exercises the new opcode-0x33 path that picks offset-binary or 2C
// sign-conversion to match the AD9484 SCLK/DFS strap (SJ1) on the
// Main Board. Probes adc_signed_w via hierarchical reference because
// the wire is internal to the DUT.
//
// Expected pre-DSP values (MIXER_WIDTH=18, ADC_WIDTH=8):
// format=00 (offset-binary), adc=0x80 -> +256 (mid-scale ≈ 0V)
// format=00 (offset-binary), adc=0x00 -> -65280 (full negative)
// format=00 (offset-binary), adc=0xFF -> +65280 (full positive)
// format=01 (2's-complement), adc=0x00 -> 0 (mid-scale 0V)
// format=01 (2's-complement), adc=0x80 -> -65536 (full negative)
// format=01 (2's-complement), adc=0x7F -> +65024 (full positive)
// ════════════════════════════════════════════════════════
$display("\n--- Test Group 5: AUDIT-C3 ADC format selection ---");
reset_n = 0;
adc_data_valid_i = 0;
adc_data_valid_q = 0;
repeat (10) @(posedge clk_400m);
reset_n = 1;
repeat (5) @(posedge clk_400m);
// Offset-binary mid-scale (adc=0x80)
adc_format = 2'b00;
repeat (5) @(posedge clk_400m); // 2-FF sync settle
adc_data = 8'h80;
@(posedge clk_400m); #1;
check(uut.adc_signed_w === 18'sd256,
"format=00 adc=0x80 -> +256 (offset-binary mid-scale)");
// Offset-binary full negative (adc=0x00)
adc_data = 8'h00;
@(posedge clk_400m); #1;
check(uut.adc_signed_w === -18'sd65280,
"format=00 adc=0x00 -> -65280 (offset-binary min)");
// Offset-binary full positive (adc=0xFF)
adc_data = 8'hFF;
@(posedge clk_400m); #1;
check(uut.adc_signed_w === 18'sd65280,
"format=00 adc=0xFF -> +65280 (offset-binary max)");
// Switch to 2's-complement and let the synchronizer settle
adc_format = 2'b01;
repeat (5) @(posedge clk_400m);
// 2's-complement mid-scale (adc=0x00)
adc_data = 8'h00;
@(posedge clk_400m); #1;
check(uut.adc_signed_w === 18'sd0,
"format=01 adc=0x00 -> 0 (2's-complement mid-scale)");
// 2's-complement full negative (adc=0x80)
adc_data = 8'h80;
@(posedge clk_400m); #1;
check(uut.adc_signed_w === -18'sd65536,
"format=01 adc=0x80 -> -65536 (2's-complement min)");
// 2's-complement full positive (adc=0x7F)
adc_data = 8'h7F;
@(posedge clk_400m); #1;
check(uut.adc_signed_w === 18'sd65024,
"format=01 adc=0x7F -> +65024 (2's-complement max)");
// Reserved 2'b1x must fall back to offset-binary
adc_format = 2'b10;
repeat (5) @(posedge clk_400m);
adc_data = 8'h80;
@(posedge clk_400m); #1;
check(uut.adc_signed_w === 18'sd256,
"format=10 (reserved) -> offset-binary fallback");
// Restore default for any later tests
adc_format = 2'b00;
repeat (5) @(posedge clk_400m);
// ════════════════════════════════════════════════════════
// Summary
// ════════════════════════════════════════════════════════
9_Firmware/9_2_FPGA/tb/tb_ddc_cosim.v
+1
View File
@@ -88,6 +88,7 @@ module tb_ddc_cosim;
.adc_data (adc_data),
.adc_data_valid_i (adc_data_valid),
.adc_data_valid_q (adc_data_valid),
.adc_format (2'b00), // AUDIT-C3: offset-binary (cosim baseline)
.baseband_i (baseband_i),
.baseband_q (baseband_q),
.baseband_valid_i (baseband_valid_i),
9_Firmware/9_2_FPGA/tb/tb_radar_receiver_final.v
+2
View File
@@ -173,6 +173,8 @@ radar_receiver_final dut (
// Fix 3: digital gain control — pass-through for golden reference
.host_gain_shift(4'd0),
// AUDIT-C3: ADC format select — offset-binary baseline
.host_adc_format(2'b00),
// CFAR: frame-complete output (not used in this TB)
.doppler_frame_done_out()
);