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PR-AB.b expanded commit 1: RTL strip (dead modes + counters + range_mode)

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Flatten chirp_scheduler.v to single-FSM auto-scan. Mode 00 (STM32 pass-through),
mode 10 (single-chirp debug) and mode 11 (track dwell) FSM branches were all
half-implemented and unreachable in production: MCU dispatcher was deleted in
F-2.1; mode 11 inputs were tied to constants in radar_receiver_final; mode 10
debug_wave_sel was hardcoded to SHORT. The case-switch wrapper, watchdog,
effective_mode mux, and all host_track_* / host_debug_wave_sel / host_trigger
plumbing are removed.

Strip host_radar_mode (opcode 0x01), host_trigger_pulse (opcode 0x02), and
host_range_mode (opcode 0x20). The mode register had no consumer after the
single-mode flatten; the range_mode register was already write-only telemetry
(declared as input in radar_receiver_final but never read). The runtime 3km vs
20km presentation on a 200T build is driven by host_subframe_enable (0x19) +
per-waveform chirp/listen cycles (0x10-0x18) — no separate mode field needed.

Strip stm32_new_elevation / stm32_new_azimuth GPIOs and the elevation_counter /
azimuth_counter regs in plfm_chirp_controller_v2. The FPGA-side counters had no
consumer (status pack never carried them; on 50T they went to _nc; on 200T to
unconstrained outputs). MCU software counters n/y reach the GUI via USB-CDC
on a separate channel.

USB status word 0 bits [23:22] (was radar_mode) and word 4 bits [1:0] (was
range_mode) are now reserved zeros — host parser keeps the same byte offsets.

Files modified:
  chirp_scheduler.v               - flatten to single FSM (~155 LOC delta)
  plfm_chirp_controller_v2.v      - strip counter blocks + ports
  radar_transmitter.v             - strip elev/azim CDC + edge detectors + ports
  radar_receiver_final.v          - strip host_mode/range_mode/trigger + STM32 toggle ports
  radar_system_top.v              - strip regs, opcodes 0x01/0x02/0x20, status_*_mode wiring, top-level ports
  radar_system_top_50t.v          - strip _nc wires + stm32_new_elev/azim + tie-offs
  radar_system_top_te0713_umft601x_dev.v - strip status_radar_mode/range_mode ties
  usb_data_interface.v            - drop status_*_mode ports, reserve word 0 [23:22] + word 4 [1:0]
  usb_data_interface_ft2232h.v    - same as above
  radar_params.vh                 - strip RP_MODE_* / RP_RANGE_MODE_* / RP_OP_RADAR_MODE / RP_OP_TRIGGER_PULSE / RP_OP_RANGE_MODE / RP_DEF_TRACK_*

Regression will fail at this commit due to TB references to deleted signals
(host_radar_mode, status_range_mode, etc.) — TB cleanup follows in commit 2.
This commit is contained in:
Jason
2026-05-11 10:24:20 +05:45
parent a718e00475
commit 1b2a21d55b
10 changed files with 127 additions and 565 deletions
Download Patch File Download Diff File Expand all files Collapse all files
9_Firmware/9_2_FPGA/chirp_scheduler.v
+57 -280
View File
@@ -3,32 +3,26 @@
`include "radar_params.vh"
/**
* chirp_scheduler.v (chirp-v2 PR-D, replaces radar_mode_controller.v)
* chirp_scheduler.v
*
* Single source of truth for waveform identity and inter-chirp timing on the
* RX side. Drives `wave_sel[1:0]` and `chirp_pulse` natively; downstream
* modules (chirp_reference_rom, matched_filter_multi_segment, mti_canceller)
* consume those without 1-bit shims.
*
* Operating modes (host_radar_mode, opcode 0x01):
* 2'b00 STM32 pass-through STM32 owns chirp timing; we follow stm32_*
* toggles and announce the wave_sel that matches
* the current sub-frame index.
* 2'b01 Auto-scan Internal FSM cycles SHORT, MEDIUM, LONG sub-
* frames in order (host_subframe_enable masks
* individual waveforms out without recompiling).
* Each sub-frame fires `host_chirps_per_subframe`
* chirps at the per-waveform timing.
* 2'b10 Single-chirp debug One chirp per host_trigger pulse, waveform
* from host_debug_wave_sel.
* 2'b11 Track Host-cued dwell on one beam + one waveform
* for host_track_chirp_count chirps. A watchdog
* falls back to mode 01 after
* RP_DEF_TRACK_WATCHDOG_FRAMES idle frames so a
* USB-yank does not silently drop coverage.
* Operation: FPGA-paced auto-scan over the enabled sub-frames (SHORT, MEDIUM,
* LONG). `host_subframe_enable[2:0]` masks individual waveforms out without
* recompiling. Each sub-frame fires `host_chirps_per_subframe` chirps at the
* per-waveform chirp/listen-cycle setpoints.
*
* The legacy multi-mode field (STM32 pass-through / single-chirp debug /
* track dwell) was retired in PR-AB.b expanded (2026-05-11). All three
* dead branches plus their host_* inputs (host_mode, host_trigger,
* host_debug_wave_sel, host_track_*) and the track watchdog were stripped
* — see project_aeris10_mode_strip_2026-05-11.md for rationale.
*
* Pulse outputs (chirp_pulse, subframe_pulse, frame_pulse) are 1-cycle
* positive pulses, not toggles. The legacy mc_new_*-style toggles are gone.
* positive pulses, not toggles.
*
* Clock domain: clk (100 MHz), async-low reset.
*/
@@ -37,8 +31,7 @@ module chirp_scheduler (
input wire clk,
input wire reset_n,
// Top-level mode and 3-bit sub-frame enable mask (LONG|MEDIUM|SHORT)
input wire [1:0] host_mode,
// 3-bit sub-frame enable mask (LONG|MEDIUM|SHORT)
input wire [2:0] host_subframe_enable,
// 3-ladder timing (100 MHz cycles). host_*_listen sums with host_guard
@@ -55,22 +48,6 @@ module chirp_scheduler (
// Frame structure (chirps per Doppler sub-frame, default 16)
input wire [5:0] host_chirps_per_subframe,
// Single-chirp debug (mode 10)
input wire host_trigger,
input wire [1:0] host_debug_wave_sel,
// Track mode (mode 11)
input wire host_track_request,
input wire [1:0] host_track_wave_sel,
input wire [8:0] host_track_chirp_count,
input wire [5:0] host_track_beam_az,
input wire [5:0] host_track_beam_el,
// STM32 pass-through (mode 00) toggle inputs (CDC-synced upstream)
input wire stm32_new_chirp,
input wire stm32_new_subframe,
input wire stm32_new_frame,
// Master enable (PR-E). When low, the scheduler holds in S_IDLE and
// emits no chirp_pulse — the FSM resumes on the next clock edge after
// mixers_enable returns high. Keeps the radar quiet between operator
@@ -89,45 +66,9 @@ module chirp_scheduler (
// Currently selected timing for the in-flight chirp (PR-E TX async FIFO)
output wire [15:0] cfg_chirp_cycles,
output wire [15:0] cfg_listen_cycles,
output wire [15:0] cfg_guard_cycles,
// Track-mode beam pointer (latched on host_track_request rising edge)
output reg track_mode_active,
output reg [5:0] track_beam_az,
output reg [5:0] track_beam_el
output wire [15:0] cfg_guard_cycles
);
// ============================================================================
// Edge / pulse detection on async inputs
// ============================================================================
reg trigger_prev;
reg track_request_prev;
reg stm32_new_chirp_prev;
reg stm32_new_subframe_prev;
reg stm32_new_frame_prev;
wire trigger_pulse = host_trigger & ~trigger_prev;
wire track_request_pulse = host_track_request & ~track_request_prev;
wire stm32_chirp_edge = stm32_new_chirp ^ stm32_new_chirp_prev;
wire stm32_subframe_edge = stm32_new_subframe ^ stm32_new_subframe_prev;
wire stm32_frame_edge = stm32_new_frame ^ stm32_new_frame_prev;
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
trigger_prev <= 1'b0;
track_request_prev <= 1'b0;
stm32_new_chirp_prev <= 1'b0;
stm32_new_subframe_prev <= 1'b0;
stm32_new_frame_prev <= 1'b0;
end else begin
trigger_prev <= host_trigger;
track_request_prev <= host_track_request;
stm32_new_chirp_prev <= stm32_new_chirp;
stm32_new_subframe_prev <= stm32_new_subframe;
stm32_new_frame_prev <= stm32_new_frame;
end
end
// ============================================================================
// Sub-frame helpers — pure functions of (subframe, mask)
// ============================================================================
@@ -169,39 +110,6 @@ function [1:0] subframe_to_wave;
end
endfunction
// ============================================================================
// Track watchdog — count frames since last host_track_request rising edge.
// effective_mode collapses to scan once the watchdog expires so a USB stall
// does not silently freeze coverage on one beam.
// ============================================================================
reg [7:0] track_idle_frames;
wire watchdog_expired = (track_idle_frames >= `RP_DEF_TRACK_WATCHDOG_FRAMES);
wire [1:0] effective_mode = (host_mode == `RP_MODE_TRACK && watchdog_expired)
? `RP_MODE_AUTO_3KM
: host_mode;
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
track_idle_frames <= 8'd0;
end else if (track_request_pulse) begin
track_idle_frames <= 8'd0;
end else if (frame_pulse && track_idle_frames != 8'hFF) begin
track_idle_frames <= track_idle_frames + 8'd1;
end
end
// Latch beam pointer at the start of every track dwell.
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
track_beam_az <= 6'd0;
track_beam_el <= 6'd0;
end else if (track_request_pulse) begin
track_beam_az <= host_track_beam_az;
track_beam_el <= host_track_beam_el;
end
end
// ============================================================================
// Output mux for selected timing — wave_sel drives chirp/listen window length.
// guard is shared across waveforms.
@@ -233,7 +141,7 @@ assign cfg_listen_cycles = sel_listen_cycles;
assign cfg_guard_cycles = host_guard_cycles;
// ============================================================================
// Main FSM
// Main FSM — auto-scan over enabled sub-frames.
// ============================================================================
localparam S_IDLE = 3'd0;
localparam S_CHIRP = 3'd1;
@@ -243,7 +151,6 @@ localparam S_ADVANCE = 3'd4;
reg [2:0] state;
reg [16:0] timer; // 17 bits cover LONG+listen+guard worst case
reg [5:0] track_remaining; // saturated copy of host_track_chirp_count
// Pre-computed wires used inside the FSM advance logic so non-blocking
// updates to subframe_id / wave_sel see the correct next value in the same
@@ -253,20 +160,17 @@ wire [1:0] next_sf = next_enabled_subframe(subframe_id, host_subframe_enable);
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
state <= S_IDLE;
timer <= 17'd0;
wave_sel <= `RP_WAVE_SHORT;
chirp_pulse <= 1'b0;
subframe_pulse <= 1'b0;
frame_pulse <= 1'b0;
chirp_counter <= 6'd0;
subframe_id <= 2'd0;
track_mode_active <= 1'b0;
track_remaining <= 6'd0;
state <= S_IDLE;
timer <= 17'd0;
wave_sel <= `RP_WAVE_SHORT;
chirp_pulse <= 1'b0;
subframe_pulse <= 1'b0;
frame_pulse <= 1'b0;
chirp_counter <= 6'd0;
subframe_id <= 2'd0;
end else if (!mixers_enable) begin
// Master disable — quiesce the FSM so chirp_pulse never asserts and
// the TX side stays at idle. Doesn't disturb track_mode_active so
// the host can still observe whether track was last requested.
// the TX side stays at idle.
state <= S_IDLE;
timer <= 17'd0;
chirp_pulse <= 1'b0;
@@ -278,22 +182,38 @@ always @(posedge clk or negedge reset_n) begin
subframe_pulse <= 1'b0;
frame_pulse <= 1'b0;
case (effective_mode)
// --------------------------------------------------------------------
// MODE 00 — STM32 pass-through. STM32 owns chirp timing; we walk
// sub-frames in step with stm32_chirp_edge so wave_sel always matches
// the chirp the firmware just fired.
// --------------------------------------------------------------------
`RP_MODE_STM32_PASSTHROUGH: begin
state <= S_IDLE;
timer <= 17'd0;
track_mode_active <= 1'b0;
if (stm32_chirp_edge) begin
chirp_pulse <= 1'b1;
case (state)
S_IDLE: begin
timer <= 17'd0;
chirp_counter <= 6'd0;
subframe_id <= first_sf;
wave_sel <= subframe_to_wave(first_sf);
chirp_pulse <= 1'b1;
state <= S_CHIRP;
end
S_CHIRP: begin
if (timer + 17'd1 >= {1'b0, sel_chirp_cycles}) begin
timer <= 17'd0;
state <= S_LISTEN;
end else timer <= timer + 17'd1;
end
S_LISTEN: begin
if (timer + 17'd1 >= {1'b0, sel_listen_cycles}) begin
timer <= 17'd0;
state <= S_GUARD;
end else timer <= timer + 17'd1;
end
S_GUARD: begin
if (timer + 17'd1 >= {1'b0, host_guard_cycles}) begin
timer <= 17'd0;
state <= S_ADVANCE;
end else timer <= timer + 17'd1;
end
S_ADVANCE: begin
if (chirp_counter < host_chirps_per_subframe - 6'd1) begin
chirp_counter <= chirp_counter + 6'd1;
chirp_pulse <= 1'b1;
state <= S_CHIRP;
end else begin
chirp_counter <= 6'd0;
subframe_pulse <= 1'b1;
@@ -301,154 +221,11 @@ always @(posedge clk or negedge reset_n) begin
wave_sel <= subframe_to_wave(next_sf);
if (next_sf == first_sf)
frame_pulse <= 1'b1;
chirp_pulse <= 1'b1;
state <= S_CHIRP;
end
end
// STM32 firmware can pulse subframe/frame toggles directly when it
// wants to force-advance (e.g. abort current sub-frame). These
// override the chirp-driven walk above.
if (stm32_subframe_edge) subframe_pulse <= 1'b1;
if (stm32_frame_edge) frame_pulse <= 1'b1;
end
// --------------------------------------------------------------------
// MODE 01 — Auto-scan over enabled sub-frames.
// --------------------------------------------------------------------
`RP_MODE_AUTO_3KM: begin
track_mode_active <= 1'b0;
case (state)
S_IDLE: begin
timer <= 17'd0;
chirp_counter <= 6'd0;
subframe_id <= first_sf;
wave_sel <= subframe_to_wave(first_sf);
chirp_pulse <= 1'b1;
state <= S_CHIRP;
end
S_CHIRP: begin
if (timer + 17'd1 >= {1'b0, sel_chirp_cycles}) begin
timer <= 17'd0;
state <= S_LISTEN;
end else timer <= timer + 17'd1;
end
S_LISTEN: begin
if (timer + 17'd1 >= {1'b0, sel_listen_cycles}) begin
timer <= 17'd0;
state <= S_GUARD;
end else timer <= timer + 17'd1;
end
S_GUARD: begin
if (timer + 17'd1 >= {1'b0, host_guard_cycles}) begin
timer <= 17'd0;
state <= S_ADVANCE;
end else timer <= timer + 17'd1;
end
S_ADVANCE: begin
if (chirp_counter < host_chirps_per_subframe - 6'd1) begin
chirp_counter <= chirp_counter + 6'd1;
chirp_pulse <= 1'b1;
state <= S_CHIRP;
end else begin
chirp_counter <= 6'd0;
subframe_pulse <= 1'b1;
subframe_id <= next_sf;
wave_sel <= subframe_to_wave(next_sf);
if (next_sf == first_sf)
frame_pulse <= 1'b1;
chirp_pulse <= 1'b1;
state <= S_CHIRP;
end
end
default: state <= S_IDLE;
endcase
end
// --------------------------------------------------------------------
// MODE 10 — Single-chirp debug. One chirp per host_trigger.
// --------------------------------------------------------------------
`RP_MODE_SINGLE_DEBUG: begin
track_mode_active <= 1'b0;
case (state)
S_IDLE: begin
timer <= 17'd0;
if (trigger_pulse) begin
wave_sel <= host_debug_wave_sel;
chirp_pulse <= 1'b1;
state <= S_CHIRP;
end
end
S_CHIRP: begin
if (timer + 17'd1 >= {1'b0, sel_chirp_cycles}) begin
timer <= 17'd0;
state <= S_LISTEN;
end else timer <= timer + 17'd1;
end
S_LISTEN: begin
if (timer + 17'd1 >= {1'b0, sel_listen_cycles}) begin
timer <= 17'd0;
state <= S_IDLE;
end else timer <= timer + 17'd1;
end
default: state <= S_IDLE;
endcase
end
// --------------------------------------------------------------------
// MODE 11 — Track dwell. Watchdog fallback handled by effective_mode.
// --------------------------------------------------------------------
`RP_MODE_TRACK: begin
track_mode_active <= 1'b1;
case (state)
S_IDLE: begin
timer <= 17'd0;
if (track_request_pulse) begin
wave_sel <= host_track_wave_sel;
// chirp_counter is 6 bits; clip the dwell length to
// avoid wrapping inside a single dwell.
track_remaining <= (host_track_chirp_count > 9'd63)
? 6'd63
: host_track_chirp_count[5:0];
chirp_counter <= 6'd0;
chirp_pulse <= 1'b1;
state <= S_CHIRP;
end
end
S_CHIRP: begin
if (timer + 17'd1 >= {1'b0, sel_chirp_cycles}) begin
timer <= 17'd0;
state <= S_LISTEN;
end else timer <= timer + 17'd1;
end
S_LISTEN: begin
if (timer + 17'd1 >= {1'b0, sel_listen_cycles}) begin
timer <= 17'd0;
state <= S_GUARD;
end else timer <= timer + 17'd1;
end
S_GUARD: begin
if (timer + 17'd1 >= {1'b0, host_guard_cycles}) begin
timer <= 17'd0;
state <= S_ADVANCE;
end else timer <= timer + 17'd1;
end
S_ADVANCE: begin
if (chirp_counter < track_remaining) begin
chirp_counter <= chirp_counter + 6'd1;
chirp_pulse <= 1'b1;
state <= S_CHIRP;
end else begin
// Dwell complete = one track frame. Watchdog ticks
// here on every dwell; host re-pulsing track_request
// resets it.
frame_pulse <= 1'b1;
chirp_counter <= 6'd0;
state <= S_IDLE;
end
end
default: state <= S_IDLE;
endcase
end
default: state <= S_IDLE;
endcase
end
end