fix(fpga): PR-O.8.1 — drop stale BFP-era ports, fix xsim include path

Wrapper xfft_2048.v had m_axis_data_tuser and m_axis_status_{tdata,tvalid,
tready} hooked up to the IP, but the regenerated xfft_2048_ip in scaled
mode + Pipelined Streaming + 1 channel + no XK_INDEX/OVFLO doesn't expose
those ports. xelab errored "cannot find port" on all four. Removed.

run_xfft_xsim.sh missed -i "$PROJ_ROOT" so xvlog couldn't resolve
`include "radar_params.vh"` from inside tb/. Fixed.

gen_xfft_2048_ip.tcl header comment described the old Burst I/O 11-stage
schedule; updated to PG109 Pipelined Streaming pair-grouped layout that
matches the actual SCALE_SCH = 12'hAA9 we now drive.

Verified: tb_xfft_2048_xsim 5/5 PASS on real LogiCORE FFT v9.1 IP under
Vivado 2025.2 xsim — DC peak at bin 0, impulse flat spectrum, tone at
bin 128. Closes T-10 (FFT-block synth-mode validation).

9_Firmware/9_2_FPGA/scripts/50t/gen_xfft_2048_ip.tcl

@@ -6,7 +6,9 @@
 #   - Architecture:     Pipelined Streaming I/O (Radix-2, 11 stages)
 #   - Data Format:      Fixed Point
 #   - Scaling:          Scaled (fixed schedule via cfg_tdata SCALE_SCH bits)
-#                       Schedule [1,1,1,1,1,1,1,1,1,1,1] = /N (unitary FFT).
+#                       Schedule = 12'hAA9 (PG109 Pipelined Streaming layout):
+#                       stage 1 alone >>1, stages 2-3, 4-5, 6-7, 8-9, 10-11
+#                       grouped each >>2 (per pair). Total = /N = unitary FFT.
 #                       AUDIT-C10/C-8 resolution: BFP previously hid a per-frame
 #                       block exponent the bridge dropped, making sim/silicon
 #                       absolute magnitudes incomparable. Scaled mode locks a

9_Firmware/9_2_FPGA/scripts/50t/run_xfft_xsim.sh

@@ -23,8 +23,9 @@ mkdir -p "$WORK_DIR"
 cd "$WORK_DIR"
 
 echo "===== Compiling Verilog sources ====="
-# Wrapper + testbench with the IP-on define
-xvlog -d FFT_USE_XILINX_IP "$WRAPPER" "$TB"
+# Wrapper + testbench with the IP-on define. -i adds the FPGA root so
+# `include "radar_params.vh"` resolves from inside tb/.
+xvlog -d FFT_USE_XILINX_IP -i "$PROJ_ROOT" "$WRAPPER" "$TB"
 # IP simulation netlist — references unisim primitives
 xvlog "$IP_NETLIST"
 # fft_engine etc. NOT needed because FFT_USE_XILINX_IP routes around it,