From 0100967eac07723cad56b7cac34204c61f204218 Mon Sep 17 00:00:00 2001
From: Jason <83615043+JJassonn69@users.noreply.github.com>
Date: Tue, 5 May 2026 12:15:15 +0545
Subject: [PATCH] =?UTF-8?q?fix(fpga):=20PR-X.1=20F-7.7=20=E2=80=94=20wire?=
 =?UTF-8?q?=20AD9484=20OR=20sticky=20to=20shared=20clear=20pulse?=
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Stage-7 ADC chain audit. radar_receiver_final.v's
adc_overrange_sticky_400m had no clear path other than full system
reset_n — once latched, the only way to acknowledge the AD9484
overrange flag was a reboot. The DDC's analogous diagnostic flags
(cdc_cic_fir_overrun_sticky, mixer_saturation) already clear on the
DDC's `reset_monitors` port; the OR sticky in the receiver wrapper
was the lone outlier.

Introduce a shared `clear_monitors_pulse` wire at the receiver scope
and route it both to the OR sticky's clear branch and to the DDC's
`reset_monitors` port (replacing the literal `1'b0`). Today the
wire is tied 1'b0, preserving the prior reset_n-only behaviour bit-
for-bit. When a future host opcode for "clear diagnostic stickies"
lands, both the receiver-level OR sticky and the DDC's internal
sticky flags clear from the same pulse — no per-flag re-plumbing.

Local FPGA regression 36/1/6 unchanged (1 FAIL = pre-existing T-6
drift, deferred PR-M.4).
---
 9_Firmware/9_2_FPGA/radar_receiver_final.v | 28 +++++++++++++++++-----
 1 file changed, 22 insertions(+), 6 deletions(-)

diff --git a/9_Firmware/9_2_FPGA/radar_receiver_final.v b/9_Firmware/9_2_FPGA/radar_receiver_final.v
index b8b0fb7..3df4df1 100644
--- a/9_Firmware/9_2_FPGA/radar_receiver_final.v
+++ b/9_Firmware/9_2_FPGA/radar_receiver_final.v
@@ -320,14 +320,27 @@ ad9484_interface_400m adc (
 	.mmcm_locked()
 );
 
-// Audit F-0.1: stickify the 400 MHz OR pulse, then CDC to clk_100m via 2FF.
-// Same reasoning as ddc_cic_fir_overrun: single-bit, low→high-only once
-// latched, so a 2FF sync is sufficient for a GPIO-class diagnostic. Cleared
-// only by global reset_n.
-reg adc_overrange_sticky_400m;
+// Audit F-0.1 / F-7.7: stickify the 400 MHz OR pulse, then CDC to clk_100m
+// via 2FF. Single-bit, low→high-only once latched, so a 2FF sync is
+// sufficient for a GPIO-class diagnostic.
+//
+// F-7.7 fix: clear path now follows the same `clear_monitors_pulse` wire
+// as the DDC's `reset_monitors` port (see ddc instance below). Today
+// clear_monitors_pulse is tied 1'b0, matching the prior reset_n-only
+// behaviour; once a host opcode for "clear diagnostic stickies" lands,
+// both this OR sticky and the DDC's overrun/saturation flags clear from
+// the same edge — no per-flag re-plumbing needed.
+//
+// Compare with ddc_400m.v `cdc_cic_fir_overrun_sticky` which already
+// uses reset_monitors as a clear, and the new symmetric path here keeps
+// the AD9484 overrange diagnostic consistent.
+wire clear_monitors_pulse = 1'b0;   // future host-driven clear hook
+reg  adc_overrange_sticky_400m;
 always @(posedge clk_400m or negedge reset_n) begin
     if (!reset_n)
         adc_overrange_sticky_400m <= 1'b0;
+    else if (clear_monitors_pulse)
+        adc_overrange_sticky_400m <= 1'b0;
     else if (adc_overrange_400m)
         adc_overrange_sticky_400m <= 1'b1;
 end
@@ -391,7 +404,10 @@ ddc_400m_enhanced ddc(
     .test_mode(2'b00),
     .test_phase_inc(16'h0000),
     .force_saturation(1'b0),
-    .reset_monitors(1'b0),
+    // F-7.7: routed through the shared clear_monitors_pulse wire so the
+    // DDC's internal stickies and the AD9484 OR sticky above clear from
+    // the same future host opcode.
+    .reset_monitors(clear_monitors_pulse),
     .debug_sample_count(),
     .debug_internal_i(),
     .debug_internal_q(),